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X-CSE-ConnectionGUID: GwKHmzT4TZWNj+oV/a3wSw== X-CSE-MsgGUID: tT6fHqo3QCKIm0EpWSKOUA== X-IronPort-AV: E=McAfee;i="6800,10657,11602"; a="81767548" X-IronPort-AV: E=Sophos;i="6.19,279,1754982000"; d="scan'208";a="81767548" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2025 06:26:59 -0800 X-CSE-ConnectionGUID: D7xvNA+0R76wWmLtoIviIw== X-CSE-MsgGUID: U6CJ0f+XSuGRaR1jIIer7w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,279,1754982000"; d="scan'208";a="186857506" Received: from jmaxwel1-mobl.amr.corp.intel.com (HELO [10.125.110.166]) ([10.125.110.166]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2025 06:26:58 -0800 Message-ID: <47b3e8ba-bc95-41ce-be0a-ddfd1323bab3@intel.com> Date: Tue, 4 Nov 2025 06:26:58 -0800 Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/2] x86/mm: support memory-failure on 32-bits with SPARSEMEM To: Xie Yuanbin , david@redhat.com, bp@alien8.de, tglx@linutronix.de, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, akpm@linux-foundation.org, lorenzo.stoakes@oracle.com, Liam.Howlett@oracle.com, vbabka@suse.cz, rppt@kernel.org, surenb@google.com, mhocko@suse.com, linmiaohe@huawei.com, nao.horiguchi@gmail.com, luto@kernel.org, peterz@infradead.org, tony.luck@intel.com Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-edac@vger.kernel.org, will@kernel.org, liaohua4@huawei.com, lilinjie8@huawei.com References: <20251104072306.100738-1-xieyuanbin1@huawei.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/3/25 23:23, Xie Yuanbin wrote: > Memory bit flips are among the most common hardware errors in the server > and embedded fields, many hardware components have memory verification > mechanisms, for example ECC. When an error is detected, some hardware or > architectures report the information to software (OS/BIOS), for example, > the MCE (Machine Check Exception) on x86. > > Common errors include CE (Correctable Errors) and UE (Uncorrectable > Errors). When the kernel receives memory error information, if it has the > memory-failure feature, it can better handle memory errors without reboot. > For example, kernel can attempt to offline the affected memory by > migrating it or killing the process. Therefore, this feature is widely > used in servers and embedded fields. > > For historical versions, memory-failure cannot be enabled with x86_32 && > SPARSEMEM because the number of page-flags are insufficient. However, this > issue has been resolved in the current version, and this patch will allow > SPARSEMEM and memory-failure to be enabled together on x86_32. > > By the way, due to increased demand, DRAM prices have recently > skyrocketed, making memory-failure potentially even more valuable in the > coming years. Which LLM generated that for you, btw? I wanted to know _specifically_ what kind of hardware or 32-bit environment you wanted to support with this series, though.