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Sat, 12 Oct 2024 16:13:19 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from [10.32.65.156] (10.32.65.156) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Sat, 12 Oct 2024 15:57:12 +0800 Message-ID: <47dd0e33-4204-42c4-9176-207d65fa3217@zhaoxin.com> Date: Sat, 12 Oct 2024 15:56:52 +0800 Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/4] x86/mce: Add CMCI storm switching support for Zhaoxin To: "Zhuo, Qiuxu" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "x86@kernel.org" , "hpa@zytor.com" , "Luck, Tony" , "linux-kernel@vger.kernel.org" , "linux-edac@vger.kernel.org" X-ASG-Orig-Subj: Re: [PATCH v4 4/4] x86/mce: Add CMCI storm switching support for Zhaoxin CC: "CobeChen@zhaoxin.com" , "TimGuo@zhaoxin.com" , "LeoLiu-oc@zhaoxin.com" , "Lyle Li" References: <20240918055436.15551-1-TonyWWang-oc@zhaoxin.com> <20240923073311.4290-1-TonyWWang-oc@zhaoxin.com> <20240923073311.4290-5-TonyWWang-oc@zhaoxin.com> Content-Language: en-US From: Tony W Wang-oc In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ZXSHCAS1.zhaoxin.com (10.28.252.161) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 10/12/2024 4:13:18 PM X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1728720799 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1885 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.131700 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- On 2024/10/12 15:13, Zhuo, Qiuxu wrote: >=20 >=20 > [=E8=BF=99=E5=B0=81=E9=82=AE=E4=BB=B6=E6=9D=A5=E8=87=AA=E5=A4=96=E9=83=A8= =E5=8F=91=E4=BB=B6=E4=BA=BA =E8=B0=A8=E9=98=B2=E9=A3=8E=E9=99=A9] >=20 >> From: Tony W Wang-oc >> [...] >> Subject: [PATCH v4 4/4] x86/mce: Add CMCI storm switching support for >> Zhaoxin >> >> From: Lyle Li >> >> Zhaoxin CPUs support CMCI compatible with Intel, because Zhaoxin's UCR e= rror >> is not reported through CMCI, and in order to be compatible with intel's= CMCI >> code, so add Zhaoxin CMCI storm toggle to support the new CMCI storm >> switching in mce/intel.c, mce/zhaoxin.c, mce/threshold.c, and mce/intern= al.h. >=20 > Could you tweak and simplify the commit message, like this: >=20 > Zhaoxin CPUs support CMCI which is compatible with Intel, but their = UCR errors are > not reported through CMCI like Intel's. To be compatible with Intel'= s CMCI code, > add Zhaoxin's specific CMCI storm toggle. >=20 >> [...] >> diff --git a/arch/x86/kernel/cpu/mce/internal.h >> b/arch/x86/kernel/cpu/mce/internal.h >> index 836e56027..086b833c5 100644 >> --- a/arch/x86/kernel/cpu/mce/internal.h >> +++ b/arch/x86/kernel/cpu/mce/internal.h >> @@ -7,7 +7,7 @@ >> >> #include >> #include >> - >> +#include >=20 > Please sort the header files, like this: >=20 > #include > #include >=20 > #include >=20 > And keep a blank line here as it was. >=20 >> enum severity_level { >> MCE_NO_SEVERITY, >> MCE_DEFERRED_SEVERITY, >> @@ -334,11 +334,16 @@ static __always_inline u32 mca_msr_reg(int bank, >> enum mca_msr reg) } > [...] >=20 > Other than that: >=20 > Reviewed-by: Qiuxu Zhuo Thank you for reviewing this patchset. v5 will be resent according to=20 your suggestion. Sincerely TonyWWang-oc