From: Zhengqiang <zhengqiang10@huawei.com>
To: Borislav Petkov <bp@alien8.de>, James Morse <james.morse@arm.com>
Cc: Tyler Baicar <tbaicar@qti.qualcomm.com>,
mchehab@kernel.org, toshi.kani@hpe.com,
linux-edac@vger.kernel.org, linuxarm@huawei.com,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: EDAC, ghes: Make platform-based whitelisting x86-only
Date: Mon, 21 May 2018 17:39:01 +0800 [thread overview]
Message-ID: <5B0293B5.5060406@huawei.com> (raw)
Thanks, it works for me.
On 2018/5/18 19:20, Borislav Petkov wrote:
> From: Borislav Petkov <bp@suse.de>
>
> ARM machines all have DMI tables so if they request hw error reporting
> through GHES, then the driver should be able to detect DIMMs and report
> errors successfully (famous last words :)).
>
> Make the platform-based list x86-specific so that ghes_edac can load on
> ARM.
>
> Signed-off-by: Borislav Petkov <bp@suse.de>
> Reviewed-by: James Morse <james.morse@arm.com>
> Tested-by: James Morse <james.morse@arm.com>
> Cc: Qiang Zheng <zhengqiang10@huawei.com>
> Link: https://lkml.kernel.org/r/1526039543-180996-1-git-send-email-zhengqiang10@huawei.com
Tested-by: Qiang Zheng <zhengqiang10@huawei.com>
> ---
> drivers/edac/ghes_edac.c | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c
> index 863fbf3db29f..473aeec4b1da 100644
> --- a/drivers/edac/ghes_edac.c
> +++ b/drivers/edac/ghes_edac.c
> @@ -440,12 +440,16 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
> struct mem_ctl_info *mci;
> struct edac_mc_layer layers[1];
> struct ghes_edac_dimm_fill dimm_fill;
> - int idx;
> + int idx = -1;
>
> - /* Check if safe to enable on this system */
> - idx = acpi_match_platform_list(plat_list);
> - if (!force_load && idx < 0)
> - return -ENODEV;
> + if (IS_ENABLED(CONFIG_X86)) {
> + /* Check if safe to enable on this system */
> + idx = acpi_match_platform_list(plat_list);
> + if (!force_load && idx < 0)
> + return -ENODEV;
> + } else {
> + idx = 0;
> + }
>
> /*
> * We have only one logical memory controller to which all DIMMs belong.
>
---
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next reply other threads:[~2018-05-21 9:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-21 9:39 Zhengqiang [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-05-22 2:10 EDAC, ghes: Make platform-based whitelisting x86-only Tyler Baicar
2018-05-21 20:44 Borislav Petkov
2018-05-21 20:34 Tyler Baicar
2018-05-21 17:15 Borislav Petkov
2018-05-21 13:48 Tyler Baicar
2018-05-18 11:20 Borislav Petkov
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