Re: [PATCH v10 08/38] x86/cpufeatures: Add the cpu feature bit for FRED

Juergen Gross
2023-09-14T06:03:35Z

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On 14.09.23 06:47, Xin Li wrote:
> From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
>
> Any FRED CPU will always have the following features as its baseline:
> 1) LKGS, load attributes of the GS segment but the base address into
> the IA32_KERNEL_GS_BASE MSR instead of the GS segment’s descriptor
> cache.
> 2) WRMSRNS, non-serializing WRMSR for faster MSR writes.
>
> Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
> Tested-by: Shan Kang <shan.kang@intel.com>
> Signed-off-by: Xin Li <xin3.li@intel.com>

In order to avoid having to add paravirt support for FRED I think
xen_init_capabilities() should gain:

+ setup_clear_cpu_cap(X86_FEATURE_FRED);

Juergen

> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> arch/x86/kernel/cpu/cpuid-deps.c | 2 ++
> tools/arch/x86/include/asm/cpufeatures.h | 1 +
> 3 files changed, 4 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 330876d34b68..57ae93dc1e52 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -321,6 +321,7 @@
> #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */
> #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */
> #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
> +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */
> #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */
> #define X86_FEATURE_WRMSRNS (12*32+19) /* "" Non-Serializing Write to Model Specific Register instruction */
> #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */
> diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
> index e462c1d3800a..b7174209d855 100644
> --- a/arch/x86/kernel/cpu/cpuid-deps.c
> +++ b/arch/x86/kernel/cpu/cpuid-deps.c
> @@ -82,6 +82,8 @@ static const struct cpuid_dep cpuid_deps[] = {
> { X86_FEATURE_XFD, X86_FEATURE_XGETBV1 },
> { X86_FEATURE_AMX_TILE, X86_FEATURE_XFD },
> { X86_FEATURE_SHSTK, X86_FEATURE_XSAVES },
> + { X86_FEATURE_FRED, X86_FEATURE_LKGS },
> + { X86_FEATURE_FRED, X86_FEATURE_WRMSRNS },
> {}
> };
>
> diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
> index 1b9d86ba5bc2..18bab7987d7f 100644
> --- a/tools/arch/x86/include/asm/cpufeatures.h
> +++ b/tools/arch/x86/include/asm/cpufeatures.h
> @@ -317,6 +317,7 @@
> #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */
> #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */
> #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
> +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */
> #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */
> #define X86_FEATURE_WRMSRNS (12*32+19) /* "" Non-Serializing Write to Model Specific Register instruction */
> #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */

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