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Fri, 20 Sep 2024 18:49:20 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from [10.32.65.165] (10.32.65.165) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 20 Sep 2024 18:41:58 +0800 Message-ID: <662a0c91-2f84-4091-b971-0219a1c8a3d9@zhaoxin.com> Date: Fri, 20 Sep 2024 18:41:52 +0800 Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] x86/mce: Add centaur vendor to support Zhaoxin MCA To: Yazen Ghannam X-ASG-Orig-Subj: Re: [PATCH v3 1/3] x86/mce: Add centaur vendor to support Zhaoxin MCA CC: , , , , , , , , , , , , Lyle Li References: <20240910092652.13354-1-TonyWWang-oc@zhaoxin.com> <20240918055436.15551-1-TonyWWang-oc@zhaoxin.com> <20240918055436.15551-2-TonyWWang-oc@zhaoxin.com> <20240919135518.GA3717@yaz-khff2.amd.com> Content-Language: en-US From: Tony W Wang-oc In-Reply-To: <20240919135518.GA3717@yaz-khff2.amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: ZXSHCAS1.zhaoxin.com (10.28.252.161) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 9/20/2024 6:49:19 PM X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1726829360 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 3422 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.130712 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- On 2024/9/19 21:55, Yazen Ghannam wrote: > > On Wed, Sep 18, 2024 at 01:54:34PM +0800, Tony W Wang-oc wrote: >> From: Lyle Li >> >> Zhaoxin consists of two vendors, X86_VENDOR_ZHAOXIN and >> X86_VENDOR_CENTAUR, so add the centaur vendor to support >> Zhaoxin MCA in mce/core.c and mce/intel.c. >> >> Signed-off-by: Lyle Li >> Signed-off-by: Tony W Wang-oc >> --- >> arch/x86/kernel/cpu/mce/core.c | 12 +++++++++--- >> arch/x86/kernel/cpu/mce/intel.c | 3 ++- >> 2 files changed, 11 insertions(+), 4 deletions(-) >> >> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c >> index ad0623b65..7f79d900f 100644 >> --- a/arch/x86/kernel/cpu/mce/core.c >> +++ b/arch/x86/kernel/cpu/mce/core.c >> @@ -496,6 +496,7 @@ bool mce_usable_address(struct mce *m) >> >> case X86_VENDOR_INTEL: >> case X86_VENDOR_ZHAOXIN: >> + case X86_VENDOR_CENTAUR: >> return intel_mce_usable_address(m); >> >> default: >> @@ -513,6 +514,7 @@ bool mce_is_memory_error(struct mce *m) >> >> case X86_VENDOR_INTEL: >> case X86_VENDOR_ZHAOXIN: >> + case X86_VENDOR_CENTAUR: >> /* >> * Intel SDM Volume 3B - 15.9.2 Compound Error Codes >> * >> @@ -1247,7 +1249,8 @@ static noinstr bool mce_check_crashing_cpu(void) >> >> mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); >> >> - if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { >> + if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || >> + boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) { >> if (mcgstatus & MCG_STATUS_LMCES) >> return false; >> } >> @@ -1521,7 +1524,8 @@ noinstr void do_machine_check(struct pt_regs *regs) >> * on Intel, Zhaoxin only. >> */ >> if (m.cpuvendor == X86_VENDOR_INTEL || >> - m.cpuvendor == X86_VENDOR_ZHAOXIN) >> + m.cpuvendor == X86_VENDOR_ZHAOXIN || >> + m.cpuvendor == X86_VENDOR_CENTAUR) >> lmce = m.mcgstatus & MCG_STATUS_LMCES; >> >> /* >> @@ -2092,6 +2096,7 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) >> break; >> >> case X86_VENDOR_ZHAOXIN: >> + case X86_VENDOR_CENTAUR: >> mce_zhaoxin_feature_clear(c); >> break; >> >> @@ -2401,7 +2406,8 @@ static void vendor_disable_error_reporting(void) >> if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || >> boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || >> boot_cpu_data.x86_vendor == X86_VENDOR_AMD || >> - boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) >> + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || >> + boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) >> return; >> >> mce_disable_error_reporting(); > > At this point, should we even do this? It seems all major vendors want > to *not* disable MCA_CTL after init. > > This, and related functions, can be deleted. Unless there's a compelling > reason to keep them. > From the current code implementation, your suggestion is reasonable. Will delete the related functions in the next version. Sincerely TonyWWang-oc