From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 970531D5CE8; Thu, 10 Apr 2025 16:23:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744302209; cv=none; b=SwkKiyTuskV+dncWhLnCaPPCUHWpocn5rVrpT7q8bngy8imX+EmHZirtu5rZGQGE1MgfbU2TeYe2pidLkUGWuYhIbJbIxMbeqJC+hCBHQdS1b0ngWG420X7m/JDTxwjxPT3GeAGaMSuKgX0UMV5farD4RyegSGAEZlBLGvAoUfg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744302209; c=relaxed/simple; bh=MIJHmLndng2qHd6AMjG45aj/Tigau0sdbPDDS+LPv04=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=oCnNyBT1jcY85h4QpWRijWB3nBso6+DYogCo9xTClriedo4jGMX4aJgSwX7JnQU1mwDmY5d4LIOXLhwpsghFEzsOR4VZRR07nYbPk9riAVGTjryn7+BdgGSnLpdwY/PskYKlDxhotwbfLRzvs5Ub7PWm7vAaxh7wQIf7F4+T2Y8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e9B0xgxT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e9B0xgxT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 69337C4CEDD; Thu, 10 Apr 2025 16:23:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744302209; bh=MIJHmLndng2qHd6AMjG45aj/Tigau0sdbPDDS+LPv04=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=e9B0xgxTWYrcFHkiVGBGJiHaFYVWKGZTUNNrXkTWimGY9SCcDGUgx9YBRI46PJhSb AVGgwpR0PxaS6YG0syWk1G7ANdk8a9CDHd8y/osqZYuslTbkMxZqwMAPwepHm0x1MU B9/MmJb/iZXqun7sge9kx68lNvHQxteIuDAbGGddcChKwKyRRe2LkOTEHztoOK9cCW zoraxTe36oFVBBaC3qWyauq0pENkJASB5TYyt7IfVAQOSN/JVWFRti9/41q2ErU8ky k7YE5GNIyRKEVXp5Bh5/JCb+3JO0tCiFD+LzaFs7Rio0EzDqTLY8yjkkx77A8YSEna 8KB0fI+tYqy1g== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1u2ugZ-004I5l-37; Thu, 10 Apr 2025 17:23:27 +0100 Date: Thu, 10 Apr 2025 17:23:26 +0100 Message-ID: <86frigkmtd.wl-maz@kernel.org> From: Marc Zyngier To: "Tyler Hicks (Microsoft)" Cc: Krzysztof Kozlowski , Vijay Balakrishna , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Sascha Hauer Subject: Re: [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property In-Reply-To: References: <1744241785-20256-1-git-send-email-vijayb@linux.microsoft.com> <1744241785-20256-3-git-send-email-vijayb@linux.microsoft.com> <319b7c65-3e2f-456b-a845-45f7a57ba2c5@kernel.org> <86o6x4lcf9.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: code@tyhicks.com, krzk@kernel.org, vijayb@linux.microsoft.com, bp@alien8.de, tony.luck@intel.com, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, s.hauer@pengutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 10 Apr 2025 15:30:17 +0100, "Tyler Hicks (Microsoft)" wrote: > > On 2025-04-10 08:10:18, Marc Zyngier wrote: > > On Thu, 10 Apr 2025 07:00:55 +0100, > > Krzysztof Kozlowski wrote: > > > > > > On 10/04/2025 01:36, Vijay Balakrishna wrote: > > > > From: Sascha Hauer > > > > > > > > Some ARM Cortex CPUs like the A53, A57 and A72 have Error Detection And > > > > Correction (EDAC) support on their L1 and L2 caches. This is implemented > > > > in implementation defined registers, so usage of this functionality is > > > > not safe in virtualized environments or when EL3 already uses these > > > > registers. This patch adds a edac-enabled flag which can be explicitly > > > > set when EDAC can be used. > > > > > > Can't hypervisor tell you that? > > > > No, it can't. This is not an architecture feature, and KVM will gladly > > inject an UNDEF exception if the guest tries to use this. > > > > Which is yet another reason why this whole exercise is futile. > > Hi Marc - could you clarify why this is futile for baremetal or were you just > referring to virtualized environments? This is futile in general. This sort of stuff only makes sense if you can take useful action upon detecting an error, such as cache scrubbing. Here, this is just telling you "bang, you're dead", without any other recourse. You are not even sure you'll be able to actually *run* this code. You cannot identify what the blast radius. We have some other EDAC implementation for arm64 CPUs (XGene, ThunderX), and they are all perfectly useless (I have them in my collection of horrors). I know you are familiar enough with the RAS architecture to appreciate the difference with a contemporary implementation that would actually do the right thing. Thanks, M. -- Without deviation from the norm, progress is not possible.