From: Marc Zyngier <maz@kernel.org>
To: Vijay Balakrishna <vijayb@linux.microsoft.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>,
linux-edac@vger.kernel.org, Borislav Petkov <bp@alien8.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Tony Luck <tony.luck@intel.com>,
James Morse <james.morse@arm.com>,
Robert Richter <rrichter@marvell.com>,
York Sun <york.sun@nxp.com>,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH v5 0/2] Add L1 and L2 error detection for A53 and A57
Date: Thu, 13 Mar 2025 09:22:07 +0000 [thread overview]
Message-ID: <86msdpnv40.wl-maz@kernel.org> (raw)
In-Reply-To: <ff79f33d-91fd-49e5-9a6f-fa2c32c7021d@linux.microsoft.com>
On Thu, 13 Mar 2025 01:43:55 +0000,
Vijay Balakrishna <vijayb@linux.microsoft.com> wrote:
>
> On 4/1/2021 4:06 AM, Sascha Hauer wrote:
> > Hi,
> >
> > Resending this mainly because Marc Zyngier and Mark Rutland raised
> > concerns about using implementation defined registers and I forgot to Cc
> > them with the last version. This version, like v4 already, should fix
> > these concerns. Looking forward to feedback.
>
> We aim to revive and adapt this patch series for A72 and A78. Is
> anyone actively working on this? Please share any information on why
> it wasn't pursued and thoughts on adapting it to A72 and A78.
Because, and especially for less ancient CPUs such as A78 that
implement some form of FEAT_RAS support, this makes little sense. We
fully expect RAS errors to be handled by firmware, which knows exactly
the cache topology and can abstract the reporting into error records.
Firmware is also the correct place for all this IMPDEF stuff.
M.
--
Without deviation from the norm, progress is not possible.
prev parent reply other threads:[~2025-03-13 9:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-01 11:06 [PATCH v5 0/2] Add L1 and L2 error detection for A53 and A57 Sascha Hauer
2021-04-01 11:06 ` [PATCH 1/2] drivers/edac: " Sascha Hauer
2021-04-02 10:06 ` Marc Zyngier
2021-04-15 10:15 ` Sascha Hauer
2021-04-01 11:06 ` [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property Sascha Hauer
2021-04-01 15:37 ` Marc Zyngier
2025-03-13 1:43 ` [PATCH v5 0/2] Add L1 and L2 error detection for A53 and A57 Vijay Balakrishna
2025-03-13 9:22 ` Marc Zyngier [this message]
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