From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3384C2C80 for ; Thu, 13 Mar 2025 09:22:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741857731; cv=none; b=Ph7rC8NwvwaJ7CeQ6HS1j8BOdcOxxq0wMEScCIvH3ZfKOdGG4DLwy0CC5a5/Yb3SulUW0Tw0iVb6MSgat9+X/Vk5QOCClRRbi5aM9DTVaLfANxrtBWnGVfHQrMtnAR0Ar+5/UHap4vCJ+5+rgUGNJ12B8DjhyEAJs3W8YppTEdQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741857731; c=relaxed/simple; bh=XdeBR9m2VcWibmHMg21PFruzKcPhd6Kz1ihDbhRx1+8=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=O9S7bAjUk6gBNmsxHfec1J091LOwVMjA6dcWSaxkYyh3BO+UBjx+UJPvMHAUWheR7TcdrYyzLkhwG/EhCTn65UxEScPa0N+x+H8XKFtsY5em5VDk/hCaIM2/7NgqN9qcqiq/lDZXewsOQDWr8w3Mn9HHCq44Tgu/vFTYsaem4NM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S6ycttKa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S6ycttKa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7841AC4CEDD; Thu, 13 Mar 2025 09:22:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741857730; bh=XdeBR9m2VcWibmHMg21PFruzKcPhd6Kz1ihDbhRx1+8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=S6ycttKaj8HlLgujdPMi7HuQ/lFKLXctTcF257z79AJiDZhpfcPUL5Fdd7D+vNdBo emSXOgg4dsbkaYpn8S9yvLOzx71SQNtMGUzOD+n1MNcmrhfpiDvXUP2AXiYCHnOJBS 47mt4/n2QZgxfMxDDQSJjFhkcrpOur4F5asxRKw0/x2y3FP3qcPRwpwXA+fT1mHZUm HOKj95rJCtMZePnRecOo1/y2uFf4APTRM+qupkJVWvCnFEBPBy1QD4+Ox71jIbKwXT /O7bHRxeBmR7/LqkDvaKdj+9MtQTIOXA/XjxTilqfiaLHr5v/OXTGe3B6m5mos5Oy/ Dea2kH5aOsxxQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tselT-00D8gc-HC; Thu, 13 Mar 2025 09:22:07 +0000 Date: Thu, 13 Mar 2025 09:22:07 +0000 Message-ID: <86msdpnv40.wl-maz@kernel.org> From: Marc Zyngier To: Vijay Balakrishna Cc: Sascha Hauer , linux-edac@vger.kernel.org, Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , James Morse , Robert Richter , York Sun , kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org, Rob Herring , Mark Rutland Subject: Re: [PATCH v5 0/2] Add L1 and L2 error detection for A53 and A57 In-Reply-To: References: <20210401110615.15326-1-s.hauer@pengutronix.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: vijayb@linux.microsoft.com, s.hauer@pengutronix.de, linux-edac@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, james.morse@arm.com, rrichter@marvell.com, york.sun@nxp.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, mark.rutland@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 13 Mar 2025 01:43:55 +0000, Vijay Balakrishna wrote: > > On 4/1/2021 4:06 AM, Sascha Hauer wrote: > > Hi, > > > > Resending this mainly because Marc Zyngier and Mark Rutland raised > > concerns about using implementation defined registers and I forgot to Cc > > them with the last version. This version, like v4 already, should fix > > these concerns. Looking forward to feedback. > > We aim to revive and adapt this patch series for A72 and A78. Is > anyone actively working on this? Please share any information on why > it wasn't pursued and thoughts on adapting it to A72 and A78. Because, and especially for less ancient CPUs such as A78 that implement some form of FEAT_RAS support, this makes little sense. We fully expect RAS errors to be handled by firmware, which knows exactly the cache topology and can abstract the reporting into error records. Firmware is also the correct place for all this IMPDEF stuff. M. -- Without deviation from the norm, progress is not possible.