From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 610844F7CA3; Tue, 13 Oct 2026 13:53:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791899583; cv=none; b=WWkC8nMsyCfEvAuQd9ize5uiOgZpz9NtatQ+gF8VEbKC2PCTiN45RfVwFhUlLZQcbzOIvm19jf+Nur67UHZfX8E3JxxiFdMWqMEzmchfDyNjhpkfFzyUVp/I/pWWA3oUusCAhQbjkUHwts/mYgszoeT+/xZud7O5NUv7TWWMKjk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791899583; c=relaxed/simple; bh=saLD1mV0ic++PwAbLNYu01ddzsXMm90zjgupVeJiaIw=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=WVLnSWTpFFXxjqLe9hhDRHH5OuU42kYAtrAjxA6xbYk53CeXX9cIRIOpRBC+TW0wNvu9RtrV/IwjVnUC/C28c1RvShDr1XgWwavGjSGsCa9+q1NBTfvzyNhSv+GiHYm9NY5Gtk1LHnc6EbcxxbqtPbJFLZN121YZ3SSV1UCPiV8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=QvDQ7l1R; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="QvDQ7l1R" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id C67331A1203; Tue, 13 Oct 2026 13:52:53 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 98EED60362; Tue, 13 Oct 2026 13:52:53 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1788311D71615; Tue, 13 Oct 2026 15:52:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1791899572; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=CtXqRswKbx5dTP1pjP03sqibyt/3E5DuejRQw9zPWYI=; b=QvDQ7l1R7gpA9iQt5x97bXgtASuMhTjV4SK6ygVYVkv0C71u/RdEkWriCYEvJoxILd3y4Y /dNFjk9SZcVk8Ex8O1RZkwX/j1tTka+q83nMT0JEcTFSBfZcbxIefluOiLHq/1qpUoTrWX 6W7zBl1uleL9U+UBf1XKp68fU3UhGSjn/iLX7Z3wQRNm26H0vt3Lk3LGb6WkuRV0gShf4i gnUZmig5OO2PR8jRxjINRa/Tr2hjnMWFw0z4z6sZvB5vvtLwtQ2n9GuEwwuFyEBUEghufQ QdU3eT9r84+rbP0JOvziOHcvYlK6imcXEsN8gy3YEIYXHUbt6uo7zSNGqVg+5w== From: Miquel Raynal To: "Paul Louvel" Cc: "Geert Uytterhoeven" , "Borislav Petkov" , "Tony Luck" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Geert Uytterhoeven" , "Magnus Damm" , , , , , "Thomas Petazzoni" , "Herve Codina" , "Wolfram Sang" Subject: Re: [PATCH v6 3/3] ARM: dts: renesas: r9a06g032: add EDAC node In-Reply-To: (Paul Louvel's message of "Tue, 13 Oct 2026 13:57:56 +0200") References: <20261013-paul-v7-3-rc1-edac-v6-0-2f1d6f2f74db@bootlin.com> <20261013-paul-v7-3-rc1-edac-v6-3-2f1d6f2f74db@bootlin.com> User-Agent: mu4e 1.12.12; emacs 30.2 Date: Tue, 13 Oct 2026 15:52:47 +0200 Message-ID: <87se29wvv4.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 >>> + edac: memory-controller@4000d000 { >>> + compatible =3D "renesas,r9a06g032-ddr-edac", "c= dns,ddr-edac"; >>> + reg =3D <0x4000d000 0x1000>; >>> + interrupts =3D ; >>> + clocks =3D <&sysctrl R9A06G032_CLK_DDRC>, <&sys= ctrl R9A06G032_HCLK_DDRC>; >>> + clock-names =3D "ddrc", "pclk"; >>> + status =3D "disabled"; >> >> Should this node be enabled by default, or am I too naive? > > The bootloader will be responsible to initialize the DDR controller and e= nable > ECC if specified. On this specific platform (r9a06g032), ECC is disabled = by > default. > Enabling the ECC require a specific property to be present under the cont= roller > node in U-Boot. I think it make sense to keep it by default disabled. Wouldn't enabling it also require some reserved memory regions? There should be an impact on the amount of available RAM for the system. Thanks, Miqu=C3=A8l