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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: "Luck, Tony" <tony.luck@intel.com>,
	"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: yazen.ghannam@amd.com,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH] x86/mce: Schedule mce_setup() on correct CPU for CPER decoding
Date: Fri, 9 Jun 2023 10:26:54 -0400	[thread overview]
Message-ID: <96f6201e-8c33-a25d-7ec3-00769f67869a@amd.com> (raw)
In-Reply-To: <SJ1PR11MB60837EAC6B0AA28AF7D16784FC9C9@SJ1PR11MB6083.namprd11.prod.outlook.com>

On 4/17/23 1:39 PM, Luck, Tony wrote:
>> The function expects the data to match the "MCAX" register layout used on
>> Scalable MCA systems. CTL, STATUS, ADDR, and MISC will be at the same offsets
>> for legacy MCA and MCAX. But the rest will be different.
> 
> Ah yes. Looking at the code, rather than the patch I see that it first checks for SMCA
> and returns if it isn't on an SMCA system.
> 
>         if (!boot_cpu_has(X86_FEATURE_SMCA))
>                 return -EINVAL;
> 
>> This could be extended though, if other systems will use it.
> 
> I'll keep it in mind if Intel makes a hybrid server.
>

Hi all,

Any further comments on this?

Thanks,
Yazen

  reply	other threads:[~2023-06-09 14:27 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-17 16:20 [PATCH] x86/mce: Schedule mce_setup() on correct CPU for CPER decoding Yazen Ghannam
2023-04-17 17:17 ` Luck, Tony
2023-04-17 17:28   ` Yazen Ghannam
2023-04-17 17:39     ` Luck, Tony
2023-06-09 14:26       ` Yazen Ghannam [this message]
2023-06-15 15:20 ` Borislav Petkov
2023-06-15 15:34   ` Yazen Ghannam
2023-06-15 16:20     ` Borislav Petkov
2023-06-15 17:02       ` Yazen Ghannam
2023-06-15 17:39         ` Yazen Ghannam
2023-06-15 17:54           ` Luck, Tony
2023-06-16 14:16             ` Yazen Ghannam
2023-06-16 16:05               ` Luck, Tony

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