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[2001:67c:10ec:2886:8000::14b7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1f2ca3597sm10959075e9.2.2026.10.19.11.34.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Oct 2026 11:34:07 -0700 (PDT) X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 19 Oct 2026 20:34:06 +0200 Message-Id: Cc: , , , , , Subject: Re: [PATCH v3] x86/mce: Do not treat cache hierarchy errors as memory errors From: "Adrian Schlegel" To: "Yazen Ghannam" , "Adrian Schlegel" X-Mailer: aerc 0.22.0 References: <20261003222012.19685-1-me@adrianschlegel.com> <20261012193305.38931-1-me@adrianschlegel.com> <20261019153207.GA144824@yaz-khff2.amd.com> In-Reply-To: <20261019153207.GA144824@yaz-khff2.amd.com> On Mon Oct 19, 2026 at 5:32 PM CEST, Yazen Ghannam wrote: > The SDM also mentions "Extended Memory Errors". I guess these were left > out before, but should they be included? I don't think so, since from what I can tell from the Intel SDM (Memory Controller and Extended Memory Errors), extended memory errors use the same encoding as normal memory errors, but report errors in memory that is used as a cache, similar to what cache hierarchy errors do. I also found this thread, where Tony made the same point: https://lore.kernel.org/all/SJ1PR11MB60831E048B544C83E845D907FC8DA@SJ1PR11M= B6083.namprd11.prod.outlook.com/ Best, Adrian