From: Borislav Petkov <bp@alien8.de>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, tony.luck@intel.com,
quic_saipraka@quicinc.com, konrad.dybcio@linaro.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
james.morse@arm.com, mchehab@kernel.org, rric@kernel.org,
linux-edac@vger.kernel.org, quic_ppareek@quicinc.com,
luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org
Subject: Re: [PATCH v5 15/17] qcom: llcc/edac: Fix the base address used for accessing LLCC banks
Date: Sat, 14 Jan 2023 14:27:50 +0100 [thread overview]
Message-ID: <Y8Kt1uKAIPyl0y+d@zn.tnic> (raw)
In-Reply-To: <20221228084028.46528-16-manivannan.sadhasivam@linaro.org>
On Wed, Dec 28, 2022 at 02:10:26PM +0530, Manivannan Sadhasivam wrote:
> The Qualcomm LLCC/EDAC drivers were using a fixed register stride for
> accessing the (Control and Status Registers) CSRs of each LLCC bank.
> This stride only works for some SoCs like SDM845 for which driver
> support was initially added.
>
> But the later SoCs use different register stride that vary between the
> banks with holes in-between. So it is not possible to use a single register
> stride for accessing the CSRs of each bank. By doing so could result in a
> crash.
If this patch fixes a crash, then it should be
Cc: <stable@kernel.org>
If there are prerequisites to it, they should be CC:stable too.
So looking at the urgent stuff: patches 1, 3, I'm thinking I can take them
through the EDAC tree and send them to Linus now, after you've addressed the
review comments.
This one can go through some other tree, I presume, but since it fixes a crash
it should go in now too...
> For fixing this issue, let's obtain the base address of each LLCC bank from
> devicetree and get rid of the fixed stride. This also means, we no longer
Please use passive voice in your commit message: no "we" or "I", etc,
and describe your changes in imperative mood.
Personal pronouns are ambiguous in text, especially with so many
parties/companies/etc developing the kernel so let's avoid them please.
> need to rely on reg-names property and get the base addresses using index.
>
> First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC
> supports more than one bank, then those needs to be defined in devicetree
s/needs/need/
> for index from 1..N-1.
>
> Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
> Tested-by: Luca Weiss <luca.weiss@fairphone.com>
> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s
> Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8540p-ride
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
With the above addressed, for the EDAC bits:
Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2023-01-14 13:28 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-28 8:40 [PATCH v5 00/17] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 01/17] EDAC/device: Make use of poll_msec value in edac_device_ctl_info struct Manivannan Sadhasivam
2022-12-28 11:17 ` Borislav Petkov
2022-12-28 8:40 ` [PATCH v5 02/17] EDAC/qcom: Add platform_device_id table for module autoloading Manivannan Sadhasivam
2022-12-28 11:54 ` Borislav Petkov
2022-12-28 8:40 ` [PATCH v5 03/17] EDAC/qcom: Do not pass llcc_driv_data as edac_device_ctl_info's pvt_info Manivannan Sadhasivam
2022-12-28 11:58 ` Borislav Petkov
2022-12-28 8:40 ` [PATCH v5 04/17] dt-bindings: arm: msm: Update the maintainers for LLCC Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 05/17] dt-bindings: arm: msm: Fix register regions used for LLCC banks Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 06/17] arm64: dts: qcom: sdm845: Fix the base addresses of " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 07/17] arm64: dts: qcom: sc7180: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 08/17] arm64: dts: qcom: sc7280: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 09/17] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 10/17] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 11/17] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 12/17] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 13/17] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 14/17] arm64: dts: qcom: sm6350: " Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 15/17] qcom: llcc/edac: Fix the base address used for accessing " Manivannan Sadhasivam
2023-01-14 13:27 ` Borislav Petkov [this message]
2023-01-15 4:01 ` Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 16/17] qcom: llcc/edac: Support polling mode for ECC handling Manivannan Sadhasivam
2023-01-14 13:36 ` Borislav Petkov
2023-01-15 4:08 ` Manivannan Sadhasivam
2023-01-16 10:41 ` Borislav Petkov
2023-01-18 15:08 ` Manivannan Sadhasivam
2022-12-28 8:40 ` [PATCH v5 17/17] soc: qcom: llcc: Do not create EDAC platform device on SDM845 Manivannan Sadhasivam
2022-12-28 10:36 ` [PATCH v5 00/17] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Borislav Petkov
2022-12-28 16:47 ` Manivannan Sadhasivam
2022-12-28 17:55 ` Borislav Petkov
2023-01-02 17:30 ` Manivannan Sadhasivam
2023-01-14 7:12 ` Manivannan Sadhasivam
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