From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A886C433F5 for ; Tue, 7 Dec 2021 19:00:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235960AbhLGTEH (ORCPT ); Tue, 7 Dec 2021 14:04:07 -0500 Received: from mail.skyhub.de ([5.9.137.197]:36302 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231778AbhLGTEF (ORCPT ); Tue, 7 Dec 2021 14:04:05 -0500 Received: from zn.tnic (dslb-088-067-202-008.088.067.pools.vodafone-ip.de [88.67.202.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id E20DF1EC0118; Tue, 7 Dec 2021 20:00:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1638903630; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=9enz5ts+vCqpd36KcwT4E4Jl+vidS2bA+MLNI4C40GQ=; b=kCuGn20tKJiYy6qhhQtQGNrjD+lpS4AzDVRblLYCAbVVTIxQaA37HRme7i7uANL4hs76pI Ics6/SqT2rRwR/F0glVj8ZHOQFfkfXyXc85y0VL6DZI5w6aGha5KCsMOtgxAt00nANxmxh pQWJPDNkd+g6BfX6/69KcugOPmnuVKA= Date: Tue, 7 Dec 2021 20:00:32 +0100 From: Borislav Petkov To: Smita Koralahalli Cc: x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Tony Luck , "H . Peter Anvin" , yazen.ghannam@amd.com Subject: Re: [PATCH v3 3/6] x86/mce/inject: Check for writes ignored in status registers Message-ID: References: <20211104215846.254012-1-Smita.KoralahalliChannabasappa@amd.com> <20211104215846.254012-4-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20211104215846.254012-4-Smita.KoralahalliChannabasappa@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On Thu, Nov 04, 2021 at 04:58:43PM -0500, Smita Koralahalli wrote: > According to Section 2.1.16.3 under HWCR[McStatusWrEn] in "PPR for AMD > Family 19h, Model 01h, Revision B1 Processors - 55898 Rev 0.35 - Feb 5, > 2021", the status register may sometimes enforce write ignored behavior > independent of the value of HWCR[McStatusWrEn] depending on the platform > settings. How and when can it enforce that? Can we detect whether that enforcement is active and if so, fail the injection directly instead of checking whether the writes have stuck in the MSRs? -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette