[PATCH 07/14] EDAC/amd64: Add ecc_enabled() into pvt->ops

Naveen Krishna Chatradhi
2022-02-28T16:14:41Z

From: Muralidhara M K <muralimk@amd.com>

Add function pointer for ecc_enabled() in pvt->ops and assign
family specific ecc_enabled() definitions appropriately.

Signed-off-by: Muralidhara M K <muralimk@amd.com>
Signed-off-by: Naveen Krishna Chatradhi <nchatrad@amd.com>
---
This patch is created by splitting the 5/12th patch in series
[v7 5/12] https://patchwork.kernel.org/project/linux-edac/patch/20220203174942.31630-6-nchatrad@amd.com/

drivers/edac/amd64_edac.c | 77 ++++++++++++++++++++++++---------------
drivers/edac/amd64_edac.h | 1 +
2 files changed, 48 insertions(+), 30 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 713ffe763e64..15d775a9ce7e 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3649,49 +3649,60 @@ static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid,
amd64_warn("Error restoring NB MCGCTL settings!\n");
}

-static bool ecc_enabled(struct amd64_pvt *pvt)
+static bool f1x_ecc_enabled(struct amd64_pvt *pvt)
{
u16 nid = pvt->mc_node_id;
bool nb_mce_en = false;
- u8 ecc_en = 0, i;
+ u8 ecc_en = 0;
u32 value;

- if (boot_cpu_data.x86 >= 0x17) {
- u8 umc_en_mask = 0, ecc_en_mask = 0;
- struct amd64_umc *umc;
+ amd64_read_pci_cfg(pvt->F3, NBCFG, &value);

- for_each_umc(i) {
- umc = &pvt->umc[i];
+ ecc_en = !!(value & NBCFG_ECC_ENABLE);

- /* Only check enabled UMCs. */
- if (!(umc->sdp_ctrl & UMC_SDP_INIT))
- continue;
+ nb_mce_en = nb_mce_bank_enabled_on_node(nid);
+ if (!nb_mce_en)
+ edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",
+ MSR_IA32_MCG_CTL, nid);

- umc_en_mask |= BIT(i);
+ edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));

- if (umc->umc_cap_hi & UMC_ECC_ENABLED)
- ecc_en_mask |= BIT(i);
- }
+ if (!ecc_en || !nb_mce_en)
+ return false;
+ else
+ return true;
+}

- /* Check whether at least one UMC is enabled: */
- if (umc_en_mask)
- ecc_en = umc_en_mask == ecc_en_mask;
- else
- edac_dbg(0, "Node %d: No enabled UMCs.\n", nid);
+static bool f17_ecc_enabled(struct amd64_pvt *pvt)
+{
+ u8 umc_en_mask = 0, ecc_en_mask = 0;
+ u8 ecc_en = 0, i;
+ u16 nid = pvt->mc_node_id;
+ bool nb_mce_en = false;
+ struct amd64_umc *umc;

- /* Assume UMC MCA banks are enabled. */
- nb_mce_en = true;
- } else {
- amd64_read_pci_cfg(pvt->F3, NBCFG, &value);
+ for_each_umc(i) {
+ umc = &pvt->umc[i];
+
+ /* Only check enabled UMCs. */
+ if (!(umc->sdp_ctrl & UMC_SDP_INIT))
+ continue;

- ecc_en = !!(value & NBCFG_ECC_ENABLE);
+ umc_en_mask |= BIT(i);

- nb_mce_en = nb_mce_bank_enabled_on_node(nid);
- if (!nb_mce_en)
- edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",
- MSR_IA32_MCG_CTL, nid);
+ if (umc->umc_cap_hi & UMC_ECC_ENABLED)
+ ecc_en_mask |= BIT(i);
}

+ /* Check whether at least one UMC is enabled: */
+ if (umc_en_mask)
+ ecc_en = umc_en_mask == ecc_en_mask;
+ else
+ edac_dbg(0, "Node %d: No enabled UMCs.\n", nid);
+
+ /* Assume UMC MCA banks are enabled. */
+ nb_mce_en = true;
+
edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));

if (!ecc_en || !nb_mce_en)
@@ -3784,6 +3795,7 @@ static int per_family_init(struct amd64_pvt *pvt)
pvt->ops->determine_memory_type = f1x_determine_memory_type;
pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz;
pvt->ops->get_mc_regs = read_mc_regs;
+ pvt->ops->ecc_enabled = f1x_ecc_enabled;
break;

case 0x10:
@@ -3798,6 +3810,7 @@ static int per_family_init(struct amd64_pvt *pvt)
pvt->ops->determine_memory_type = f1x_determine_memory_type;
pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz;
pvt->ops->get_mc_regs = read_mc_regs;
+ pvt->ops->ecc_enabled = f1x_ecc_enabled;
break;

case 0x15:
@@ -3828,6 +3841,7 @@ static int per_family_init(struct amd64_pvt *pvt)
pvt->ops->determine_memory_type = f1x_determine_memory_type;
pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz;
pvt->ops->get_mc_regs = read_mc_regs;
+ pvt->ops->ecc_enabled = f1x_ecc_enabled;
break;

case 0x16:
@@ -3848,6 +3862,7 @@ static int per_family_init(struct amd64_pvt *pvt)
pvt->ops->determine_memory_type = f1x_determine_memory_type;
pvt->ops->determine_ecc_sym_sz = f1x_determine_ecc_sym_sz;
pvt->ops->get_mc_regs = read_mc_regs;
+ pvt->ops->ecc_enabled = f1x_ecc_enabled;
break;

case 0x17:
@@ -3882,6 +3897,7 @@ static int per_family_init(struct amd64_pvt *pvt)
pvt->ops->determine_memory_type = f17_determine_memory_type;
pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz;
pvt->ops->get_mc_regs = __read_mc_regs_df;
+ pvt->ops->ecc_enabled = f17_ecc_enabled;

if (pvt->fam == 0x18) {
pvt->ctl_name = "F18h";
@@ -3922,6 +3938,7 @@ static int per_family_init(struct amd64_pvt *pvt)
pvt->ops->determine_memory_type = f17_determine_memory_type;
pvt->ops->determine_ecc_sym_sz = f17_determine_ecc_sym_sz;
pvt->ops->get_mc_regs = __read_mc_regs_df;
+ pvt->ops->ecc_enabled = f17_ecc_enabled;
break;

default:
@@ -3933,7 +3950,7 @@ static int per_family_init(struct amd64_pvt *pvt)
if (!pvt->ops->early_channel_count || !pvt->ops->dbam_to_cs ||
!pvt->ops->get_base_mask || !pvt->ops->prep_chip_selects ||
!pvt->ops->determine_memory_type || !pvt->ops->determine_ecc_sym_sz ||
- !pvt->ops->get_mc_regs) {
+ !pvt->ops->get_mc_regs || !pvt->ops->ecc_enabled) {
edac_dbg(1, "Common helper routines not defined.\n");
return -EFAULT;
}
@@ -4095,7 +4112,7 @@ static int probe_one_instance(unsigned int nid)
goto err_enable;
}

- if (!ecc_enabled(pvt)) {
+ if (!pvt->ops->ecc_enabled(pvt)) {
ret = -ENODEV;

if (!ecc_enable_override)
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 1b6df33bb0a8..6cc3fc943fcd 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -469,6 +469,7 @@ struct low_ops {
void (*determine_memory_type)(struct amd64_pvt *pvt);
void (*determine_ecc_sym_sz)(struct amd64_pvt *pvt);
void (*get_mc_regs)(struct amd64_pvt *pvt);
+ bool (*ecc_enabled)(struct amd64_pvt *pvt);
};

int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
--
2.25.1