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Thu, 10 Apr 2025 10:30:19 -0400 (EDT) Date: Thu, 10 Apr 2025 09:30:17 -0500 From: "Tyler Hicks (Microsoft)" To: Marc Zyngier Cc: Krzysztof Kozlowski , Vijay Balakrishna , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Sascha Hauer Subject: Re: [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property Message-ID: References: <1744241785-20256-1-git-send-email-vijayb@linux.microsoft.com> <1744241785-20256-3-git-send-email-vijayb@linux.microsoft.com> <319b7c65-3e2f-456b-a845-45f7a57ba2c5@kernel.org> <86o6x4lcf9.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86o6x4lcf9.wl-maz@kernel.org> On 2025-04-10 08:10:18, Marc Zyngier wrote: > On Thu, 10 Apr 2025 07:00:55 +0100, > Krzysztof Kozlowski wrote: > > > > On 10/04/2025 01:36, Vijay Balakrishna wrote: > > > From: Sascha Hauer > > > > > > Some ARM Cortex CPUs like the A53, A57 and A72 have Error Detection And > > > Correction (EDAC) support on their L1 and L2 caches. This is implemented > > > in implementation defined registers, so usage of this functionality is > > > not safe in virtualized environments or when EL3 already uses these > > > registers. This patch adds a edac-enabled flag which can be explicitly > > > set when EDAC can be used. > > > > Can't hypervisor tell you that? > > No, it can't. This is not an architecture feature, and KVM will gladly > inject an UNDEF exception if the guest tries to use this. > > Which is yet another reason why this whole exercise is futile. Hi Marc - could you clarify why this is futile for baremetal or were you just referring to virtualized environments? Thanks! Tyler > > M. > > -- > Without deviation from the norm, progress is not possible.