[RFC PATCH v1 01/18] x86: Set the write-protect cache mode for AMD processors

Tom Lendacky
2016-04-26T22:45:20Z

For AMD processors that support PAT, set the write-protect cache mode
(_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05).

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
arch/x86/mm/pat.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index fb0604f..dda78ed 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -345,6 +345,8 @@ void pat_init(void)
* we lose performance without causing a correctness issue.
* Pentium 4 erratum N46 is an example for such an erratum,
* although we try not to use PAT at all on affected CPUs.
+ * AMD processors support write-protect so initialize the
+ * PAT slot 5 appropriately.
*
* PTE encoding:
* PAT
@@ -356,7 +358,7 @@ void pat_init(void)
* 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
* 011 3 UC : _PAGE_CACHE_MODE_UC
* 100 4 WB : Reserved
- * 101 5 WC : Reserved
+ * 101 5 WC : Reserved (AMD: _PAGE_CACHE_MODE_WP)
* 110 6 UC-: Reserved
* 111 7 WT : _PAGE_CACHE_MODE_WT
*
@@ -364,7 +366,12 @@ void pat_init(void)
* corresponding types in the presence of PAT errata.
*/
pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
- PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, WT);
+ PAT(4, WB) | PAT(6, UC_MINUS) | PAT(7, WT);
+
+ if (c->x86_vendor == X86_VENDOR_AMD)
+ pat |= PAT(5, WP);
+ else
+ pat |= PAT(5, WC);
}

if (!boot_cpu_done) {