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From: Himanshu Chauhan <hchauhan@ventanamicro.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org,
	acpica-devel@lists.linux.dev
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org,
	james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org,
	conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com,
	sunilvl@ventanamicro.com, apatel@ventanamicro.com,
	Himanshu Chauhan <hchauhan@ventanamicro.com>
Subject: [RFC PATCH v1 10/10] riscv: Enable APEI and NMI safe cmpxchg options required for RAS
Date: Thu, 27 Feb 2025 18:06:28 +0530	[thread overview]
Message-ID: <20250227123628.2931490-11-hchauhan@ventanamicro.com> (raw)
In-Reply-To: <20250227123628.2931490-1-hchauhan@ventanamicro.com>

Enable the APEI option so that APEI GHES options are visible.
Enable SAFE_CMPXCHG option required for GHES error handling.

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
---
 arch/riscv/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7612c52e9b1e..baf97a4f6830 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -54,6 +54,7 @@ config RISCV
 	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
 	select ARCH_HAS_UBSAN
 	select ARCH_HAS_VDSO_TIME_DATA
+	select ARCH_HAVE_NMI_SAFE_CMPXCHG
 	select ARCH_KEEP_MEMBLOCK if ACPI
 	select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE	if 64BIT && MMU
 	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
@@ -175,6 +176,7 @@ config RISCV
 	select HAVE_MOVE_PUD
 	select HAVE_PAGE_SIZE_4KB
 	select HAVE_PCI
+	select HAVE_ACPI_APEI if ACPI
 	select HAVE_PERF_EVENTS
 	select HAVE_PERF_REGS
 	select HAVE_PERF_USER_STACK_DUMP
-- 
2.43.0


  parent reply	other threads:[~2025-02-27 12:37 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-27 12:36 [RFC PATCH v1 00/10] Add RAS support for RISC-V architecture Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 01/10] riscv: Define ioremap_cache for RISC-V Himanshu Chauhan
2025-05-05 12:32   ` Anup Patel
2025-02-27 12:36 ` [RFC PATCH v1 02/10] riscv: Define arch_apei_get_mem_attribute " Himanshu Chauhan
2025-02-27 12:57   ` Clément Léger
2025-02-27 12:36 ` [RFC PATCH v1 03/10] acpi: Introduce SSE in HEST notification types Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 04/10] riscv: Add fixmap indices for GHES IRQ and SSE contexts Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 05/10] riscv: conditionally compile GHES NMI spool function Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 06/10] riscv: Add functions to register ghes having SSE notification Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 07/10] riscv: Add RISC-V entries in processor type and ISA strings Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 08/10] riscv: Introduce HEST SSE notification handlers Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 09/10] riscv: Add config option to enable APEI SSE handler Himanshu Chauhan
2025-02-27 12:36 ` Himanshu Chauhan [this message]
2025-09-12  7:30 ` [RFC PATCH v1 00/10] Add RAS support for RISC-V architecture Ruidong Tian

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