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From: Sohil Mehta <sohil.mehta@intel.com>
To: x86@kernel.org, Dave Hansen <dave.hansen@linux.intel.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>
Cc: Jonathan Corbet <corbet@lwn.net>,
	"H . Peter Anvin" <hpa@zytor.com>,
	Andy Lutomirski <luto@kernel.org>,
	Josh Poimboeuf <jpoimboe@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Ard Biesheuvel <ardb@kernel.org>,
	"Kirill A . Shutemov" <kas@kernel.org>,
	Sohil Mehta <sohil.mehta@intel.com>, Xin Li <xin@zytor.com>,
	David Woodhouse <dwmw@amazon.co.uk>,
	Sean Christopherson <seanjc@google.com>,
	Rick Edgecombe <rick.p.edgecombe@intel.com>,
	Vegard Nossum <vegard.nossum@oracle.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	David Laight <david.laight.linux@gmail.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Kees Cook <kees@kernel.org>, Tony Luck <tony.luck@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-efi@vger.kernel.org
Subject: [PATCH v10 14/15] x86/traps: Provide additional hints for a kernel stack segment fault
Date: Mon,  6 Oct 2025 23:51:18 -0700	[thread overview]
Message-ID: <20251007065119.148605-15-sohil.mehta@intel.com> (raw)
In-Reply-To: <20251007065119.148605-1-sohil.mehta@intel.com>

From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>

Kernel triggered #SS exceptions are rare, and the faulting instruction
may not even have a memory operand. In cases where it does, hints about
the cause of the fault can be useful.

LASS throws a #GP for any violation except for stack register access,
which instead triggers a #SS. Handle a kernel #SS similarly to a #GP and
reuse the address decode logic to provide additional hints, such as a
non-canonical address or an LASS violation.

In case of FRED, before handling #SS as a kernel violation, check if
there's a fixup for the exception. Redirect the #SS due to invalid user
context on ERETU to userspace. See commit 5105e7687ad3 ("x86/fred: Fixup
fault on ERETU by jumping to fred_entrypoint_user") for details.

Originally-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
---
v10:
 - Remove the LASS feature check to always provide hints independent of
   LASS being enabled.
 - Update printk to use KERN_DEFAULT (checkpatch warning).
 - Add code comments.
---
 arch/x86/kernel/traps.c | 43 +++++++++++++++++++++++++++++++++++------
 1 file changed, 37 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 3ee8a36a4e6a..864c614cddab 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -418,12 +418,6 @@ DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)
 		      SIGBUS, 0, NULL);
 }
 
-DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)
-{
-	do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS,
-		      0, NULL);
-}
-
 DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)
 {
 	char *str = "alignment check";
@@ -873,6 +867,43 @@ DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
 	cond_local_irq_disable(regs);
 }
 
+#define SSFSTR "stack segment fault"
+
+DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)
+{
+	enum kernel_exc_hint hint;
+	unsigned long exc_addr;
+
+	if (user_mode(regs))
+		goto error_trap;
+
+	/*
+	 * With FRED enabled, an invalid user context can lead to an #SS
+	 * trap on ERETU. Fixup the exception and redirect the fault to
+	 * userspace in that case.
+	 */
+	if (cpu_feature_enabled(X86_FEATURE_FRED) &&
+	    fixup_exception(regs, X86_TRAP_SS, error_code, 0))
+		return;
+
+	if (notify_die(DIE_TRAP, SSFSTR, regs, error_code, X86_TRAP_SS, SIGBUS) == NOTIFY_STOP)
+		return;
+
+	hint = get_kernel_exc_address(regs, &exc_addr);
+	if (hint != EXC_NO_HINT)
+		printk(KERN_DEFAULT SSFSTR ", %s 0x%lx", kernel_exc_hint_help[hint], exc_addr);
+
+	/* KASAN only cares about the non-canonical case, clear it otherwise */
+	if (hint != EXC_NON_CANONICAL)
+		exc_addr = 0;
+
+	die_addr(SSFSTR, regs, error_code, exc_addr);
+	return;
+
+error_trap:
+	do_error_trap(regs, error_code, SSFSTR, X86_TRAP_SS, SIGBUS, 0, NULL);
+}
+
 static bool do_int3(struct pt_regs *regs)
 {
 	int res;
-- 
2.43.0


  parent reply	other threads:[~2025-10-07  6:54 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-07  6:51 [PATCH v10 00/15] x86: Enable Linear Address Space Separation support Sohil Mehta
2025-10-07  6:51 ` [PATCH v10 01/15] x86/cpu: Enumerate the LASS feature bits Sohil Mehta
2025-10-07 18:19   ` Edgecombe, Rick P
2025-10-07 18:28     ` Dave Hansen
2025-10-07 20:20       ` Sohil Mehta
2025-10-07 20:38         ` Edgecombe, Rick P
2025-10-07 20:53           ` Sohil Mehta
2025-10-16  3:10         ` H. Peter Anvin
2025-10-07 20:49     ` Sohil Mehta
2025-10-07 23:16       ` Xin Li
2025-10-08 16:00         ` Edgecombe, Rick P
2025-10-16 15:35   ` Borislav Petkov
2025-10-21 18:03     ` Sohil Mehta
2025-10-07  6:51 ` [PATCH v10 02/15] x86/asm: Introduce inline memcpy and memset Sohil Mehta
2025-10-21 12:47   ` Borislav Petkov
2025-10-21 13:48     ` David Laight
2025-10-21 18:06     ` Sohil Mehta
2025-10-07  6:51 ` [PATCH v10 03/15] x86/alternatives: Disable LASS when patching kernel alternatives Sohil Mehta
2025-10-07 16:55   ` Edgecombe, Rick P
2025-10-07 22:28     ` Sohil Mehta
2025-10-08 16:22       ` Edgecombe, Rick P
2025-10-10 17:10         ` Sohil Mehta
2025-10-21 20:03   ` Borislav Petkov
2025-10-21 20:55     ` Sohil Mehta
2025-10-22  9:56       ` Borislav Petkov
2025-10-22 19:49         ` Sohil Mehta
2025-10-22 20:03           ` Luck, Tony
2025-10-22  8:25     ` Peter Zijlstra
2025-10-22  9:40       ` Borislav Petkov
2025-10-22 10:22         ` Peter Zijlstra
2025-10-22 10:52           ` Borislav Petkov
2025-10-07  6:51 ` [PATCH v10 04/15] x86/cpu: Set LASS CR4 bit as pinning sensitive Sohil Mehta
2025-10-07 18:24   ` Edgecombe, Rick P
2025-10-07 23:11     ` Sohil Mehta
2025-10-08 16:52       ` Edgecombe, Rick P
2025-10-10 19:03         ` Sohil Mehta
2025-10-07  6:51 ` [PATCH v10 05/15] x86/cpu: Defer CR pinning enforcement until late_initcall() Sohil Mehta
2025-10-07 17:23   ` Edgecombe, Rick P
2025-10-07 23:05     ` Sohil Mehta
2025-10-08 17:36       ` Edgecombe, Rick P
2025-10-10 20:45         ` Sohil Mehta
2025-10-15 21:17           ` Sohil Mehta
2025-10-17 19:28   ` Sohil Mehta
2025-10-07  6:51 ` [PATCH v10 06/15] x86/efi: Disable LASS while mapping the EFI runtime services Sohil Mehta
2025-10-07  6:51 ` [PATCH v10 07/15] x86/kexec: Disable LASS during relocate kernel Sohil Mehta
2025-10-07 17:43   ` Edgecombe, Rick P
2025-10-07 22:33     ` Sohil Mehta
2025-10-07  6:51 ` [PATCH v10 08/15] x86/vsyscall: Reorganize the page fault emulation code Sohil Mehta
2025-10-07 18:37   ` Edgecombe, Rick P
2025-10-07 18:48     ` Dave Hansen
2025-10-07 19:53       ` Edgecombe, Rick P
2025-10-07 22:52         ` Sohil Mehta
2025-10-08 17:42           ` Edgecombe, Rick P
2025-10-30 16:58       ` Andy Lutomirski
2025-10-30 17:22         ` H. Peter Anvin
2025-10-30 17:35           ` Andy Lutomirski
2025-10-30 19:28         ` Sohil Mehta
2025-10-30 21:37           ` David Laight
2025-10-07  6:51 ` [PATCH v10 09/15] x86/traps: Consolidate user fixups in exc_general_protection() Sohil Mehta
2025-10-07 17:46   ` Edgecombe, Rick P
2025-10-07 22:41     ` Sohil Mehta
2025-10-08 17:43       ` Edgecombe, Rick P
2025-10-07  6:51 ` [PATCH v10 10/15] x86/vsyscall: Add vsyscall emulation for #GP Sohil Mehta
2025-10-07  6:51 ` [PATCH v10 11/15] x86/vsyscall: Disable LASS if vsyscall mode is set to EMULATE Sohil Mehta
2025-10-07 18:43   ` Edgecombe, Rick P
2025-10-07  6:51 ` [PATCH v10 12/15] x86/traps: Communicate a LASS violation in #GP message Sohil Mehta
2025-10-07 18:07   ` Edgecombe, Rick P
2025-10-07  6:51 ` [PATCH v10 13/15] x86/traps: Generalize #GP address decode and hint code Sohil Mehta
2025-10-07 18:43   ` Edgecombe, Rick P
2025-10-07  6:51 ` Sohil Mehta [this message]
2025-10-07  6:51 ` [PATCH v10 15/15] x86/cpu: Enable LASS by default during CPU initialization Sohil Mehta
2025-10-07 18:42   ` Edgecombe, Rick P
2025-10-07 16:23 ` [PATCH v10 00/15] x86: Enable Linear Address Space Separation support Edgecombe, Rick P
2025-10-17 19:52   ` Sohil Mehta

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