From: Ira Weiny <ira.weiny@intel.com>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>,
<linux-efi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-cxl@vger.kernel.org>
Cc: Ard Biesheuvel <ardb@kernel.org>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
"Ira Weiny" <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Yazen Ghannam <yazen.ghannam@amd.com>,
Terry Bowman <terry.bowman@amd.com>,
"Smita Koralahalli" <Smita.KoralahalliChannabasappa@amd.com>
Subject: Re: [PATCH v7 2/2] cxl/pci: Add trace logging for CXL PCIe Port RAS errors
Date: Tue, 4 Mar 2025 11:45:08 -0600 [thread overview]
Message-ID: <67c73c24431ee_f1e0294e1@iweiny-mobl.notmuch> (raw)
In-Reply-To: <20250226221157.149406-3-Smita.KoralahalliChannabasappa@amd.com>
Smita Koralahalli wrote:
> The CXL drivers use kernel trace functions for logging endpoint and
> Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality
> is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL
> Upstream Switch Ports.
>
> Introduce trace logging functions for both RAS correctable and
> uncorrectable errors specific to CXL PCIe Ports. Use them to trace
> FW-First Protocol errors.
>
> Co-developed-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
[snip]
next prev parent reply other threads:[~2025-03-04 17:45 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-26 22:11 [PATCH v7 0/2] acpi/ghes, cper, cxl: Process CXL CPER Protocol errors Smita Koralahalli
2025-02-26 22:11 ` [PATCH v7 1/2] acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors Smita Koralahalli
2025-03-04 17:44 ` Ira Weiny
2025-03-05 0:56 ` Ira Weiny
2025-03-04 19:57 ` Yazen Ghannam
2025-03-04 20:16 ` Koralahalli Channabasappa, Smita
2025-02-26 22:11 ` [PATCH v7 2/2] cxl/pci: Add trace logging for CXL PCIe Port RAS errors Smita Koralahalli
2025-03-04 17:45 ` Ira Weiny [this message]
2025-03-04 18:56 ` Alison Schofield
2025-03-04 20:33 ` Koralahalli Channabasappa, Smita
2025-03-04 21:10 ` Alison Schofield
2025-03-04 21:21 ` Alison Schofield
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=67c73c24431ee_f1e0294e1@iweiny-mobl.notmuch \
--to=ira.weiny@intel.com \
--cc=Jonathan.Cameron@huawei.com \
--cc=Smita.KoralahalliChannabasappa@amd.com \
--cc=alison.schofield@intel.com \
--cc=ardb@kernel.org \
--cc=dan.j.williams@intel.com \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-efi@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=terry.bowman@amd.com \
--cc=vishal.l.verma@intel.com \
--cc=yazen.ghannam@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox