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From: "Koralahalli Channabasappa, Smita" <Smita.KoralahalliChannabasappa@amd.com>
To: "Luck, Tony" <tony.luck@intel.com>
Cc: linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-cxl@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Yazen Ghannam <yazen.ghannam@amd.com>,
	Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v6 5/6] acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors
Date: Wed, 12 Feb 2025 13:04:39 -0800	[thread overview]
Message-ID: <ab7d50b3-4125-4449-bfd2-eb04e76b0010@amd.com> (raw)
In-Reply-To: <Z6ES_MZy2FuRsfjF@agluck-desk3>

On 2/3/2025 11:03 AM, Luck, Tony wrote:
> On Thu, Jan 23, 2025 at 08:44:20AM +0000, Smita Koralahalli wrote:
>> When PCIe AER is in FW-First, OS should process CXL Protocol errors from
>> CPER records. Introduce support for handling and logging CXL Protocol
>> errors.
>>
>> The defined trace events cxl_aer_uncorrectable_error and
>> cxl_aer_correctable_error trace native CXL AER endpoint errors. Reuse them
>> to trace FW-First Protocol errors.
>>
>> Since the CXL code is required to be called from process context and
>> GHES is in interrupt context, use workqueues for processing.
>>
>> Similar to CXL CPER event handling, use kfifo to handle errors as it
>> simplifies queue processing by providing lock free fifo operations.
>>
>> Add the ability for the CXL sub-system to register a workqueue to
>> process CXL CPER protocol errors.
>>
>> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
>> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
>> ---
>>   drivers/acpi/apei/ghes.c | 49 ++++++++++++++++++++++++++++++++++++++++
>>   drivers/cxl/core/pci.c   | 36 +++++++++++++++++++++++++++++
>>   drivers/cxl/cxlpci.h     |  5 ++++
>>   drivers/cxl/pci.c        | 46 ++++++++++++++++++++++++++++++++++++-
>>   include/cxl/event.h      | 15 ++++++++++++
>>   5 files changed, 150 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
>> index 4d725d988c43..289e365f84b2 100644
>> --- a/drivers/acpi/apei/ghes.c
>> +++ b/drivers/acpi/apei/ghes.c
>> @@ -674,6 +674,15 @@ static void ghes_defer_non_standard_event(struct acpi_hest_generic_data *gdata,
>>   	schedule_work(&entry->work);
>>   }
>>   
>> +/* Room for 8 entries */
> 
> Any science behind the choice of "8" here? This comment is merely
> stating what the #define is used for, not why 8 was chosen.
> 

The choice of "8" was arbitrary and not based on a specific rationale. 
If there are better heuristics or considerations for determining the 
optimal number of entries, I’d appreciate any suggestions.

Thanks
Smita

  reply	other threads:[~2025-02-12 21:04 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-23  8:44 [PATCH v6 0/6] acpi/ghes, cper, cxl: Process CXL CPER Protocol errors Smita Koralahalli
2025-01-23  8:44 ` [PATCH v6 1/6] efi/cper, cxl: Prefix protocol error struct and function names with cxl_ Smita Koralahalli
2025-02-04  0:12   ` Fan Ni
2025-02-05 19:17   ` Gregory Price
2025-01-23  8:44 ` [PATCH v6 2/6] efi/cper, cxl: Make definitions and structures global Smita Koralahalli
2025-02-04  0:16   ` Fan Ni
2025-02-05 19:16   ` Gregory Price
2025-02-06 10:54     ` Jonathan Cameron
2025-02-06 16:14       ` Gregory Price
2025-02-06 17:14         ` Konstantin Ryabitsev
2025-02-06 17:32           ` Gregory Price
2025-01-23  8:44 ` [PATCH v6 3/6] efi/cper, cxl: Remove cper_cxl.h Smita Koralahalli
2025-02-04  0:20   ` Fan Ni
2025-02-05 19:18   ` Gregory Price
2025-01-23  8:44 ` [PATCH v6 4/6] acpi/ghes, cper: Recognize and cache CXL Protocol errors Smita Koralahalli
2025-02-03 18:59   ` Luck, Tony
2025-02-05 19:35     ` Gregory Price
2025-02-05 22:21   ` Dan Williams
2025-07-22 19:24   ` "invalid agent type: 1" in " Marc Herbert
2025-07-23  7:13     ` Marc Herbert
2025-07-24 14:49       ` Fabio M. De Francesco
2025-07-25 11:04         ` Jonathan Cameron
2025-07-28 15:01       ` dan.j.williams
2025-07-28 16:25     ` Koralahalli Channabasappa, Smita
2025-07-29  5:41       ` Marc Herbert
2025-07-29 15:52         ` Koralahalli Channabasappa, Smita
2025-07-29 17:39           ` dan.j.williams
2025-01-23  8:44 ` [PATCH v6 5/6] acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors Smita Koralahalli
2025-02-03 19:03   ` Luck, Tony
2025-02-12 21:04     ` Koralahalli Channabasappa, Smita [this message]
2025-02-05 19:50   ` Gregory Price
2025-02-05 22:58   ` Dan Williams
2025-02-12 20:57     ` Koralahalli Channabasappa, Smita
2025-01-23  8:44 ` [PATCH v6 6/6] cxl/pci: Add trace logging for CXL PCIe Port RAS errors Smita Koralahalli
2025-01-24 16:36   ` Ira Weiny
2025-02-05 20:01   ` Gregory Price
2025-02-05 23:06   ` Dan Williams
2025-02-03 17:09 ` [PATCH v6 0/6] acpi/ghes, cper, cxl: Process CXL CPER Protocol errors Dave Jiang
2025-02-06 18:38 ` Dave Jiang

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