Re: [PATCH v6 0/3] riscv32 library enhancements and build fixes

[Andy Shevchenko <andriy.shevchenko@intel.com>]

On Mon, Apr 27, 2026 at 11:13:20AM +0300, Dmitry Antipov wrote:
> On Sat, 2026-04-25 at 14:36 -0700, Andrew Morton wrote:
> 
> > I didn't upstream "lib and lib/cmdline enhancements v9" this cycle.
> 
> You don't have to upstream v9. Because v9 is v8 + initial RISC-V build
> fix, which is a part of another series (this one) now. The proper sequence
> is v8 + this series.
> 
> > So can we please sort through these things (and the AI review) before
> > adding more?
> 
> Not sure about AI but hopefully human should realize that I'm not an
> expert in m68k/sparc32/xtensa/csky/[your favorite arch here]. Enabling
> and running the test on _all_ architectures where it is expected to 
> work requires obtaining (or even building by myself) a cross-compiler,
> setting up the kernel and QEMU, etc. I've spent a reasonable time with
> RISC-V and ARM and hopefully set up a good starting point for 
> m68k/sparc32/xtensa/csky/[your favorite arch here] maintainers, who are
> free to incorporate the test into their target architecture.
> 
> I'm going to fix everything I consider reasonable, submit v7 and give up -
> because without even a single reply from core RISC-V maintainers, this
> just turns into an endless brain masturbation.

I believe it's better to issue v10 of that series + v7 of this in one go.

-- 
With Best Regards,
Andy Shevchenko