From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Lendacky Subject: Re: [RFC PATCH v3 04/20] x86: Handle reduction in physical address size with SME Date: Tue, 15 Nov 2016 10:06:16 -0600 Message-ID: References: <20161110003426.3280.2999.stgit@tlendack-t1.amdoffice.net> <20161110003513.3280.12104.stgit@tlendack-t1.amdoffice.net> <20161115121035.GD24857@8bytes.org> <20161115121456.f4slpk4i2jl3e2ke@pd.tnic> <20161115153338.a2cxmatnpqcgiaiy@pd.tnic> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20161115153338.a2cxmatnpqcgiaiy-fF5Pk5pvG8Y@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Borislav Petkov Cc: linux-efi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Matt Fleming , x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org, Alexander Potapenko , "H. Peter Anvin" , Larry Woodman , linux-arch-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Jonathan Corbet , linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kasan-dev-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Ingo Molnar , Andrey Ryabinin , Rik van Riel , Arnd Bergmann , Andy Lutomirski , Thomas Gleixner , Dmitry Vyukov , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, Paolo Bonzini List-Id: linux-efi@vger.kernel.org On 11/15/2016 9:33 AM, Borislav Petkov wrote: > On Tue, Nov 15, 2016 at 08:40:05AM -0600, Tom Lendacky wrote: >> The feature may be present and enabled even if it is not currently >> active. In other words, the SYS_CFG MSR bit could be set but we aren't >> actually using encryption (sme_me_mask is 0). As long as the SYS_CFG >> MSR bit is set we need to take into account the physical reduction in >> address space. > > But later in the series I see sme_early_mem_enc() which tests exactly > that mask. Yes, but that doesn't relate to the physical address space reduction. Once the SYS_CFG MSR bit for SME is set, even if the encryption bit is never used, there is a physical reduction of the address space. So when checking whether to adjust the physical address bits I can't rely on the sme_me_mask, I have to look at the MSR. But when I'm looking to decide whether to encrypt or decrypt something, I use the sme_me_mask to decide if that is needed. If the sme_me_mask is not set then the encrypt/decrypt op shouldn't be performed. I might not be grasping the point you're trying to make... Thanks, Tom > > And in patch 12 you have: > > + /* > + * If memory encryption is active, the trampoline area will need to > + * be in un-encrypted memory in order to bring up other processors > + * successfully. > + */ > + sme_early_mem_dec(__pa(base), size); > + sme_set_mem_unenc(base, size); > > What's up? > > IOW, it all sounds to me like you want to have an sme_active() helper > and use it everywhere. >