Re: [PATCH v10 01/15] x86/cpu: Enumerate the LASS feature bits

Edgecombe, Rick P
2025-10-07T20:38:28Z

On Tue, 2025-10-07 at 13:20 -0700, Sohil Mehta wrote:
> > STAC/CLAC are also architected to:
> >
> >   #UD - If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
> >
> > So, even though LASS _technically_ doesn't require SMAP, it would be a
> > real pain without SMAP and STAC/CLAC. Thus, this series relies on SMAP
> > being present.

Ah, ok.

>
>
> The spec says,
> "A supervisor-mode data access causes a LASS violation if it would
> access a linear address of which bit 63 is 0, supervisor-mode access
> protection is enabled (by setting CR4.SMAP), and either RFLAGS.AC = 0 or
> the access is an implicit supervisor-mode access."
>
> One could argue that the LASS hardware enforcement of the kernel data
> accesses *depends* on SMAP being enabled.

The fetch part doesn't though?