/*
 *  linux/drivers/video/vgaops.h -- Low level frame buffer operations
 *				     for VGA 4-plane modes
 *
 * Copyright 1999 Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
 * Based on code by Michael Schmitz
 * Based on the old macfb.c 4bpp code by Alan Cox
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License.  See the file COPYING in the main directory of this
 * archive for more details.  */


#define GRAPHICS_ADDR_REG 0x3ce		/* Graphics address register. */
#define GRAPHICS_DATA_REG 0x3cf		/* Graphics data register. */

#define SET_RESET_INDEX 0		/* Set/Reset Register index. */
#define ENABLE_SET_RESET_INDEX 1	/* Enable Set/Reset Register index. */
#define DATA_ROTATE_INDEX 3		/* Data Rotate Register index. */
#define GRAPHICS_MODE_INDEX 5		/* Graphics Mode Register index. */
#define BIT_MASK_INDEX 8		/* Bit Mask Register index. */

/* The VGA's weird architecture often requires that we read a byte and
   write a byte to the same location.  It doesn't matter *what* byte
   we write, however.  This is because all the action goes on behind
   the scenes in the VGA's 32-bit latch register, and reading and writing
   video memory just invokes latch behavior.

   To avoid race conditions (is this necessary?), reading and writing
   the memory byte should be done with a single instruction.  One
   suitable instruction is the x86 bitwise OR.  The following
   read-modify-write routine should optimize to one such bitwise
   OR. */
#define rmw(p) \
{ \
	readb(p); \
	writeb(1, p); \
} \

/* Set the Graphics Mode Register.  Bits 0-1 are write mode, bit 3 is
   read mode. */
#define setmode(mode)                                 \
{                                                     \
	outb(GRAPHICS_MODE_INDEX, GRAPHICS_ADDR_REG); \
	outb(mode, GRAPHICS_DATA_REG);                \
}

/* Select the Bit Mask Register. */
#define selectmask()                                  \
{                                                     \
	outb(BIT_MASK_INDEX, GRAPHICS_ADDR_REG);      \
}

/* Set the value of the Bit Mask Register.  It must already have been
   selected with selectmask(). */
#define setmask(mask)                                 \
{                                                     \
	outb(mask, GRAPHICS_DATA_REG);                \
}

/* Set the Data Rotate Register.  Bits 0-2 are rotate count, bits 3-4
   are logical operation (0=NOP, 1=AND, 2=OR, 3=XOR). */
#define setop(op)                                    \
{                                                    \
	outb(DATA_ROTATE_INDEX, GRAPHICS_ADDR_REG);  \
	outb(op, GRAPHICS_DATA_REG);                 \
}

/* Set the Enable Set/Reset Register.  The code here always uses value
   0xf for this register.  */
#define setsr(sr)                                        \
{                                                        \
	outb(ENABLE_SET_RESET_INDEX, GRAPHICS_ADDR_REG); \
	outb(sr, GRAPHICS_DATA_REG);                     \
}

/* Set the Set/Reset Register. */
#define setcolor(color)                              \
{                                                    \
	outb(SET_RESET_INDEX, GRAPHICS_ADDR_REG);    \
	outb(color, GRAPHICS_DATA_REG);              \
}

/* Set the value in the Graphics Address Register. */
#define setindex(index)                              \
{                                                    \
	outb(index, GRAPHICS_ADDR_REG);              \
}