From: Antonino Daplas <adaplas@pol.net>
To: Andrea Mazzoleni <amadvance@users.sourceforge.net>
Cc: Linux Fbdev development list <linux-fbdev-devel@lists.sourceforge.net>
Subject: Re: Possible Bug in radeonfb (?)
Date: 26 Feb 2003 16:02:55 +0800 [thread overview]
Message-ID: <1046246472.11751.44.camel@localhost.localdomain> (raw)
In-Reply-To: <20030225182115.GB2487@elitel.biz>
On Wed, 2003-02-26 at 02:21, Andrea Mazzoleni wrote:
> In radeonfb (2.4.20) I have found a possible inconsistency.
>
> In the PLL clock computation the initial range check compares the
> requested clock with the value pll_min/12. But immeditially later
> I see that the higher PLL post divider is 16 and not 12.
>
> Is it correct ? Or the check should use 16 instead of 12 ?
>
Probably does not matter, unless you intend to use very, very low
dotclocks (< 10MHz).
Tony
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next prev parent reply other threads:[~2003-02-26 8:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-02-25 18:21 Possible Bug in radeonfb (?) Andrea Mazzoleni
2003-02-26 8:02 ` Antonino Daplas [this message]
2003-02-27 18:00 ` Andrea Mazzoleni
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