* [PATCH] s3c2410fb: byte ordering fixes
@ 2007-08-14 16:26 Krzysztof Helt
2007-09-09 9:28 ` Krzysztof Helt
0 siblings, 1 reply; 6+ messages in thread
From: Krzysztof Helt @ 2007-08-14 16:26 UTC (permalink / raw)
To: linux-fbdev-devel; +Cc: ben-linux
[-- Attachment #1: Type: text/plain, Size: 2604 bytes --]
From: Krzysztof Helt <krzysztof.h1@wp.pl>
This patch sets correct bits related to the byte ordering
of the framebuffer. This was tested on little endian kernel
only. The big endian kernel may require different settings.
The patch also adds 32 bpp mode which is called 24 bpp by
Samsung. One pixel takes 32 bits but only 24 bits are used
in this mode.
Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
---
This patch requires all s3c2410fb patches sent to this list.
The patch was tested on iPAQ rx1950 (TFT display only).
The 1, 2 and 4 bpp modes do not work on little endian kernel
(wrong order of pixels in byte). 1bpp is not stable for
unknown reason.
diff -urp linux-2.6.23.old/drivers/video/s3c2410fb.c linux-2.6.
23/drivers/video/s3c2410fb.c
--- linux-2.6.23.old/drivers/video/s3c2410fb.c 2007-08-13 20:
21:57.000000000 +0200
+++ linux-2.6.23/drivers/video/s3c2410fb.c 2007-08-13 20:46:
18.000000000 +0200
@@ -270,8 +270,8 @@ static int s3c2410fb_check_var(struct fb
var->blue.length = 5;
}
break;
- case 24:
- /* 24 bpp 888 */
+ case 32:
+ /* 24 bpp 888 and 8 dummy */
var->red.length = 8;
var->red.offset = 16;
var->green.length = 8;
@@ -279,8 +279,6 @@ static int s3c2410fb_check_var(struct fb
var->blue.length = 8;
var->blue.offset = 0;
break;
-
-
}
return 0;
}
@@ -379,11 +377,21 @@ static void s3c2410fb_calculate_tft_lcd_
break;
case 8:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
+ regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
+ S3C2410_LCDCON5_FRM565;
+ regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
break;
case 16:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
+ regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
+ regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
+ break;
+ case 32:
+ regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
+ regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
+ S3C2410_LCDCON5_HWSWP |
+ S3C2410_LCDCON5_BPP24BL);
break;
-
default:
/* invalid pixel depth */
dev_err(fbi->dev, "invalid bpp %d\n",
@@ -475,7 +483,9 @@ static int s3c2410fb_set_par(struct fb_i
struct fb_var_screeninfo *var = &info->var;
switch (var->bits_per_pixel) {
+ case 32:
case 16:
+ case 12:
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 1:
----------------------------------------------------
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[-- Attachment #2: s3c2410fb-32bpp.diff --]
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From: Krzysztof Helt <krzysztof.h1@wp.pl>
This patch sets correct bits related to the byte ordering
of the framebuffer. This was tested on little endian kernel
only. The big endian kernel may require different settings.
The patch also adds 32 bpp mode which is called 24 bpp by
Samsung. One pixel takes 32 bits but only 24 bits are used
in this mode.
Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
---
This patch requires all s3c2410fb patches sent to this list.
The patch was tested on iPAQ rx1950 (TFT display only).
The 1, 2 and 4 bpp modes do not work on little endian kernel
(wrong order of pixels in byte).
diff -urp linux-2.6.23.old/drivers/video/s3c2410fb.c linux-2.6.23/drivers/video/s3c2410fb.c
--- linux-2.6.23.old/drivers/video/s3c2410fb.c 2007-08-13 20:21:57.000000000 +0200
+++ linux-2.6.23/drivers/video/s3c2410fb.c 2007-08-13 20:46:18.000000000 +0200
@@ -270,8 +270,8 @@ static int s3c2410fb_check_var(struct fb
var->blue.length = 5;
}
break;
- case 24:
- /* 24 bpp 888 */
+ case 32:
+ /* 24 bpp 888 and 8 dummy */
var->red.length = 8;
var->red.offset = 16;
var->green.length = 8;
@@ -279,8 +279,6 @@ static int s3c2410fb_check_var(struct fb
var->blue.length = 8;
var->blue.offset = 0;
break;
-
-
}
return 0;
}
@@ -379,11 +377,21 @@ static void s3c2410fb_calculate_tft_lcd_
break;
case 8:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
+ regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
+ S3C2410_LCDCON5_FRM565;
+ regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
break;
case 16:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
+ regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
+ regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
+ break;
+ case 32:
+ regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
+ regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
+ S3C2410_LCDCON5_HWSWP |
+ S3C2410_LCDCON5_BPP24BL);
break;
-
default:
/* invalid pixel depth */
dev_err(fbi->dev, "invalid bpp %d\n",
@@ -475,7 +483,9 @@ static int s3c2410fb_set_par(struct fb_i
struct fb_var_screeninfo *var = &info->var;
switch (var->bits_per_pixel) {
+ case 32:
case 16:
+ case 12:
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 1:
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] s3c2410fb: byte ordering fixes
2007-08-14 16:26 [PATCH] s3c2410fb: byte ordering fixes Krzysztof Helt
@ 2007-09-09 9:28 ` Krzysztof Helt
2007-09-15 0:17 ` Antonino A. Daplas
0 siblings, 1 reply; 6+ messages in thread
From: Krzysztof Helt @ 2007-09-09 9:28 UTC (permalink / raw)
To: Antonino A. Daplas; +Cc: linux-fbdev-devel
On Tue, 14 Aug 2007 18:26:38 +0200
"Krzysztof Helt" <krzysztof.h1@wp.pl> wrote:
> From: Krzysztof Helt <krzysztof.h1@wp.pl>
>
> This patch sets correct bits related to the byte ordering
> of the framebuffer. This was tested on little endian kernel
> only. The big endian kernel may require different settings.
>
> The patch also adds 32 bpp mode which is called 24 bpp by
> Samsung. One pixel takes 32 bits but only 24 bits are used
> in this mode.
>
Tony,
This patch didn't make into the -mm tree with other s3c2410fb patches.
Please look into it.
Regards,
Krzysztof
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] s3c2410fb: byte ordering fixes
2007-09-09 9:28 ` Krzysztof Helt
@ 2007-09-15 0:17 ` Antonino A. Daplas
2007-09-15 5:52 ` Krzysztof Helt
0 siblings, 1 reply; 6+ messages in thread
From: Antonino A. Daplas @ 2007-09-15 0:17 UTC (permalink / raw)
To: Krzysztof Helt; +Cc: linux-fbdev-devel
On Sun, 2007-09-09 at 11:28 +0200, Krzysztof Helt wrote:
> On Tue, 14 Aug 2007 18:26:38 +0200
> "Krzysztof Helt" <krzysztof.h1@wp.pl> wrote:
>
> > From: Krzysztof Helt <krzysztof.h1@wp.pl>
> >
> > This patch sets correct bits related to the byte ordering
> > of the framebuffer. This was tested on little endian kernel
> > only. The big endian kernel may require different settings.
> >
> > The patch also adds 32 bpp mode which is called 24 bpp by
> > Samsung. One pixel takes 32 bits but only 24 bits are used
> > in this mode.
> >
>
> Tony,
>
> This patch didn't make into the -mm tree with other s3c2410fb patches.
> Please look into it.
Sorry, I was a bit busy for the last couple of weeks so I wasn't able to
send your patches until now.
Anyway, what s3c2410fb patches did not make it to the -mm tree?
Tony
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] s3c2410fb: byte ordering fixes
2007-09-15 0:17 ` Antonino A. Daplas
@ 2007-09-15 5:52 ` Krzysztof Helt
2007-09-15 23:17 ` Antonino A. Daplas
0 siblings, 1 reply; 6+ messages in thread
From: Krzysztof Helt @ 2007-09-15 5:52 UTC (permalink / raw)
To: Antonino A. Daplas; +Cc: linux-fbdev-devel
On Sat, 15 Sep 2007 08:17:30 +0800
"Antonino A. Daplas" <adaplas@gmail.com> wrote:
> > Tony,
> >
> > This patch didn't make into the -mm tree with other s3c2410fb patches.
> > Please look into it.
>
> Sorry, I was a bit busy for the last couple of weeks so I wasn't able to
> send your patches until now.
>
Not a problem. I understand.
> Anyway, what s3c2410fb patches did not make it to the -mm tree?
>
Only the one (byte ordering patch):
http://marc.info/?l=linux-fbdev-devel&m=118710882602191&w=2
Regards,
Krzysztof
PS. I can repost if you want.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] s3c2410fb: byte ordering fixes
2007-09-15 5:52 ` Krzysztof Helt
@ 2007-09-15 23:17 ` Antonino A. Daplas
0 siblings, 0 replies; 6+ messages in thread
From: Antonino A. Daplas @ 2007-09-15 23:17 UTC (permalink / raw)
To: Krzysztof Helt; +Cc: linux-fbdev-devel
On Sat, 2007-09-15 at 07:52 +0200, Krzysztof Helt wrote:
> On Sat, 15 Sep 2007 08:17:30 +0800
> "Antonino A. Daplas" <adaplas@gmail.com> wrote:
>
> > Anyway, what s3c2410fb patches did not make it to the -mm tree?
> >
>
> Only the one (byte ordering patch):
>
> http://marc.info/?l=linux-fbdev-devel&m=118710882602191&w=2
>
Strangely, I did not get this patch. Fortunately, it's still archived by
gmail.
Tony
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] s3c2410fb: byte ordering fixes
@ 2007-09-15 23:22 Antonino A. Daplas
0 siblings, 0 replies; 6+ messages in thread
From: Antonino A. Daplas @ 2007-09-15 23:22 UTC (permalink / raw)
To: Andrew Morton; +Cc: Krzysztof Helt, Linux Fbdev development list
From: Krzysztof Helt <krzysztof.h1@wp.pl>
This patch sets correct bits related to the byte ordering
of the framebuffer. This was tested on little endian kernel
only. The big endian kernel may require different settings.
The patch also adds 32 bpp mode which is called 24 bpp by
Samsung. One pixel takes 32 bits but only 24 bits are used
in this mode.
Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
---
drivers/video/s3c2410fb.c | 20 +++++++++++++++-----
1 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c
index 98da79c..ae08d45 100644
--- a/drivers/video/s3c2410fb.c
+++ b/drivers/video/s3c2410fb.c
@@ -278,8 +278,8 @@ static int s3c2410fb_check_var(struct fb
var->blue.length = 5;
}
break;
- case 24:
- /* 24 bpp 888 */
+ case 32:
+ /* 24 bpp 888 and 8 dummy */
var->red.length = 8;
var->red.offset = 16;
var->green.length = 8;
@@ -287,8 +287,6 @@ static int s3c2410fb_check_var(struct fb
var->blue.length = 8;
var->blue.offset = 0;
break;
-
-
}
return 0;
}
@@ -375,11 +373,21 @@ static void s3c2410fb_calculate_tft_lcd_
break;
case 8:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
+ regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
+ S3C2410_LCDCON5_FRM565;
+ regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
break;
case 16:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
+ regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
+ regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
+ break;
+ case 32:
+ regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
+ regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
+ S3C2410_LCDCON5_HWSWP |
+ S3C2410_LCDCON5_BPP24BL);
break;
-
default:
/* invalid pixel depth */
dev_err(fbi->dev, "invalid bpp %d\n",
@@ -467,7 +475,9 @@ static int s3c2410fb_set_par(struct fb_i
struct fb_var_screeninfo *var = &info->var;
switch (var->bits_per_pixel) {
+ case 32:
case 16:
+ case 12:
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 1:
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^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2007-09-15 23:24 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2007-08-14 16:26 [PATCH] s3c2410fb: byte ordering fixes Krzysztof Helt
2007-09-09 9:28 ` Krzysztof Helt
2007-09-15 0:17 ` Antonino A. Daplas
2007-09-15 5:52 ` Krzysztof Helt
2007-09-15 23:17 ` Antonino A. Daplas
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2007-09-15 23:22 Antonino A. Daplas
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