Re: [PATCH v11 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver

[Rex-BC Chen <rex-bc.chen@mediatek.com>]

On Wed, 2022-06-15 at 11:06 +0800, CK Hu wrote:
> Hi, Bo-Chen:
> 
> On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote:
> > From: Markus Schneider-Pargmann <msp@baylibre.com>
> > 
> > This patch adds a embedded displayport driver for the MediaTek
> > mt8195
> > SoC.
> > 
> > It supports the MT8195, the embedded DisplayPort units. It offers
> > DisplayPort 1.4 with up to 4 lanes.
> > 
> > The driver creates a child device for the phy. The child device
> > will
> > never exist without the parent being active. As they are sharing a
> > register range, the parent passes a regmap pointer to the child so
> > that
> > both can work with the same register range. The phy driver sets
> > device
> > data that is read by the parent to get the phy device that can be
> > used
> > to control the phy properties.
> > 
> > This driver is based on an initial version by
> > Jitao shi <jitao.shi@mediatek.com>
> > 
> > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers]
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > ---
> 
> [snip]
> 
> > +
> > +static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp)
> > +{
> > +	u8 val;
> > +	struct mtk_dp_train_info *train_info = &mtk_dp->train_info;
> > +
> > +	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER,
> > DP_SET_POWER_D0);
> > +	usleep_range(2000, 5000);
> > +
> > +	drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap);
> > +
> > +	mtk_dp->rx_cap[DP_TRAINING_AUX_RD_INTERVAL] &=
> > DP_TRAINING_AUX_RD_MASK;
> > +
> > +	train_info->link_rate = min_t(int, mtk_dp->max_linkrate,
> > +				      mtk_dp->rx_cap[mtk_dp-
> > > max_linkrate]);
> > 
> > +	train_info->lane_count = min_t(int, mtk_dp->max_lanes,
> > +				       drm_dp_max_lane_count(mtk_dp-
> > > rx_cap));
> > 
> > +
> > +	train_info->tps3 = drm_dp_tps3_supported(mtk_dp->rx_cap);
> > +	train_info->tps4 = drm_dp_tps4_supported(mtk_dp->rx_cap);
> > +
> > +	train_info->sink_ssc = !!(mtk_dp->rx_cap[DP_MAX_DOWNSPREAD] &
> > +				  DP_MAX_DOWNSPREAD_0_5);
> 
> I think this is redundant because next statement would set sink_scc
> to
> false.
> 
> Regards,
> CK
> 

Hello Ck,

I will remove "train_info->sink_ssc = false;"

BRs,
Bo-Chen
> > +
> > +	train_info->sink_ssc = false;
> > +
> > +	drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val);
> > +	if (val & DP_MST_CAP) {
> > +		/* Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 */
> > +		drm_dp_dpcd_readb(&mtk_dp->aux,
> > +				  DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0,
> > &val);
> > +		if (val)
> > +			drm_dp_dpcd_writeb(&mtk_dp->aux,
> > +					   DP_DEVICE_SERVICE_IRQ_VECTOR
> > _ESI0,
> > +					   val);
> > +	}
> > +
> > +	return 0;
> > +}
> 
>