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From: Tomi Valkeinen <tomi.valkeinen@ti.com>
To: "Mahapatra, Chandrabhanu" <cmahapatra@ti.com>,
	Archit Taneja <archit@ti.com>
Cc: linux-omap <linux-omap@vger.kernel.org>, linux-fbdev@vger.kernel.org
Subject: Re: [PATCH V2 3/3] OMAPDSS: DISPC: Correct DISPC functional clock usage
Date: Tue, 27 Mar 2012 11:26:30 +0000	[thread overview]
Message-ID: <1332847590.1867.149.camel@deskari> (raw)
In-Reply-To: <CAF0AtAuxR6pa0y_kTgh454=joFoy_kG4XCnHAS94qkPk0+kLFw@mail.gmail.com>

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On Tue, 2012-03-27 at 16:44 +0530, Mahapatra, Chandrabhanu wrote:
> On Tue, Mar 27, 2012 at 4:33 PM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote:
> > On Wed, 2012-03-21 at 15:22 +0530, Chandrabhanu Mahapatra wrote:
> >> DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling
> >> calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC.
> >> DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC
> >> divisor LCD.
> >>
> >> Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com>
> >> ---
> >>  drivers/video/omap2/dss/dispc.c |   13 +++++++------
> >>  1 files changed, 7 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
> >> index d8a1672..1fdac73 100644
> >> --- a/drivers/video/omap2/dss/dispc.c
> >> +++ b/drivers/video/omap2/dss/dispc.c
> >> @@ -1761,6 +1761,7 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
> >>                               dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
> >>       const int max_decim_limit = 16;
> >>       unsigned long fclk = 0;
> >> +     unsigned long dispc_core_clk = dispc_mgr_lclk_rate(channel);
> >
> > Hmm, I don't think this is correct. dispc_mgr_lclk_rate() returns the
> > logic clock for the LCD output path. It's not DISPC core clock.
> >
> >  Tomi
> >
> 
> As per the OMAP4 TRM DISPC_CORE_CLK is DISPC_FCLK / LCD factor and

Hmm? No it isn't. DISPC_CORE_CLK is DISPC_FCLK / LCD, where LCD is
defined in DISPC_DIVISOR register.

dispc_mgr_lclk_rate() returns the logic clock of an output, which is
LCD1_CLK / LCD1 or LCD2_CLK / LCD2. And LCD1 and LCD2 are defined in
DISPC_DIVISORo(n) register.

(Very confusing to have LCD mean a liquid-crystal-display and also
logic-clock-divisor =) I think we should rename them. Perhaps LCKD and
PCKD).

So the clocks for DISPC and for LCD outputs are totally separate ones,
on OMAP4. For OMAP2/3 they are the same.

That said, I have no idea which of the clock is used for what regarding
scaling calculations, and even less do I know how it's managed for
TV-out...

> dispc_mgr_lclk_rate() exactly does the same. Should we rename the
> function or have a separate fucntion for dispc_core_clk to avoid
> confusion?

I think we definitely should have a separate function, as it's a
separate clock. And I guess the places where FCKs and LCKs are used
should be verified so that they use the correct one. If somebody knows
what is the correct one (the TRM is a bit vague at times =).

 Tomi


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      reply	other threads:[~2012-03-27 11:26 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-21  9:53 [PATCH V2 3/3] OMAPDSS: DISPC: Correct DISPC functional clock usage Chandrabhanu Mahapatra
2012-03-27 11:03 ` Tomi Valkeinen
2012-03-27 11:26   ` Mahapatra, Chandrabhanu
2012-03-27 11:26     ` Tomi Valkeinen [this message]

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