From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Paul Date: Wed, 31 Oct 2012 17:01:57 +0000 Subject: [PATCH] video: exynos_dp: Get pll lock before pattern set Message-Id: <1351702917-1331-1-git-send-email-seanpaul@chromium.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-fbdev@vger.kernel.org According to the exynos datasheet (Figure 49-10), we should wait for PLL lock before programming the training pattern when doing software eDP link training. Signed-off-by: Sean Paul --- drivers/video/exynos/exynos_dp_core.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c index b126e8a..ef9b003 100644 --- a/drivers/video/exynos/exynos_dp_core.c +++ b/drivers/video/exynos/exynos_dp_core.c @@ -264,7 +264,7 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, static int exynos_dp_link_start(struct exynos_dp_device *dp) { u8 buf[4]; - int lane, lane_count, retval; + int lane, lane_count, pll_tries, retval; lane_count = dp->link_train.lane_count; @@ -297,6 +297,18 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0, lane); + /* Wait for PLL lock */ + pll_tries = 0; + while (exynos_dp_get_pll_lock_status(dp) = PLL_UNLOCKED) { + if (pll_tries = DP_TIMEOUT_LOOP_COUNT) { + dev_err(dp->dev, "Wait for PLL lock timed out\n"); + return -ETIMEDOUT; + } + + pll_tries++; + usleep_range(90, 120); + } + /* Set training pattern 1 */ exynos_dp_set_training_pattern(dp, TRAINING_PTN1); -- 1.7.7.3