From mboxrd@z Thu Jan 1 00:00:00 1970 From: Archit Taneja Date: Fri, 13 Sep 2013 10:41:34 +0000 Subject: [PATCH 3/7] OMAPDSS: HDMI: OMAP4: Complete register definitions for DPLL Message-Id: <1379068178-17312-4-git-send-email-archit@ti.com> List-Id: References: <1379068178-17312-1-git-send-email-archit@ti.com> In-Reply-To: <1379068178-17312-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: tomi.valkeinen@ti.com Cc: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org, Ricardo Neri , Archit Taneja From: Ricardo Neri Add missing register definitions for spread spectrum clocking. Signed-off-by: Ricardo Neri Signed-off-by: Archit Taneja --- drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h index 469d436..d1a2315 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h +++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h @@ -168,6 +168,8 @@ #define PLLCTRL_CFG1 0xC #define PLLCTRL_CFG2 0x10 #define PLLCTRL_CFG3 0x14 +#define PLLCTRL_SSC_CFG1 0x18 +#define PLLCTRL_SSC_CFG2 0x1C #define PLLCTRL_CFG4 0x20 /* HDMI PHY */ -- 1.8.1.2