* [PATCH 1/7] OMAPDSS: HDMI: OMAP4: Complete register definitions for wrapper
2013-09-13 10:41 [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions Archit Taneja
@ 2013-09-13 10:41 ` Archit Taneja
2013-09-13 10:41 ` [PATCH 2/7] OMAPDSS: HDMI: OMAP4: Complete dumping of wrapper registers Archit Taneja
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Archit Taneja @ 2013-09-13 10:41 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, linux-fbdev, Ricardo Neri, Archit Taneja
From: Ricardo Neri <ricardo.neri@ti.com>
Add definitions for missing registers in the HDMI wrapper. Also, order
the registers by offset to improve readability.
Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index 6ef2f92..469d436 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -31,9 +31,11 @@
#define HDMI_WP_SYSCONFIG 0x10
#define HDMI_WP_IRQSTATUS_RAW 0x24
#define HDMI_WP_IRQSTATUS 0x28
-#define HDMI_WP_PWR_CTRL 0x40
#define HDMI_WP_IRQENABLE_SET 0x2C
#define HDMI_WP_IRQENABLE_CLR 0x30
+#define HDMI_WP_IRQWAKEEN 0x34
+#define HDMI_WP_PWR_CTRL 0x40
+#define HDMI_WP_DEBOUNCE 0x44
#define HDMI_WP_VIDEO_CFG 0x50
#define HDMI_WP_VIDEO_SIZE 0x60
#define HDMI_WP_VIDEO_TIMING_H 0x68
--
1.8.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/7] OMAPDSS: HDMI: OMAP4: Complete dumping of wrapper registers
2013-09-13 10:41 [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions Archit Taneja
2013-09-13 10:41 ` [PATCH 1/7] OMAPDSS: HDMI: OMAP4: Complete register definitions for wrapper Archit Taneja
@ 2013-09-13 10:41 ` Archit Taneja
2013-09-13 10:41 ` [PATCH 3/7] OMAPDSS: HDMI: OMAP4: Complete register definitions for DPLL Archit Taneja
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Archit Taneja @ 2013-09-13 10:41 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, linux-fbdev, Ricardo Neri, Archit Taneja
From: Ricardo Neri <ricardo.neri@ti.com>
Add missing registers when dumping the HDMI wrapper. Also, order the dump by
offset to improve readability.
Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index 3dfe009..ecadd7a 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -859,8 +859,11 @@ void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
DUMPREG(HDMI_WP_SYSCONFIG);
DUMPREG(HDMI_WP_IRQSTATUS_RAW);
DUMPREG(HDMI_WP_IRQSTATUS);
- DUMPREG(HDMI_WP_PWR_CTRL);
DUMPREG(HDMI_WP_IRQENABLE_SET);
+ DUMPREG(HDMI_WP_IRQENABLE_CLR);
+ DUMPREG(HDMI_WP_IRQWAKEEN);
+ DUMPREG(HDMI_WP_PWR_CTRL);
+ DUMPREG(HDMI_WP_DEBOUNCE);
DUMPREG(HDMI_WP_VIDEO_CFG);
DUMPREG(HDMI_WP_VIDEO_SIZE);
DUMPREG(HDMI_WP_VIDEO_TIMING_H);
--
1.8.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/7] OMAPDSS: HDMI: OMAP4: Complete register definitions for DPLL
2013-09-13 10:41 [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions Archit Taneja
2013-09-13 10:41 ` [PATCH 1/7] OMAPDSS: HDMI: OMAP4: Complete register definitions for wrapper Archit Taneja
2013-09-13 10:41 ` [PATCH 2/7] OMAPDSS: HDMI: OMAP4: Complete dumping of wrapper registers Archit Taneja
@ 2013-09-13 10:41 ` Archit Taneja
2013-09-13 10:41 ` [PATCH 4/7] OMAPDSS: HDMI: OMAP4: Complete dumping of DPLL registers Archit Taneja
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Archit Taneja @ 2013-09-13 10:41 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, linux-fbdev, Ricardo Neri, Archit Taneja
From: Ricardo Neri <ricardo.neri@ti.com>
Add missing register definitions for spread spectrum clocking.
Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index 469d436..d1a2315 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -168,6 +168,8 @@
#define PLLCTRL_CFG1 0xC
#define PLLCTRL_CFG2 0x10
#define PLLCTRL_CFG3 0x14
+#define PLLCTRL_SSC_CFG1 0x18
+#define PLLCTRL_SSC_CFG2 0x1C
#define PLLCTRL_CFG4 0x20
/* HDMI PHY */
--
1.8.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 4/7] OMAPDSS: HDMI: OMAP4: Complete dumping of DPLL registers
2013-09-13 10:41 [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions Archit Taneja
` (2 preceding siblings ...)
2013-09-13 10:41 ` [PATCH 3/7] OMAPDSS: HDMI: OMAP4: Complete register definitions for DPLL Archit Taneja
@ 2013-09-13 10:41 ` Archit Taneja
2013-09-13 10:41 ` [PATCH 5/7] OMAPDSS: HDMI: OMAP4: Rename the HDMI_CORE_CTRL1 register Archit Taneja
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Archit Taneja @ 2013-09-13 10:41 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, linux-fbdev, Ricardo Neri, Archit Taneja
From: Ricardo Neri <ricardo.neri@ti.com>
Add the spread spectrum clock configuration registers to the DPLL dump.
Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index ecadd7a..46af726 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -886,6 +886,8 @@ void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
DUMPPLL(PLLCTRL_CFG1);
DUMPPLL(PLLCTRL_CFG2);
DUMPPLL(PLLCTRL_CFG3);
+ DUMPPLL(PLLCTRL_SSC_CFG1);
+ DUMPPLL(PLLCTRL_SSC_CFG2);
DUMPPLL(PLLCTRL_CFG4);
}
--
1.8.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 5/7] OMAPDSS: HDMI: OMAP4: Rename the HDMI_CORE_CTRL1 register
2013-09-13 10:41 [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions Archit Taneja
` (3 preceding siblings ...)
2013-09-13 10:41 ` [PATCH 4/7] OMAPDSS: HDMI: OMAP4: Complete dumping of DPLL registers Archit Taneja
@ 2013-09-13 10:41 ` Archit Taneja
2013-09-13 10:41 ` [PATCH 6/7] OMAPDSS: HDMI: OMAP4: Complete register definitions for core Archit Taneja
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Archit Taneja @ 2013-09-13 10:41 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, linux-fbdev, Ricardo Neri, Archit Taneja
From: Ricardo Neri <ricardo.neri@ti.com>
Rename the register to be aligned with the HDMI_CORE_SYS naming convention.
Also, update the naming of the #defines used for its fields.
Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 16 ++++++++--------
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 11 ++++++-----
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index 46af726..ad5b820 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -527,7 +527,7 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
{
pr_debug("Enter hdmi_core_powerdown_disable\n");
- REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
+ REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0);
}
static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
@@ -550,12 +550,12 @@ static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
/* sys_ctrl1 default configuration not tunable */
- r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
- r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
- r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
- r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
- r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
- hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
+ r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1);
+ r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
+ r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
+ r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2);
+ r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1);
+ hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r);
REG_FLD_MOD(core_sys_base,
HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
@@ -909,7 +909,7 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
DUMPCORE(HDMI_CORE_SYS_DEV_REV);
DUMPCORE(HDMI_CORE_SYS_SRST);
- DUMPCORE(HDMI_CORE_CTRL1);
+ DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1);
DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
DUMPCORE(HDMI_CORE_SYS_DE_DLY);
DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index d1a2315..149abd8 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -53,7 +53,7 @@
#define HDMI_CORE_SYS_DEV_IDH 0xC
#define HDMI_CORE_SYS_DEV_REV 0x10
#define HDMI_CORE_SYS_SRST 0x14
-#define HDMI_CORE_CTRL1 0x20
+#define HDMI_CORE_SYS_SYS_CTRL1 0x20
#define HDMI_CORE_SYS_SYS_STAT 0x24
#define HDMI_CORE_SYS_DE_DLY 0xC8
#define HDMI_CORE_SYS_DE_CTRL 0xCC
@@ -72,10 +72,11 @@
#define HDMI_CORE_SYS_UMASK1 0x1D4
#define HDMI_CORE_SYS_TMDS_CTRL 0x208
-#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
-#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
-#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1
-#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
+/* value definitions for HDMI_CORE_SYS_SYS_CTRL1 fields */
+#define HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC 0x1
+#define HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC 0x1
+#define HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS 0x1
+#define HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE 0x1
/* HDMI DDC E-DID */
#define HDMI_CORE_DDC_ADDR 0x3B4
--
1.8.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 6/7] OMAPDSS: HDMI: OMAP4: Complete register definitions for core
2013-09-13 10:41 [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions Archit Taneja
` (4 preceding siblings ...)
2013-09-13 10:41 ` [PATCH 5/7] OMAPDSS: HDMI: OMAP4: Rename the HDMI_CORE_CTRL1 register Archit Taneja
@ 2013-09-13 10:41 ` Archit Taneja
2013-09-13 10:41 ` [PATCH 7/7] OMAPDSS: HDMI: OMAP4: Complete dumping of core registers Archit Taneja
2013-09-16 6:11 ` [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions Tomi Valkeinen
7 siblings, 0 replies; 9+ messages in thread
From: Archit Taneja @ 2013-09-13 10:41 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, linux-fbdev, Ricardo Neri, Archit Taneja
From: Ricardo Neri <ricardo.neri@ti.com>
Add missing register definitions; mainly for colorspace conversion, video
timing and interrupt handling.
Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 48 ++++++++++++++++++++++++++++++-
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
index 149abd8..b25269c 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h
@@ -55,6 +55,8 @@
#define HDMI_CORE_SYS_SRST 0x14
#define HDMI_CORE_SYS_SYS_CTRL1 0x20
#define HDMI_CORE_SYS_SYS_STAT 0x24
+#define HDMI_CORE_SYS_SYS_CTRL3 0x28
+#define HDMI_CORE_SYS_DCTL 0x34
#define HDMI_CORE_SYS_DE_DLY 0xC8
#define HDMI_CORE_SYS_DE_CTRL 0xCC
#define HDMI_CORE_SYS_DE_TOP 0xD0
@@ -62,14 +64,58 @@
#define HDMI_CORE_SYS_DE_CNTH 0xDC
#define HDMI_CORE_SYS_DE_LINL 0xE0
#define HDMI_CORE_SYS_DE_LINH_1 0xE4
+#define HDMI_CORE_SYS_HRES_L 0xE8
+#define HDMI_CORE_SYS_HRES_H 0xEC
+#define HDMI_CORE_SYS_VRES_L 0xF0
+#define HDMI_CORE_SYS_VRES_H 0xF4
+#define HDMI_CORE_SYS_IADJUST 0xF8
+#define HDMI_CORE_SYS_POLDETECT 0xFC
+#define HDMI_CORE_SYS_HWIDTH1 0x110
+#define HDMI_CORE_SYS_HWIDTH2 0x114
+#define HDMI_CORE_SYS_VWIDTH 0x11C
+#define HDMI_CORE_SYS_VID_CTRL 0x120
#define HDMI_CORE_SYS_VID_ACEN 0x124
#define HDMI_CORE_SYS_VID_MODE 0x128
+#define HDMI_CORE_SYS_VID_BLANK1 0x12C
+#define HDMI_CORE_SYS_VID_BLANK2 0x130
+#define HDMI_CORE_SYS_VID_BLANK3 0x134
+#define HDMI_CORE_SYS_DC_HEADER 0x138
+#define HDMI_CORE_SYS_VID_DITHER 0x13C
+#define HDMI_CORE_SYS_RGB2XVYCC_CT 0x140
+#define HDMI_CORE_SYS_R2Y_COEFF_LOW 0x144
+#define HDMI_CORE_SYS_R2Y_COEFF_UP 0x148
+#define HDMI_CORE_SYS_G2Y_COEFF_LOW 0x14C
+#define HDMI_CORE_SYS_G2Y_COEFF_UP 0x150
+#define HDMI_CORE_SYS_B2Y_COEFF_LOW 0x154
+#define HDMI_CORE_SYS_B2Y_COEFF_UP 0x158
+#define HDMI_CORE_SYS_R2CB_COEFF_LOW 0x15C
+#define HDMI_CORE_SYS_R2CB_COEFF_UP 0x160
+#define HDMI_CORE_SYS_G2CB_COEFF_LOW 0x164
+#define HDMI_CORE_SYS_G2CB_COEFF_UP 0x168
+#define HDMI_CORE_SYS_B2CB_COEFF_LOW 0x16C
+#define HDMI_CORE_SYS_B2CB_COEFF_UP 0x170
+#define HDMI_CORE_SYS_R2CR_COEFF_LOW 0x174
+#define HDMI_CORE_SYS_R2CR_COEFF_UP 0x178
+#define HDMI_CORE_SYS_G2CR_COEFF_LOW 0x17C
+#define HDMI_CORE_SYS_G2CR_COEFF_UP 0x180
+#define HDMI_CORE_SYS_B2CR_COEFF_LOW 0x184
+#define HDMI_CORE_SYS_B2CR_COEFF_UP 0x188
+#define HDMI_CORE_SYS_RGB_OFFSET_LOW 0x18C
+#define HDMI_CORE_SYS_RGB_OFFSET_UP 0x190
+#define HDMI_CORE_SYS_Y_OFFSET_LOW 0x194
+#define HDMI_CORE_SYS_Y_OFFSET_UP 0x198
+#define HDMI_CORE_SYS_CBCR_OFFSET_LOW 0x19C
+#define HDMI_CORE_SYS_CBCR_OFFSET_UP 0x1A0
#define HDMI_CORE_SYS_INTR_STATE 0x1C0
#define HDMI_CORE_SYS_INTR1 0x1C4
#define HDMI_CORE_SYS_INTR2 0x1C8
#define HDMI_CORE_SYS_INTR3 0x1CC
#define HDMI_CORE_SYS_INTR4 0x1D0
-#define HDMI_CORE_SYS_UMASK1 0x1D4
+#define HDMI_CORE_SYS_INTR_UNMASK1 0x1D4
+#define HDMI_CORE_SYS_INTR_UNMASK2 0x1D8
+#define HDMI_CORE_SYS_INTR_UNMASK3 0x1DC
+#define HDMI_CORE_SYS_INTR_UNMASK4 0x1E0
+#define HDMI_CORE_SYS_INTR_CTRL 0x1E4
#define HDMI_CORE_SYS_TMDS_CTRL 0x208
/* value definitions for HDMI_CORE_SYS_SYS_CTRL1 fields */
--
1.8.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 7/7] OMAPDSS: HDMI: OMAP4: Complete dumping of core registers
2013-09-13 10:41 [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions Archit Taneja
` (5 preceding siblings ...)
2013-09-13 10:41 ` [PATCH 6/7] OMAPDSS: HDMI: OMAP4: Complete register definitions for core Archit Taneja
@ 2013-09-13 10:41 ` Archit Taneja
2013-09-16 6:11 ` [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions Tomi Valkeinen
7 siblings, 0 replies; 9+ messages in thread
From: Archit Taneja @ 2013-09-13 10:41 UTC (permalink / raw)
To: tomi.valkeinen; +Cc: linux-omap, linux-fbdev, Ricardo Neri, Archit Taneja
From: Ricardo Neri <ricardo.neri@ti.com>
Add missing register entries when dumping the core.
Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
---
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 47 ++++++++++++++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index ad5b820..fd4172b 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -911,6 +911,7 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
DUMPCORE(HDMI_CORE_SYS_SRST);
DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1);
DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
+ DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3);
DUMPCORE(HDMI_CORE_SYS_DE_DLY);
DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
DUMPCORE(HDMI_CORE_SYS_DE_TOP);
@@ -918,14 +919,58 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
DUMPCORE(HDMI_CORE_SYS_DE_LINL);
DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
+ DUMPCORE(HDMI_CORE_SYS_HRES_L);
+ DUMPCORE(HDMI_CORE_SYS_HRES_H);
+ DUMPCORE(HDMI_CORE_SYS_VRES_L);
+ DUMPCORE(HDMI_CORE_SYS_VRES_H);
+ DUMPCORE(HDMI_CORE_SYS_IADJUST);
+ DUMPCORE(HDMI_CORE_SYS_POLDETECT);
+ DUMPCORE(HDMI_CORE_SYS_HWIDTH1);
+ DUMPCORE(HDMI_CORE_SYS_HWIDTH2);
+ DUMPCORE(HDMI_CORE_SYS_VWIDTH);
+ DUMPCORE(HDMI_CORE_SYS_VID_CTRL);
DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
DUMPCORE(HDMI_CORE_SYS_VID_MODE);
+ DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
+ DUMPCORE(HDMI_CORE_SYS_VID_BLANK3);
+ DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
+ DUMPCORE(HDMI_CORE_SYS_DC_HEADER);
+ DUMPCORE(HDMI_CORE_SYS_VID_DITHER);
+ DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT);
+ DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW);
+ DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP);
+ DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW);
+ DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP);
+ DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW);
+ DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP);
+ DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW);
+ DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP);
+ DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW);
+ DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP);
+ DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW);
+ DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP);
+ DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW);
+ DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP);
+ DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW);
+ DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP);
+ DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW);
+ DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP);
+ DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW);
+ DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP);
+ DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW);
+ DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP);
+ DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW);
+ DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP);
DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
DUMPCORE(HDMI_CORE_SYS_INTR1);
DUMPCORE(HDMI_CORE_SYS_INTR2);
DUMPCORE(HDMI_CORE_SYS_INTR3);
DUMPCORE(HDMI_CORE_SYS_INTR4);
- DUMPCORE(HDMI_CORE_SYS_UMASK1);
+ DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1);
+ DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2);
+ DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3);
+ DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4);
+ DUMPCORE(HDMI_CORE_SYS_INTR_CTRL);
DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
DUMPCORE(HDMI_CORE_DDC_ADDR);
--
1.8.1.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions
2013-09-13 10:41 [PATCH 0/7] omapdss: HDMI: Fix register definitions and reg dump functions Archit Taneja
` (6 preceding siblings ...)
2013-09-13 10:41 ` [PATCH 7/7] OMAPDSS: HDMI: OMAP4: Complete dumping of core registers Archit Taneja
@ 2013-09-16 6:11 ` Tomi Valkeinen
7 siblings, 0 replies; 9+ messages in thread
From: Tomi Valkeinen @ 2013-09-16 6:11 UTC (permalink / raw)
To: Archit Taneja; +Cc: linux-omap, linux-fbdev
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On 13/09/13 13:29, Archit Taneja wrote:
> These patches complete the OMAP4 HDMI register definitions for HDMI submodules
> and make sure all the corresponding regdump functions dump all the registers.
>
> Ricardo Neri (7):
> OMAPDSS: HDMI: OMAP4: Complete register definitions for wrapper
> OMAPDSS: HDMI: OMAP4: Complete dumping of wrapper registers
> OMAPDSS: HDMI: OMAP4: Complete register definitions for DPLL
> OMAPDSS: HDMI: OMAP4: Complete dumping of DPLL registers
> OMAPDSS: HDMI: OMAP4: Rename the HDMI_CORE_CTRL1 register
> OMAPDSS: HDMI: OMAP4: Complete register definitions for core
> OMAPDSS: HDMI: OMAP4: Complete dumping of core registers
>
> drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 70 ++++++++++++++++++++++++++-----
> drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 65 ++++++++++++++++++++++++----
> 2 files changed, 118 insertions(+), 17 deletions(-)
>
These look fine to me, queuing for 3.13.
Tomi
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^ permalink raw reply [flat|nested] 9+ messages in thread