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From: Philipp Zabel <p.zabel@pengutronix.de>
To: Steve Longerbeam <steve_longerbeam@mentor.com>
Cc: linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org, tomi.valkeinen@ti.com,
	Steve Longerbeam <slongerbeam@gmail.com>,
	plagnioj@jcrosoft.com
Subject: Re: [PATCH v2 11/13] gpu: ipu-ic: Add complete image conversion support with tiling
Date: Mon, 01 Aug 2016 09:29:40 +0000	[thread overview]
Message-ID: <1470043780.3025.31.camel@pengutronix.de> (raw)
In-Reply-To: <8fad20e2-66c4-e2f4-b5d2-25190fdbaa2c@mentor.com>

Am Donnerstag, den 28.07.2016, 16:09 -0700 schrieb Steve Longerbeam:
> > Now split the frame in half and suddenly pixel x' = 640 is the start of
> > a new tile, so it is sampled at x = 160, and pixel x' = 1279 will be
> > sampled at x = 160 + (1279 - 640) * 8192/32846. = 319.37, reading over
> > the edge of the source image.
> 
> Here's where we part.
> 
> The 320x200 --> 1280x800 conversion is split into two 160x200 -->
> 640x800 conversions. The DMA controller and ipu_ic_task_init() are given
> those width/height dimensions, not the dimensions of the original images.
> So this is simply two separate 160x200 --> 640x800 conversions. The only
> difference from a true 160x200 --> 640x800 image conversion is that the DMA
> controller must be given the stride lengths of the original 320x200 and 
> 1280x800
> images.
> 
> The rsc for the 160x200 --> 640x800 conversions is
> 
> x = x' * (160-1)/(640-1) = x' * 8192/rsc, so rsc = 32923
> 
> 
> So original horizontal position 640 is really x' = 0 of the second 
> conversion,
> which is sampled at x = 0 of the second conversion. And the pixel at x' 
> = 1279
> is really x' = 639 of the second conversion, which is sampled at x = 639 
> * 8192/32923
> = 158.98, which does not read over the edge of the source tile.

My bad, I somehow thought that the scaling factor is calculated per
image (as it IMHO should be), not just per tile.

Of course in that case you won't ever read over the edge, but on the
other hand the visual problems are worse because you underestimate the
scaling factor and introduce a sharp edge at the center: even if the
source pixel step per target pixel step is a fraction, between pixels
width/2-1 and width/2 there's always a whole source pixel step.

Take the extreme example of scaling 32x32 to 1080x1080 pixels. The ideal
source pixels for x' = 519 and 520 should be x = 14.911 and 14.939,
respectively. Due to tiling they will be x = 15 and 16, introducing a
sharp seam in the otherwise blurry mess.

> > This problem gets worse if you start using arbitrary frame sizes and YUV
> > planar images and consider that tile start addresses are (currently)
> > limited to 8 byte boundaries, to the point that there are very visible
> > seams in the center of the image, depending on scaling factor and image
> > sizes.
> 
> Indeed there could be other parameters that would cause the resizer to
> read past the edge of the source tiles, I will need to try and find such 
> cases. 
> But not in the above case.

Ok.

> That said, I _have_ noticed seams, but I have always attributed them to the
> fact that we have a discontinuity in color-space conversion and/or resize
> interpolation at the boundary between tiles.
>
> I've also found that the seams are quite noticeable when rendered to a
> display overlay, but become significantly less pronounced if the images are
> converted to a back buffer, and then page-flipped to front buffer when the
> conversion (all tiles) completes.

I don't know what to make of this. Maybe it is a timing issue and what
you are actually seeing is tearing between tiles of different frames?

regards
Philipp


  reply	other threads:[~2016-08-01  9:29 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1467932621-358-1-git-send-email-steve_longerbeam@mentor.com>
2016-07-20  1:10 ` [PATCH v2 00/13] IPUv3 prep for i.MX5/6 v4l2 staging drivers, v2 Steve Longerbeam
2016-07-20  1:10   ` [PATCH v2 01/13] gpu: ipu-v3: Add Video Deinterlacer unit Steve Longerbeam
2016-07-25  6:06     ` kbuild test robot
2016-07-26 10:06     ` Philipp Zabel
2016-07-20  1:11   ` [PATCH v2 02/13] gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset() Steve Longerbeam
2016-07-20  1:11   ` [PATCH v2 03/13] gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize() Steve Longerbeam
2016-07-20  1:11   ` [PATCH v2 04/13] gpu: ipu-v3: Add ipu_get_num() Steve Longerbeam
2016-07-20  1:11   ` [PATCH v2 05/13] gpu: ipu-v3: Add IDMA channel linking support Steve Longerbeam
2016-07-26 10:06     ` Philipp Zabel
2016-07-28 23:40       ` Steve Longerbeam
2016-07-20  1:11   ` [PATCH v2 06/13] gpu: ipu-v3: Add ipu_set_vdi_src_mux() Steve Longerbeam
2016-07-20  1:11   ` [PATCH v2 07/13] gpu: ipu-v3: Add VDI input IDMAC channels Steve Longerbeam
2016-07-20  1:11   ` [PATCH v2 08/13] gpu: ipu-v3: set correct full sensor frame for PAL/NTSC Steve Longerbeam
2016-07-20  1:11   ` [PATCH v2 09/13] gpu: ipu-v3: Fix CSI data format for 16-bit media bus formats Steve Longerbeam
2016-07-20  1:11   ` [PATCH v2 10/13] gpu: ipu-v3: Fix IRT usage Steve Longerbeam
2016-07-20  1:11   ` [PATCH v2 11/13] gpu: ipu-ic: Add complete image conversion support with tiling Steve Longerbeam
2016-07-26 10:08     ` Philipp Zabel
2016-07-28 23:09       ` Steve Longerbeam
2016-08-01  9:29         ` Philipp Zabel [this message]
2016-08-04  0:18           ` Steve Longerbeam
2016-08-12 14:56             ` Philipp Zabel
2016-07-20  1:11   ` [PATCH v2 12/13] gpu: ipu-ic: allow multiple handles to ic Steve Longerbeam
2016-07-20  1:11   ` [PATCH v2 13/13] gpu: ipu-v3: rename CSI client device Steve Longerbeam
2016-07-26 10:06   ` [PATCH v2 00/13] IPUv3 prep for i.MX5/6 v4l2 staging drivers, v2 Philipp Zabel

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