Possible Bug in radeonfb (?)

[Andrea Mazzoleni <amadvance@users.sourceforge.net>]

In radeonfb (2.4.20) I have found a possible inconsistency.

In the PLL clock computation the initial range check compares the
requested clock with the value pll_min/12. But immeditially later
I see that the higher PLL post divider is 16 and not 12.

Is it correct ? Or the check should use 16 instead of 12 ?

This is the code :

	if (freq > rinfo->pll.ppll_max)
		freq = rinfo->pll.ppll_max;
	if (freq*12 < rinfo->pll.ppll_min)
		freq = rinfo->pll.ppll_min / 12;

	{
		struct {
			int divider;
			int bitvalue;
		} *post_div,
		  post_divs[] = {
			{ 1,  0 },
			{ 2,  1 },
			{ 4,  2 },
			{ 8,  3 },
			{ 3,  4 },
			{ 16, 5 },
			{ 6,  6 },
			{ 12, 7 },
			{ 0,  0 },
		};

		for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
			rinfo->pll_output_freq = post_div->divider * freq;
			if (rinfo->pll_output_freq >= rinfo->pll.ppll_min  &&
			    rinfo->pll_output_freq <= rinfo->pll.ppll_max)
				break;
		}


-- 
Andrea Mazzoleni
935A 2D3C 5C70 BCD6 CB0C  ED89 7C19 4321 6340 3F6D




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