Re: radeon, apertures & memory mapping

["Ville Syrjälä" <syrjala@sci.fi>]

On Mon, Mar 14, 2005 at 11:41:23AM +1100, Paul Mackerras wrote:
> Jon Smirl writes:
> 
> > > It works, but it's illegal. That means that the CPU might well speculate
> > > a load from one of these pages in kernel-land just because it happens to
> > > be next to a page where you are iterating an array, and may then bring a
> > > bit in the cache from that page.
> > 
> > That shouldn't matter the page brought in would be for a speculative
> > read and never accessed. It should just fall out of the cache and not
> > be written back. There is only one cachable mapping. In this model
> > writes are always followed by a flush before telling the GPU to access
> > the memory that has just been written.
> 
> That would be fine, but it would mean making sure that every time any
> code in the DRI, DRM or X server writes to the AGP memory, it does the
> flush as well.  Sounds like a maintenance nightmare to me...

It should be the responsibility of the memory manager. If anything wants 
to access the memory it would call lock() and when it's done with the 
memory it calls unlock(). That's exactly how DirectFB's memory manager 
works.

-- 
Ville Syrjälä
syrjala@sci.fi
http://www.sci.fi/~syrjala/