Fw: [Bugme-new] [Bug 7966] New: atyfb (mach64_ct) framebuffer hangs at boot time

[Andrew Morton <akpm@linux-foundation.org>]

Begin forwarded message:

Date: Thu, 8 Feb 2007 06:59:27 -0800
From: bugme-daemon@bugzilla.kernel.org
To: bugme-new@lists.osdl.org
Subject: [Bugme-new] [Bug 7966] New: atyfb (mach64_ct) framebuffer hangs at boot time


http://bugzilla.kernel.org/show_bug.cgi?id=7966

           Summary: atyfb (mach64_ct) framebuffer hangs at boot time
    Kernel Version: 2.6.20 (2.6.19.2)
            Status: NEW
          Severity: normal
             Owner: jsimmons@infradead.org
         Submitter: rootshell@web.de


Distribution: OpenSuse 10.2

Hardware Environment:
 Machine: FujitsuSiemens Primergy TX150
 Board: ServerWorks D1501 
 Chipset: Broadcom CSB6
 Graphic: ati 3d rage xl (mach64 gr) (onBoard) 

Problem Description:
System hangs at boot time, when it tries to switch to frame buffer console. Last
messages are:
atyfb: using auxiliary register aperture
atyfb: 3D RAGE XL (Mach64 GR, PCI-33) [0x4752 rev 0x27]
atyfb: Mach64 BIOS is located at c0000, mapped at c00c0000.
atyfb: BIOS frequency table:
atyfb: PCLK_min_freq 984, PCLK_max_freq 23600, ref_freq 2950, ref_divider 64
atyfb: MCLK_pwd 4200, MCLK_max_freq 8300, XCLK_max_freq 6250, SCLK_freq 0
atyfb: 8M SDRAM (2:1) (32-bit), 29.498928 MHz XTAL, 236 MHz PLL, 83 Mhz MCLK, 62
MHz XCLK
atyfb: atyfb(aty_init_pll_ct): mckl_fb_mult=4, xclk_post_div=1
atyfb: atyfb(aty_init_pll_ct): pllmclk=247 MHz, xclk=61 MHz
atyfb: atyfb(aty_init_pll_ct): use sclk, pllsclk=165 MHz, sclk=mclk=82 MHz

Work around:
After enabling and adding some debugging outputs it suddenly works. After
disabling one to one the debugging printk I found this small patch for me. But I
don't understand why it works.

mach64_ct.c.patch:
--- linux-2.6.20/drivers/video/aty/mach64_ct.c.orig     2007-02-04
19:44:54.000000000 +0100
+++ linux-2.6.20/drivers/video/aty/mach64_ct.c  2007-02-07 14:07:09.000000000 +0100
@@ -29,6 +29,8 @@ u8 aty_ld_pll_ct(int offset, const struc
 
 static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par)
 {
+       printk( " atyfb(%s): \n", __FUNCTION__ );
+
        /* write addr byte */
        aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par);
        /* write the register value */

misc:
Maybe it's at the end the same bug as http://bugme.osdl.org/show_bug.cgi?id=7176

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