* [PATCH 1/2] atyfb: fix CONFIG_ namespace violations
[not found] ` <20090131121008.eb7f5ddd.akpm@linux-foundation.org>
@ 2009-02-02 23:00 ` Randy Dunlap
2009-02-03 8:09 ` [Linux-fbdev-devel] " Geert Uytterhoeven
2009-02-02 23:00 ` [PATCH 2/2] atyfb: fix header file trailing whitespace Randy Dunlap
1 sibling, 1 reply; 6+ messages in thread
From: Randy Dunlap @ 2009-02-02 23:00 UTC (permalink / raw)
To: Andrew Morton, linux-fbdev-devel; +Cc: linux-kernel, Benjamin Herrenschmidt
On Sat, 31 Jan 2009 12:10:08 -0800 Andrew Morton wrote:
> On Sat, 31 Jan 2009 11:53:36 -0800 Randy Dunlap <randy.dunlap@oracle.com> wrote:
>
> > so staging adds a new config symbol that conflicts with the
> > (incorrect namespace) usage in mach64.h.
> >
> > mach64 needs to change IMO, even though it is older.
>
> Sigh, yes, that file has gone on a rampage through the namespace
> rules. I'll take a look at it sometime.
> --
I went ahead with a minimal set of changes, but you can toss them
and do more if you prefer.
---
From: Randy Dunlap <randy.dunlap@oracle.com>
[1/2] Fix namespace violations by changing non-kconfig CONFIG_ names
to CNFG_*.
Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
drivers/video/aty/aty128fb.c | 8 ++++----
drivers/video/aty/atyfb_base.c | 22 +++++++++++-----------
drivers/video/aty/radeon_base.c | 10 +++++-----
drivers/video/aty/radeon_pm.c | 18 +++++++++---------
include/video/aty128.h | 4 ++--
include/video/mach64.h | 24 ++++++++++++------------
include/video/radeon.h | 18 +++++++++---------
7 files changed, 52 insertions(+), 52 deletions(-)
--- linux-2.6.29-rc3-git3.orig/drivers/video/aty/atyfb_base.c
+++ linux-2.6.29-rc3-git3/drivers/video/aty/atyfb_base.c
@@ -135,7 +135,7 @@
#if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
static const u32 lt_lcd_regs[] = {
- CONFIG_PANEL_LG,
+ CNFG_PANEL_LG,
LCD_GEN_CNTL_LG,
DSTN_CONTROL_LG,
HFB_PITCH_ADDR_LG,
@@ -446,7 +446,7 @@ static int __devinit correct_chipset(str
par->pll_limits.ecp_max = aty_chips[i].ecp_max;
par->features = aty_chips[i].features;
- chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
+ chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
type = chip_id & CFG_CHIP_TYPE;
rev = (chip_id & CFG_CHIP_REV) >> 24;
@@ -629,7 +629,7 @@ static void aty_get_crtc(const struct at
crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
}
- crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
+ crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par);
crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
@@ -676,7 +676,7 @@ static void aty_set_crtc(const struct at
aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
/* update non-shadow registers first */
- aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
+ aty_st_lcd(CNFG_PANEL, crtc->lcd_config_panel, par);
aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
@@ -858,7 +858,7 @@ static int aty_var_to_crtc(const struct
if (!M64_HAS(MOBIL_BUS))
crtc->lcd_index |= CRTC2_DISPLAY_DIS;
- crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
+ crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par) | 0x4000;
crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
crtc->lcd_gen_cntl &=
@@ -2254,7 +2254,7 @@ static int __devinit aty_init(struct fb_
if (!M64_HAS(INTEGRATED)) {
u32 stat0;
u8 dac_type, dac_subtype, clk_type;
- stat0 = aty_ld_le32(CONFIG_STAT0, par);
+ stat0 = aty_ld_le32(CNFG_STAT0, par);
par->bus_type = (stat0 >> 0) & 0x07;
par->ram_type = (stat0 >> 3) & 0x07;
ramname = aty_gx_ram[par->ram_type];
@@ -2324,7 +2324,7 @@ static int __devinit aty_init(struct fb_
par->dac_ops = &aty_dac_ct;
par->pll_ops = &aty_pll_ct;
par->bus_type = PCI;
- par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
+ par->ram_type = (aty_ld_le32(CNFG_STAT0, par) & 0x07);
ramname = aty_ct_ram[par->ram_type];
/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
@@ -2433,7 +2433,7 @@ static int __devinit aty_init(struct fb_
}
if (M64_HAS(MAGIC_VRAM_SIZE)) {
- if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
+ if (aty_ld_le32(CNFG_STAT1, par) & 0x40000000)
info->fix.smem_len += 0x400000;
}
@@ -2946,7 +2946,7 @@ static int __devinit atyfb_setup_sparc(s
* Fix PROMs idea of MEM_CNTL settings...
*/
mem = aty_ld_le32(MEM_CNTL, par);
- chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
+ chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
switch (mem & 0x0f) {
case 3:
@@ -2964,7 +2964,7 @@ static int __devinit atyfb_setup_sparc(s
default:
break;
}
- if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
+ if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)
mem &= ~(0x00700000);
}
mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
@@ -3572,7 +3572,7 @@ static int __init atyfb_atari_probe(void
}
/* Fake pci_id for correct_chipset() */
- switch (aty_ld_le32(CONFIG_CHIP_ID, par) & CFG_CHIP_TYPE) {
+ switch (aty_ld_le32(CNFG_CHIP_ID, par) & CFG_CHIP_TYPE) {
case 0x00d7:
par->pci_id = PCI_CHIP_MACH64GX;
break;
--- linux-2.6.29-rc3-git3.orig/include/video/mach64.h
+++ linux-2.6.29-rc3-git3/include/video/mach64.h
@@ -103,7 +103,7 @@
#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
#define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
-#define CONFIG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */
+#define CNFG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */
/* General I/O Control */
#define GP_IO 0x0078 /* Dword offset 0_1E */
@@ -146,8 +146,8 @@
#define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */
/* Configuration */
-#define CONFIG_STAT1 0x0094 /* Dword offset 0_25 */
-#define CONFIG_STAT2 0x0098 /* Dword offset 0_26 */
+#define CNFG_STAT1 0x0094 /* Dword offset 0_25 */
+#define CNFG_STAT2 0x0098 /* Dword offset 0_26 */
/* Bus Control */
#define BUS_CNTL 0x00A0 /* Dword offset 0_28 */
@@ -190,9 +190,9 @@
#define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */
/* Configuration */
-#define CONFIG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
-#define CONFIG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
-#define CONFIG_STAT0 0x00E4 /* Dword offset 0_39 */
+#define CNFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
+#define CNFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
+#define CNFG_STAT0 0x00E4 /* Dword offset 0_39 */
/* Test and Debug */
#define CRC_SIG 0x00E8 /* Dword offset 0_3A */
@@ -851,17 +851,17 @@
#define PLL_YCLK_CNTL 0x29
#define PM_DYN_CLK_CNTL 0x2A
-/* CONFIG_CNTL register constants */
+/* CNFG_CNTL register constants */
#define APERTURE_4M_ENABLE 1
#define APERTURE_8M_ENABLE 2
#define VGA_APERTURE_ENABLE 4
-/* CONFIG_STAT0 register constants (GX, CX) */
+/* CNFG_STAT0 register constants (GX, CX) */
#define CFG_BUS_TYPE 0x00000007
#define CFG_MEM_TYPE 0x00000038
#define CFG_INIT_DAC_TYPE 0x00000e00
-/* CONFIG_STAT0 register constants (CT, ET, VT) */
+/* CNFG_STAT0 register constants (CT, ET, VT) */
#define CFG_MEM_TYPE_xT 0x00000007
#define ISA 0
@@ -942,7 +942,7 @@
#define PCI_ATI_VENDOR_ID 0x1002
-/* CONFIG_CHIP_ID register constants */
+/* CNFG_CHIP_ID register constants */
#define CFG_CHIP_TYPE 0x0000FFFF
#define CFG_CHIP_CLASS 0x00FF0000
#define CFG_CHIP_REV 0xFF000000
@@ -951,7 +951,7 @@
#define CFG_CHIP_MINOR 0xC0000000
-/* Chip IDs read from CONFIG_CHIP_ID */
+/* Chip IDs read from CNFG_CHIP_ID */
/* mach64GX family */
#define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */
@@ -1254,7 +1254,7 @@
#define CRTC2_DISPLAY_DIS 0x00000400
/* LCD register indices */
-#define CONFIG_PANEL 0x00
+#define CNFG_PANEL 0x00
#define LCD_GEN_CNTL 0x01
#define DSTN_CONTROL 0x02
#define HFB_PITCH_ADDR 0x03
--- linux-2.6.29-rc3-git3.orig/drivers/video/aty/aty128fb.c
+++ linux-2.6.29-rc3-git3/drivers/video/aty/aty128fb.c
@@ -1475,7 +1475,7 @@ static int aty128fb_set_par(struct fb_in
aty128_set_pll(&par->pll, par);
aty128_set_fifo(&par->fifo_reg, par);
- config = aty_ld_le32(CONFIG_CNTL) & ~3;
+ config = aty_ld_le32(CNFG_CNTL) & ~3;
#if defined(__BIG_ENDIAN)
if (par->crtc.bpp == 32)
@@ -1484,7 +1484,7 @@ static int aty128fb_set_par(struct fb_in
config |= 1; /* make aperture do 16 bit swapping */
#endif
- aty_st_le32(CONFIG_CNTL, config);
+ aty_st_le32(CNFG_CNTL, config);
aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
@@ -1875,7 +1875,7 @@ static int __devinit aty128_init(struct
u32 dac;
/* Get the chip revision */
- chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
+ chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
strcpy(video_card, "Rage128 XX ");
video_card[8] = ent->device >> 8;
@@ -2057,7 +2057,7 @@ static int __devinit aty128_probe(struct
/* Grab memory size from the card */
// How does this relate to the resource length from the PCI hardware?
- par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
+ par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
/* Virtualize the framebuffer */
info->screen_base = ioremap(fb_addr, par->vram_size);
--- linux-2.6.29-rc3-git3.orig/include/video/aty128.h
+++ linux-2.6.29-rc3-git3/include/video/aty128.h
@@ -21,9 +21,9 @@
#define I2C_CNTL_1 0x0094
#define PALETTE_INDEX 0x00b0
#define PALETTE_DATA 0x00b4
-#define CONFIG_CNTL 0x00e0
+#define CNFG_CNTL 0x00e0
#define GEN_RESET_CNTL 0x00f0
-#define CONFIG_MEMSIZE 0x00f8
+#define CNFG_MEMSIZE 0x00f8
#define MEM_CNTL 0x0140
#define MEM_POWER_MISC 0x015c
#define AGP_BASE 0x0170
--- linux-2.6.29-rc3-git3.orig/drivers/video/aty/radeon_base.c
+++ linux-2.6.29-rc3-git3/drivers/video/aty/radeon_base.c
@@ -1936,8 +1936,8 @@ static void fixup_memory_mappings(struct
OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
mdelay(100);
- aper_base = INREG(CONFIG_APER_0_BASE);
- aper_size = INREG(CONFIG_APER_SIZE);
+ aper_base = INREG(CNFG_APER_0_BASE);
+ aper_size = INREG(CNFG_APER_SIZE);
#ifdef SET_MC_FB_FROM_APERTURE
/* Set framebuffer to be at the same address as set in PCI BAR */
@@ -2024,11 +2024,11 @@ static void radeon_identify_vram(struct
~CRTC_H_CUTOFF_ACTIVE_EN);
}
} else {
- tmp = INREG(CONFIG_MEMSIZE);
+ tmp = INREG(CNFG_MEMSIZE);
}
/* mem size is bits [28:0], mask off the rest */
- rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
+ rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
/*
* Hack to get around some busted production M6's
@@ -2228,7 +2228,7 @@ static int __devinit radeonfb_pci_regist
*/
rinfo->errata = 0;
if (rinfo->family == CHIP_FAMILY_R300 &&
- (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
+ (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK)
== CFG_ATI_REV_A11)
rinfo->errata |= CHIP_ERRATA_R300_CG;
--- linux-2.6.29-rc3-git3.orig/drivers/video/aty/radeon_pm.c
+++ linux-2.6.29-rc3-git3/drivers/video/aty/radeon_pm.c
@@ -333,7 +333,7 @@ static void radeon_pm_enable_dynamic_mod
if (!rinfo->has_CRTC2) {
tmp = INPLL(pllSCLK_CNTL);
- if ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
+ if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB);
tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_SE |
@@ -468,9 +468,9 @@ static void radeon_pm_enable_dynamic_mod
/*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
if ((rinfo->family == CHIP_FAMILY_RV250 &&
- ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
+ ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
((rinfo->family == CHIP_FAMILY_RV100) &&
- ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
+ ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
tmp |= SCLK_CNTL__FORCE_CP;
tmp |= SCLK_CNTL__FORCE_VIP;
}
@@ -486,7 +486,7 @@ static void radeon_pm_enable_dynamic_mod
/* RV200::A11 A12 RV250::A11 A12 */
if (((rinfo->family == CHIP_FAMILY_RV200) ||
(rinfo->family == CHIP_FAMILY_RV250)) &&
- ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
+ ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
tmp |= SCLK_MORE_CNTL__FORCEON;
OUTPLL(pllSCLK_MORE_CNTL, tmp);
@@ -497,7 +497,7 @@ static void radeon_pm_enable_dynamic_mod
/* RV200::A11 A12, RV250::A11 A12 */
if (((rinfo->family == CHIP_FAMILY_RV200) ||
(rinfo->family == CHIP_FAMILY_RV250)) &&
- ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
+ ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
tmp = INPLL(pllPLL_PWRMGT_CNTL);
tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
@@ -702,7 +702,7 @@ static void radeon_pm_restore_regs(struc
OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
- OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
+ OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
@@ -1723,7 +1723,7 @@ static void radeon_reinitialize_M10(stru
OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
- OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
+ OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
OUTREG(BUS_CNTL, rinfo->save_regs[36]);
OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
@@ -1961,7 +1961,7 @@ static void radeon_pm_m9p_reconfigure_mc
OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
OUTREG(MC_IND_INDEX, 0);
- OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
+ OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
mdelay(20);
}
@@ -2361,7 +2361,7 @@ static void radeon_reinitialize_QW(struc
OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
OUTREG(MC_IND_INDEX, 0);
- OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
+ OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
radeon_pm_full_reset_sdram(rinfo);
--- linux-2.6.29-rc3-git3.orig/include/video/radeon.h
+++ linux-2.6.29-rc3-git3/include/video/radeon.h
@@ -11,13 +11,13 @@
#define HI_STAT 0x004C
#define BUS_CNTL1 0x0034
#define I2C_CNTL_1 0x0094
-#define CONFIG_CNTL 0x00E0
-#define CONFIG_MEMSIZE 0x00F8
-#define CONFIG_APER_0_BASE 0x0100
-#define CONFIG_APER_1_BASE 0x0104
-#define CONFIG_APER_SIZE 0x0108
-#define CONFIG_REG_1_BASE 0x010C
-#define CONFIG_REG_APER_SIZE 0x0110
+#define CNFG_CNTL 0x00E0
+#define CNFG_MEMSIZE 0x00F8
+#define CNFG_APER_0_BASE 0x0100
+#define CNFG_APER_1_BASE 0x0104
+#define CNFG_APER_SIZE 0x0108
+#define CNFG_REG_1_BASE 0x010C
+#define CNFG_REG_APER_SIZE 0x0110
#define PAD_AGPINPUT_DELAY 0x0164
#define PAD_CTLR_STRENGTH 0x0168
#define PAD_CTLR_UPDATE 0x016C
@@ -509,7 +509,7 @@
/* CLOCK_CNTL_INDEX bit constants */
#define PLL_WR_EN 0x00000080
-/* CONFIG_CNTL bit constants */
+/* CNFG_CNTL bit constants */
#define CFG_VGA_RAM_EN 0x00000100
#define CFG_ATI_REV_ID_MASK (0xf << 16)
#define CFG_ATI_REV_A11 (0 << 16)
@@ -980,7 +980,7 @@
/* masks */
-#define CONFIG_MEMSIZE_MASK 0x1f000000
+#define CNFG_MEMSIZE_MASK 0x1f000000
#define MEM_CFG_TYPE 0x40000000
#define DST_OFFSET_MASK 0x003fffff
#define DST_PITCH_MASK 0x3fc00000
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] atyfb: fix header file trailing whitespace
[not found] ` <20090131121008.eb7f5ddd.akpm@linux-foundation.org>
2009-02-02 23:00 ` [PATCH 1/2] atyfb: fix CONFIG_ namespace violations Randy Dunlap
@ 2009-02-02 23:00 ` Randy Dunlap
1 sibling, 0 replies; 6+ messages in thread
From: Randy Dunlap @ 2009-02-02 23:00 UTC (permalink / raw)
To: Andrew Morton, linux-fbdev-devel; +Cc: linux-kernel, Benjamin Herrenschmidt
From: Randy Dunlap <randy.dunlap@oracle.com>
[2/2] Fix trailing whitespace because quilt complained about it.
Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
include/video/aty128.h | 2
include/video/radeon.h | 578 ++++++++++++++++++++++++-------------------------
2 files changed, 290 insertions(+), 290 deletions(-)
--- linux-2.6.29-rc3-git3.orig/include/video/aty128.h
+++ linux-2.6.29-rc3-git3/include/video/aty128.h
@@ -415,7 +415,7 @@
#define PWR_MGT_SLOWDOWN_MCLK 0x00002000
#define PMI_PMSCR_REG 0x60
-
+
/* used by ATI bug fix for hardware ROM */
#define RAGE128_MPP_TB_CONFIG 0x01c0
--- linux-2.6.29-rc3-git3.orig/include/video/radeon.h
+++ linux-2.6.29-rc3-git3/include/video/radeon.h
@@ -5,21 +5,21 @@
#define RADEON_REGSIZE 0x4000
-#define MM_INDEX 0x0000
-#define MM_DATA 0x0004
-#define BUS_CNTL 0x0030
-#define HI_STAT 0x004C
+#define MM_INDEX 0x0000
+#define MM_DATA 0x0004
+#define BUS_CNTL 0x0030
+#define HI_STAT 0x004C
#define BUS_CNTL1 0x0034
-#define I2C_CNTL_1 0x0094
-#define CNFG_CNTL 0x00E0
-#define CNFG_MEMSIZE 0x00F8
-#define CNFG_APER_0_BASE 0x0100
-#define CNFG_APER_1_BASE 0x0104
-#define CNFG_APER_SIZE 0x0108
-#define CNFG_REG_1_BASE 0x010C
-#define CNFG_REG_APER_SIZE 0x0110
-#define PAD_AGPINPUT_DELAY 0x0164
-#define PAD_CTLR_STRENGTH 0x0168
+#define I2C_CNTL_1 0x0094
+#define CNFG_CNTL 0x00E0
+#define CNFG_MEMSIZE 0x00F8
+#define CNFG_APER_0_BASE 0x0100
+#define CNFG_APER_1_BASE 0x0104
+#define CNFG_APER_SIZE 0x0108
+#define CNFG_REG_1_BASE 0x010C
+#define CNFG_REG_APER_SIZE 0x0110
+#define PAD_AGPINPUT_DELAY 0x0164
+#define PAD_CTLR_STRENGTH 0x0168
#define PAD_CTLR_UPDATE 0x016C
#define PAD_CTLR_MISC 0x0aa0
#define AGP_CNTL 0x0174
@@ -27,171 +27,171 @@
#define CAP0_TRIG_CNTL 0x0950
#define CAP1_TRIG_CNTL 0x09c0
#define VIPH_CONTROL 0x0C40
-#define VENDOR_ID 0x0F00
-#define DEVICE_ID 0x0F02
-#define COMMAND 0x0F04
-#define STATUS 0x0F06
-#define REVISION_ID 0x0F08
-#define REGPROG_INF 0x0F09
-#define SUB_CLASS 0x0F0A
-#define BASE_CODE 0x0F0B
-#define CACHE_LINE 0x0F0C
-#define LATENCY 0x0F0D
-#define HEADER 0x0F0E
-#define BIST 0x0F0F
-#define REG_MEM_BASE 0x0F10
-#define REG_IO_BASE 0x0F14
+#define VENDOR_ID 0x0F00
+#define DEVICE_ID 0x0F02
+#define COMMAND 0x0F04
+#define STATUS 0x0F06
+#define REVISION_ID 0x0F08
+#define REGPROG_INF 0x0F09
+#define SUB_CLASS 0x0F0A
+#define BASE_CODE 0x0F0B
+#define CACHE_LINE 0x0F0C
+#define LATENCY 0x0F0D
+#define HEADER 0x0F0E
+#define BIST 0x0F0F
+#define REG_MEM_BASE 0x0F10
+#define REG_IO_BASE 0x0F14
#define REG_REG_BASE 0x0F18
#define ADAPTER_ID 0x0F2C
#define BIOS_ROM 0x0F30
-#define CAPABILITIES_PTR 0x0F34
-#define INTERRUPT_LINE 0x0F3C
-#define INTERRUPT_PIN 0x0F3D
-#define MIN_GRANT 0x0F3E
-#define MAX_LATENCY 0x0F3F
-#define ADAPTER_ID_W 0x0F4C
-#define PMI_CAP_ID 0x0F50
-#define PMI_NXT_CAP_PTR 0x0F51
-#define PMI_PMC_REG 0x0F52
-#define PM_STATUS 0x0F54
-#define PMI_DATA 0x0F57
-#define AGP_CAP_ID 0x0F58
-#define AGP_STATUS 0x0F5C
-#define AGP_COMMAND 0x0F60
+#define CAPABILITIES_PTR 0x0F34
+#define INTERRUPT_LINE 0x0F3C
+#define INTERRUPT_PIN 0x0F3D
+#define MIN_GRANT 0x0F3E
+#define MAX_LATENCY 0x0F3F
+#define ADAPTER_ID_W 0x0F4C
+#define PMI_CAP_ID 0x0F50
+#define PMI_NXT_CAP_PTR 0x0F51
+#define PMI_PMC_REG 0x0F52
+#define PM_STATUS 0x0F54
+#define PMI_DATA 0x0F57
+#define AGP_CAP_ID 0x0F58
+#define AGP_STATUS 0x0F5C
+#define AGP_COMMAND 0x0F60
#define AIC_CTRL 0x01D0
#define AIC_STAT 0x01D4
#define AIC_PT_BASE 0x01D8
-#define AIC_LO_ADDR 0x01DC
-#define AIC_HI_ADDR 0x01E0
-#define AIC_TLB_ADDR 0x01E4
-#define AIC_TLB_DATA 0x01E8
-#define DAC_CNTL 0x0058
+#define AIC_LO_ADDR 0x01DC
+#define AIC_HI_ADDR 0x01E0
+#define AIC_TLB_ADDR 0x01E4
+#define AIC_TLB_DATA 0x01E8
+#define DAC_CNTL 0x0058
#define DAC_CNTL2 0x007c
-#define CRTC_GEN_CNTL 0x0050
-#define MEM_CNTL 0x0140
+#define CRTC_GEN_CNTL 0x0050
+#define MEM_CNTL 0x0140
#define MC_CNTL 0x0140
-#define EXT_MEM_CNTL 0x0144
+#define EXT_MEM_CNTL 0x0144
#define MC_TIMING_CNTL 0x0144
-#define MC_AGP_LOCATION 0x014C
-#define MEM_IO_CNTL_A0 0x0178
+#define MC_AGP_LOCATION 0x014C
+#define MEM_IO_CNTL_A0 0x0178
#define MEM_REFRESH_CNTL 0x0178
-#define MEM_INIT_LATENCY_TIMER 0x0154
+#define MEM_INIT_LATENCY_TIMER 0x0154
#define MC_INIT_GFX_LAT_TIMER 0x0154
-#define MEM_SDRAM_MODE_REG 0x0158
-#define AGP_BASE 0x0170
-#define MEM_IO_CNTL_A1 0x017C
+#define MEM_SDRAM_MODE_REG 0x0158
+#define AGP_BASE 0x0170
+#define MEM_IO_CNTL_A1 0x017C
#define MC_READ_CNTL_AB 0x017C
#define MEM_IO_CNTL_B0 0x0180
#define MC_INIT_MISC_LAT_TIMER 0x0180
#define MEM_IO_CNTL_B1 0x0184
#define MC_IOPAD_CNTL 0x0184
#define MC_DEBUG 0x0188
-#define MC_STATUS 0x0150
-#define MEM_IO_OE_CNTL 0x018C
+#define MC_STATUS 0x0150
+#define MEM_IO_OE_CNTL 0x018C
#define MC_CHIP_IO_OE_CNTL_AB 0x018C
-#define MC_FB_LOCATION 0x0148
-#define HOST_PATH_CNTL 0x0130
-#define MEM_VGA_WP_SEL 0x0038
-#define MEM_VGA_RP_SEL 0x003C
-#define HDP_DEBUG 0x0138
+#define MC_FB_LOCATION 0x0148
+#define HOST_PATH_CNTL 0x0130
+#define MEM_VGA_WP_SEL 0x0038
+#define MEM_VGA_RP_SEL 0x003C
+#define HDP_DEBUG 0x0138
#define SW_SEMAPHORE 0x013C
-#define CRTC2_GEN_CNTL 0x03f8
+#define CRTC2_GEN_CNTL 0x03f8
#define CRTC2_DISPLAY_BASE_ADDR 0x033c
-#define SURFACE_CNTL 0x0B00
-#define SURFACE0_LOWER_BOUND 0x0B04
-#define SURFACE1_LOWER_BOUND 0x0B14
-#define SURFACE2_LOWER_BOUND 0x0B24
-#define SURFACE3_LOWER_BOUND 0x0B34
-#define SURFACE4_LOWER_BOUND 0x0B44
+#define SURFACE_CNTL 0x0B00
+#define SURFACE0_LOWER_BOUND 0x0B04
+#define SURFACE1_LOWER_BOUND 0x0B14
+#define SURFACE2_LOWER_BOUND 0x0B24
+#define SURFACE3_LOWER_BOUND 0x0B34
+#define SURFACE4_LOWER_BOUND 0x0B44
#define SURFACE5_LOWER_BOUND 0x0B54
#define SURFACE6_LOWER_BOUND 0x0B64
#define SURFACE7_LOWER_BOUND 0x0B74
-#define SURFACE0_UPPER_BOUND 0x0B08
-#define SURFACE1_UPPER_BOUND 0x0B18
-#define SURFACE2_UPPER_BOUND 0x0B28
-#define SURFACE3_UPPER_BOUND 0x0B38
-#define SURFACE4_UPPER_BOUND 0x0B48
-#define SURFACE5_UPPER_BOUND 0x0B58
-#define SURFACE6_UPPER_BOUND 0x0B68
-#define SURFACE7_UPPER_BOUND 0x0B78
-#define SURFACE0_INFO 0x0B0C
-#define SURFACE1_INFO 0x0B1C
-#define SURFACE2_INFO 0x0B2C
-#define SURFACE3_INFO 0x0B3C
-#define SURFACE4_INFO 0x0B4C
-#define SURFACE5_INFO 0x0B5C
+#define SURFACE0_UPPER_BOUND 0x0B08
+#define SURFACE1_UPPER_BOUND 0x0B18
+#define SURFACE2_UPPER_BOUND 0x0B28
+#define SURFACE3_UPPER_BOUND 0x0B38
+#define SURFACE4_UPPER_BOUND 0x0B48
+#define SURFACE5_UPPER_BOUND 0x0B58
+#define SURFACE6_UPPER_BOUND 0x0B68
+#define SURFACE7_UPPER_BOUND 0x0B78
+#define SURFACE0_INFO 0x0B0C
+#define SURFACE1_INFO 0x0B1C
+#define SURFACE2_INFO 0x0B2C
+#define SURFACE3_INFO 0x0B3C
+#define SURFACE4_INFO 0x0B4C
+#define SURFACE5_INFO 0x0B5C
#define SURFACE6_INFO 0x0B6C
#define SURFACE7_INFO 0x0B7C
#define SURFACE_ACCESS_FLAGS 0x0BF8
-#define SURFACE_ACCESS_CLR 0x0BFC
-#define GEN_INT_CNTL 0x0040
-#define GEN_INT_STATUS 0x0044
+#define SURFACE_ACCESS_CLR 0x0BFC
+#define GEN_INT_CNTL 0x0040
+#define GEN_INT_STATUS 0x0044
#define CRTC_EXT_CNTL 0x0054
-#define RB3D_CNTL 0x1C3C
-#define WAIT_UNTIL 0x1720
-#define ISYNC_CNTL 0x1724
-#define RBBM_GUICNTL 0x172C
-#define RBBM_STATUS 0x0E40
-#define RBBM_STATUS_alt_1 0x1740
-#define RBBM_CNTL 0x00EC
-#define RBBM_CNTL_alt_1 0x0E44
-#define RBBM_SOFT_RESET 0x00F0
-#define RBBM_SOFT_RESET_alt_1 0x0E48
-#define NQWAIT_UNTIL 0x0E50
+#define RB3D_CNTL 0x1C3C
+#define WAIT_UNTIL 0x1720
+#define ISYNC_CNTL 0x1724
+#define RBBM_GUICNTL 0x172C
+#define RBBM_STATUS 0x0E40
+#define RBBM_STATUS_alt_1 0x1740
+#define RBBM_CNTL 0x00EC
+#define RBBM_CNTL_alt_1 0x0E44
+#define RBBM_SOFT_RESET 0x00F0
+#define RBBM_SOFT_RESET_alt_1 0x0E48
+#define NQWAIT_UNTIL 0x0E50
#define RBBM_DEBUG 0x0E6C
#define RBBM_CMDFIFO_ADDR 0x0E70
#define RBBM_CMDFIFO_DATAL 0x0E74
-#define RBBM_CMDFIFO_DATAH 0x0E78
-#define RBBM_CMDFIFO_STAT 0x0E7C
-#define CRTC_STATUS 0x005C
-#define GPIO_VGA_DDC 0x0060
-#define GPIO_DVI_DDC 0x0064
-#define GPIO_MONID 0x0068
+#define RBBM_CMDFIFO_DATAH 0x0E78
+#define RBBM_CMDFIFO_STAT 0x0E7C
+#define CRTC_STATUS 0x005C
+#define GPIO_VGA_DDC 0x0060
+#define GPIO_DVI_DDC 0x0064
+#define GPIO_MONID 0x0068
#define GPIO_CRT2_DDC 0x006c
-#define PALETTE_INDEX 0x00B0
-#define PALETTE_DATA 0x00B4
-#define PALETTE_30_DATA 0x00B8
-#define CRTC_H_TOTAL_DISP 0x0200
-#define CRTC_H_SYNC_STRT_WID 0x0204
-#define CRTC_V_TOTAL_DISP 0x0208
-#define CRTC_V_SYNC_STRT_WID 0x020C
-#define CRTC_VLINE_CRNT_VLINE 0x0210
+#define PALETTE_INDEX 0x00B0
+#define PALETTE_DATA 0x00B4
+#define PALETTE_30_DATA 0x00B8
+#define CRTC_H_TOTAL_DISP 0x0200
+#define CRTC_H_SYNC_STRT_WID 0x0204
+#define CRTC_V_TOTAL_DISP 0x0208
+#define CRTC_V_SYNC_STRT_WID 0x020C
+#define CRTC_VLINE_CRNT_VLINE 0x0210
#define CRTC_CRNT_FRAME 0x0214
#define CRTC_GUI_TRIG_VLINE 0x0218
#define CRTC_DEBUG 0x021C
-#define CRTC_OFFSET_RIGHT 0x0220
-#define CRTC_OFFSET 0x0224
-#define CRTC_OFFSET_CNTL 0x0228
-#define CRTC_PITCH 0x022C
-#define OVR_CLR 0x0230
-#define OVR_WID_LEFT_RIGHT 0x0234
-#define OVR_WID_TOP_BOTTOM 0x0238
-#define DISPLAY_BASE_ADDR 0x023C
-#define SNAPSHOT_VH_COUNTS 0x0240
-#define SNAPSHOT_F_COUNT 0x0244
-#define N_VIF_COUNT 0x0248
-#define SNAPSHOT_VIF_COUNT 0x024C
-#define FP_CRTC_H_TOTAL_DISP 0x0250
-#define FP_CRTC_V_TOTAL_DISP 0x0254
+#define CRTC_OFFSET_RIGHT 0x0220
+#define CRTC_OFFSET 0x0224
+#define CRTC_OFFSET_CNTL 0x0228
+#define CRTC_PITCH 0x022C
+#define OVR_CLR 0x0230
+#define OVR_WID_LEFT_RIGHT 0x0234
+#define OVR_WID_TOP_BOTTOM 0x0238
+#define DISPLAY_BASE_ADDR 0x023C
+#define SNAPSHOT_VH_COUNTS 0x0240
+#define SNAPSHOT_F_COUNT 0x0244
+#define N_VIF_COUNT 0x0248
+#define SNAPSHOT_VIF_COUNT 0x024C
+#define FP_CRTC_H_TOTAL_DISP 0x0250
+#define FP_CRTC_V_TOTAL_DISP 0x0254
#define CRT_CRTC_H_SYNC_STRT_WID 0x0258
#define CRT_CRTC_V_SYNC_STRT_WID 0x025C
#define CUR_OFFSET 0x0260
-#define CUR_HORZ_VERT_POSN 0x0264
-#define CUR_HORZ_VERT_OFF 0x0268
-#define CUR_CLR0 0x026C
-#define CUR_CLR1 0x0270
-#define FP_HORZ_VERT_ACTIVE 0x0278
-#define CRTC_MORE_CNTL 0x027C
+#define CUR_HORZ_VERT_POSN 0x0264
+#define CUR_HORZ_VERT_OFF 0x0268
+#define CUR_CLR0 0x026C
+#define CUR_CLR1 0x0270
+#define FP_HORZ_VERT_ACTIVE 0x0278
+#define CRTC_MORE_CNTL 0x027C
#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
-#define DAC_EXT_CNTL 0x0280
-#define FP_GEN_CNTL 0x0284
-#define FP_HORZ_STRETCH 0x028C
-#define FP_VERT_STRETCH 0x0290
-#define FP_H_SYNC_STRT_WID 0x02C4
-#define FP_V_SYNC_STRT_WID 0x02C8
-#define AUX_WINDOW_HORZ_CNTL 0x02D8
-#define AUX_WINDOW_VERT_CNTL 0x02DC
+#define DAC_EXT_CNTL 0x0280
+#define FP_GEN_CNTL 0x0284
+#define FP_HORZ_STRETCH 0x028C
+#define FP_VERT_STRETCH 0x0290
+#define FP_H_SYNC_STRT_WID 0x02C4
+#define FP_V_SYNC_STRT_WID 0x02C8
+#define AUX_WINDOW_HORZ_CNTL 0x02D8
+#define AUX_WINDOW_VERT_CNTL 0x02DC
//#define DDA_CONFIG 0x02e0
//#define DDA_ON_OFF 0x02e4
#define DVI_I2C_CNTL_1 0x02e4
@@ -199,192 +199,192 @@
#define GRPH2_BUFFER_CNTL 0x03F0
#define VGA_BUFFER_CNTL 0x02F4
#define OV0_Y_X_START 0x0400
-#define OV0_Y_X_END 0x0404
-#define OV0_PIPELINE_CNTL 0x0408
-#define OV0_REG_LOAD_CNTL 0x0410
-#define OV0_SCALE_CNTL 0x0420
-#define OV0_V_INC 0x0424
-#define OV0_P1_V_ACCUM_INIT 0x0428
-#define OV0_P23_V_ACCUM_INIT 0x042C
-#define OV0_P1_BLANK_LINES_AT_TOP 0x0430
-#define OV0_P23_BLANK_LINES_AT_TOP 0x0434
-#define OV0_BASE_ADDR 0x043C
-#define OV0_VID_BUF0_BASE_ADRS 0x0440
-#define OV0_VID_BUF1_BASE_ADRS 0x0444
-#define OV0_VID_BUF2_BASE_ADRS 0x0448
-#define OV0_VID_BUF3_BASE_ADRS 0x044C
+#define OV0_Y_X_END 0x0404
+#define OV0_PIPELINE_CNTL 0x0408
+#define OV0_REG_LOAD_CNTL 0x0410
+#define OV0_SCALE_CNTL 0x0420
+#define OV0_V_INC 0x0424
+#define OV0_P1_V_ACCUM_INIT 0x0428
+#define OV0_P23_V_ACCUM_INIT 0x042C
+#define OV0_P1_BLANK_LINES_AT_TOP 0x0430
+#define OV0_P23_BLANK_LINES_AT_TOP 0x0434
+#define OV0_BASE_ADDR 0x043C
+#define OV0_VID_BUF0_BASE_ADRS 0x0440
+#define OV0_VID_BUF1_BASE_ADRS 0x0444
+#define OV0_VID_BUF2_BASE_ADRS 0x0448
+#define OV0_VID_BUF3_BASE_ADRS 0x044C
#define OV0_VID_BUF4_BASE_ADRS 0x0450
#define OV0_VID_BUF5_BASE_ADRS 0x0454
#define OV0_VID_BUF_PITCH0_VALUE 0x0460
-#define OV0_VID_BUF_PITCH1_VALUE 0x0464
-#define OV0_AUTO_FLIP_CNTRL 0x0470
-#define OV0_DEINTERLACE_PATTERN 0x0474
-#define OV0_SUBMIT_HISTORY 0x0478
-#define OV0_H_INC 0x0480
-#define OV0_STEP_BY 0x0484
-#define OV0_P1_H_ACCUM_INIT 0x0488
-#define OV0_P23_H_ACCUM_INIT 0x048C
-#define OV0_P1_X_START_END 0x0494
-#define OV0_P2_X_START_END 0x0498
-#define OV0_P3_X_START_END 0x049C
-#define OV0_FILTER_CNTL 0x04A0
-#define OV0_FOUR_TAP_COEF_0 0x04B0
-#define OV0_FOUR_TAP_COEF_1 0x04B4
+#define OV0_VID_BUF_PITCH1_VALUE 0x0464
+#define OV0_AUTO_FLIP_CNTRL 0x0470
+#define OV0_DEINTERLACE_PATTERN 0x0474
+#define OV0_SUBMIT_HISTORY 0x0478
+#define OV0_H_INC 0x0480
+#define OV0_STEP_BY 0x0484
+#define OV0_P1_H_ACCUM_INIT 0x0488
+#define OV0_P23_H_ACCUM_INIT 0x048C
+#define OV0_P1_X_START_END 0x0494
+#define OV0_P2_X_START_END 0x0498
+#define OV0_P3_X_START_END 0x049C
+#define OV0_FILTER_CNTL 0x04A0
+#define OV0_FOUR_TAP_COEF_0 0x04B0
+#define OV0_FOUR_TAP_COEF_1 0x04B4
#define OV0_FOUR_TAP_COEF_2 0x04B8
#define OV0_FOUR_TAP_COEF_3 0x04BC
#define OV0_FOUR_TAP_COEF_4 0x04C0
-#define OV0_FLAG_CNTRL 0x04DC
-#define OV0_SLICE_CNTL 0x04E0
-#define OV0_VID_KEY_CLR_LOW 0x04E4
-#define OV0_VID_KEY_CLR_HIGH 0x04E8
-#define OV0_GRPH_KEY_CLR_LOW 0x04EC
-#define OV0_GRPH_KEY_CLR_HIGH 0x04F0
-#define OV0_KEY_CNTL 0x04F4
-#define OV0_TEST 0x04F8
-#define SUBPIC_CNTL 0x0540
-#define SUBPIC_DEFCOLCON 0x0544
-#define SUBPIC_Y_X_START 0x054C
-#define SUBPIC_Y_X_END 0x0550
-#define SUBPIC_V_INC 0x0554
-#define SUBPIC_H_INC 0x0558
+#define OV0_FLAG_CNTRL 0x04DC
+#define OV0_SLICE_CNTL 0x04E0
+#define OV0_VID_KEY_CLR_LOW 0x04E4
+#define OV0_VID_KEY_CLR_HIGH 0x04E8
+#define OV0_GRPH_KEY_CLR_LOW 0x04EC
+#define OV0_GRPH_KEY_CLR_HIGH 0x04F0
+#define OV0_KEY_CNTL 0x04F4
+#define OV0_TEST 0x04F8
+#define SUBPIC_CNTL 0x0540
+#define SUBPIC_DEFCOLCON 0x0544
+#define SUBPIC_Y_X_START 0x054C
+#define SUBPIC_Y_X_END 0x0550
+#define SUBPIC_V_INC 0x0554
+#define SUBPIC_H_INC 0x0558
#define SUBPIC_BUF0_OFFSET 0x055C
#define SUBPIC_BUF1_OFFSET 0x0560
#define SUBPIC_LC0_OFFSET 0x0564
-#define SUBPIC_LC1_OFFSET 0x0568
-#define SUBPIC_PITCH 0x056C
-#define SUBPIC_BTN_HLI_COLCON 0x0570
-#define SUBPIC_BTN_HLI_Y_X_START 0x0574
-#define SUBPIC_BTN_HLI_Y_X_END 0x0578
-#define SUBPIC_PALETTE_INDEX 0x057C
-#define SUBPIC_PALETTE_DATA 0x0580
-#define SUBPIC_H_ACCUM_INIT 0x0584
-#define SUBPIC_V_ACCUM_INIT 0x0588
-#define DISP_MISC_CNTL 0x0D00
-#define DAC_MACRO_CNTL 0x0D04
-#define DISP_PWR_MAN 0x0D08
-#define DISP_TEST_DEBUG_CNTL 0x0D10
-#define DISP_HW_DEBUG 0x0D14
+#define SUBPIC_LC1_OFFSET 0x0568
+#define SUBPIC_PITCH 0x056C
+#define SUBPIC_BTN_HLI_COLCON 0x0570
+#define SUBPIC_BTN_HLI_Y_X_START 0x0574
+#define SUBPIC_BTN_HLI_Y_X_END 0x0578
+#define SUBPIC_PALETTE_INDEX 0x057C
+#define SUBPIC_PALETTE_DATA 0x0580
+#define SUBPIC_H_ACCUM_INIT 0x0584
+#define SUBPIC_V_ACCUM_INIT 0x0588
+#define DISP_MISC_CNTL 0x0D00
+#define DAC_MACRO_CNTL 0x0D04
+#define DISP_PWR_MAN 0x0D08
+#define DISP_TEST_DEBUG_CNTL 0x0D10
+#define DISP_HW_DEBUG 0x0D14
#define DAC_CRC_SIG1 0x0D18
#define DAC_CRC_SIG2 0x0D1C
#define OV0_LIN_TRANS_A 0x0D20
-#define OV0_LIN_TRANS_B 0x0D24
-#define OV0_LIN_TRANS_C 0x0D28
-#define OV0_LIN_TRANS_D 0x0D2C
-#define OV0_LIN_TRANS_E 0x0D30
-#define OV0_LIN_TRANS_F 0x0D34
-#define OV0_GAMMA_0_F 0x0D40
-#define OV0_GAMMA_10_1F 0x0D44
-#define OV0_GAMMA_20_3F 0x0D48
-#define OV0_GAMMA_40_7F 0x0D4C
-#define OV0_GAMMA_380_3BF 0x0D50
-#define OV0_GAMMA_3C0_3FF 0x0D54
-#define DISP_MERGE_CNTL 0x0D60
-#define DISP_OUTPUT_CNTL 0x0D64
-#define DISP_LIN_TRANS_GRPH_A 0x0D80
+#define OV0_LIN_TRANS_B 0x0D24
+#define OV0_LIN_TRANS_C 0x0D28
+#define OV0_LIN_TRANS_D 0x0D2C
+#define OV0_LIN_TRANS_E 0x0D30
+#define OV0_LIN_TRANS_F 0x0D34
+#define OV0_GAMMA_0_F 0x0D40
+#define OV0_GAMMA_10_1F 0x0D44
+#define OV0_GAMMA_20_3F 0x0D48
+#define OV0_GAMMA_40_7F 0x0D4C
+#define OV0_GAMMA_380_3BF 0x0D50
+#define OV0_GAMMA_3C0_3FF 0x0D54
+#define DISP_MERGE_CNTL 0x0D60
+#define DISP_OUTPUT_CNTL 0x0D64
+#define DISP_LIN_TRANS_GRPH_A 0x0D80
#define DISP_LIN_TRANS_GRPH_B 0x0D84
#define DISP_LIN_TRANS_GRPH_C 0x0D88
#define DISP_LIN_TRANS_GRPH_D 0x0D8C
-#define DISP_LIN_TRANS_GRPH_E 0x0D90
-#define DISP_LIN_TRANS_GRPH_F 0x0D94
-#define DISP_LIN_TRANS_VID_A 0x0D98
-#define DISP_LIN_TRANS_VID_B 0x0D9C
-#define DISP_LIN_TRANS_VID_C 0x0DA0
-#define DISP_LIN_TRANS_VID_D 0x0DA4
-#define DISP_LIN_TRANS_VID_E 0x0DA8
-#define DISP_LIN_TRANS_VID_F 0x0DAC
-#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
-#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
-#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
-#define RMX_HORZ_PHASE 0x0DBC
-#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
-#define DAC_BROAD_PULSE 0x0DC4
+#define DISP_LIN_TRANS_GRPH_E 0x0D90
+#define DISP_LIN_TRANS_GRPH_F 0x0D94
+#define DISP_LIN_TRANS_VID_A 0x0D98
+#define DISP_LIN_TRANS_VID_B 0x0D9C
+#define DISP_LIN_TRANS_VID_C 0x0DA0
+#define DISP_LIN_TRANS_VID_D 0x0DA4
+#define DISP_LIN_TRANS_VID_E 0x0DA8
+#define DISP_LIN_TRANS_VID_F 0x0DAC
+#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
+#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
+#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
+#define RMX_HORZ_PHASE 0x0DBC
+#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
+#define DAC_BROAD_PULSE 0x0DC4
#define DAC_SKEW_CLKS 0x0DC8
#define DAC_INCR 0x0DCC
#define DAC_NEG_SYNC_LEVEL 0x0DD0
-#define DAC_POS_SYNC_LEVEL 0x0DD4
-#define DAC_BLANK_LEVEL 0x0DD8
-#define CLOCK_CNTL_INDEX 0x0008
-#define CLOCK_CNTL_DATA 0x000C
-#define CP_RB_CNTL 0x0704
-#define CP_RB_BASE 0x0700
-#define CP_RB_RPTR_ADDR 0x070C
-#define CP_RB_RPTR 0x0710
-#define CP_RB_WPTR 0x0714
-#define CP_RB_WPTR_DELAY 0x0718
-#define CP_IB_BASE 0x0738
-#define CP_IB_BUFSZ 0x073C
-#define SCRATCH_REG0 0x15E0
-#define GUI_SCRATCH_REG0 0x15E0
-#define SCRATCH_REG1 0x15E4
-#define GUI_SCRATCH_REG1 0x15E4
+#define DAC_POS_SYNC_LEVEL 0x0DD4
+#define DAC_BLANK_LEVEL 0x0DD8
+#define CLOCK_CNTL_INDEX 0x0008
+#define CLOCK_CNTL_DATA 0x000C
+#define CP_RB_CNTL 0x0704
+#define CP_RB_BASE 0x0700
+#define CP_RB_RPTR_ADDR 0x070C
+#define CP_RB_RPTR 0x0710
+#define CP_RB_WPTR 0x0714
+#define CP_RB_WPTR_DELAY 0x0718
+#define CP_IB_BASE 0x0738
+#define CP_IB_BUFSZ 0x073C
+#define SCRATCH_REG0 0x15E0
+#define GUI_SCRATCH_REG0 0x15E0
+#define SCRATCH_REG1 0x15E4
+#define GUI_SCRATCH_REG1 0x15E4
#define SCRATCH_REG2 0x15E8
#define GUI_SCRATCH_REG2 0x15E8
#define SCRATCH_REG3 0x15EC
-#define GUI_SCRATCH_REG3 0x15EC
-#define SCRATCH_REG4 0x15F0
-#define GUI_SCRATCH_REG4 0x15F0
-#define SCRATCH_REG5 0x15F4
-#define GUI_SCRATCH_REG5 0x15F4
-#define SCRATCH_UMSK 0x0770
-#define SCRATCH_ADDR 0x0774
-#define DP_BRUSH_FRGD_CLR 0x147C
+#define GUI_SCRATCH_REG3 0x15EC
+#define SCRATCH_REG4 0x15F0
+#define GUI_SCRATCH_REG4 0x15F0
+#define SCRATCH_REG5 0x15F4
+#define GUI_SCRATCH_REG5 0x15F4
+#define SCRATCH_UMSK 0x0770
+#define SCRATCH_ADDR 0x0774
+#define DP_BRUSH_FRGD_CLR 0x147C
#define DP_BRUSH_BKGD_CLR 0x1478
#define DST_LINE_START 0x1600
-#define DST_LINE_END 0x1604
-#define SRC_OFFSET 0x15AC
+#define DST_LINE_END 0x1604
+#define SRC_OFFSET 0x15AC
#define SRC_PITCH 0x15B0
#define SRC_TILE 0x1704
#define SRC_PITCH_OFFSET 0x1428
-#define SRC_X 0x1414
-#define SRC_Y 0x1418
-#define SRC_X_Y 0x1590
-#define SRC_Y_X 0x1434
+#define SRC_X 0x1414
+#define SRC_Y 0x1418
+#define SRC_X_Y 0x1590
+#define SRC_Y_X 0x1434
#define DST_Y_X 0x1438
#define DST_WIDTH_HEIGHT 0x1598
#define DST_HEIGHT_WIDTH 0x143c
#define DST_OFFSET 0x1404
-#define SRC_CLUT_ADDRESS 0x1780
-#define SRC_CLUT_DATA 0x1784
-#define SRC_CLUT_DATA_RD 0x1788
-#define HOST_DATA0 0x17C0
-#define HOST_DATA1 0x17C4
-#define HOST_DATA2 0x17C8
-#define HOST_DATA3 0x17CC
-#define HOST_DATA4 0x17D0
-#define HOST_DATA5 0x17D4
-#define HOST_DATA6 0x17D8
+#define SRC_CLUT_ADDRESS 0x1780
+#define SRC_CLUT_DATA 0x1784
+#define SRC_CLUT_DATA_RD 0x1788
+#define HOST_DATA0 0x17C0
+#define HOST_DATA1 0x17C4
+#define HOST_DATA2 0x17C8
+#define HOST_DATA3 0x17CC
+#define HOST_DATA4 0x17D0
+#define HOST_DATA5 0x17D4
+#define HOST_DATA6 0x17D8
#define HOST_DATA7 0x17DC
#define HOST_DATA_LAST 0x17E0
#define DP_SRC_ENDIAN 0x15D4
-#define DP_SRC_FRGD_CLR 0x15D8
-#define DP_SRC_BKGD_CLR 0x15DC
-#define SC_LEFT 0x1640
-#define SC_RIGHT 0x1644
-#define SC_TOP 0x1648
-#define SC_BOTTOM 0x164C
-#define SRC_SC_RIGHT 0x1654
-#define SRC_SC_BOTTOM 0x165C
-#define DP_CNTL 0x16C0
-#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
-#define DP_DATATYPE 0x16C4
-#define DP_MIX 0x16C8
-#define DP_WRITE_MSK 0x16CC
-#define DP_XOP 0x17F8
+#define DP_SRC_FRGD_CLR 0x15D8
+#define DP_SRC_BKGD_CLR 0x15DC
+#define SC_LEFT 0x1640
+#define SC_RIGHT 0x1644
+#define SC_TOP 0x1648
+#define SC_BOTTOM 0x164C
+#define SRC_SC_RIGHT 0x1654
+#define SRC_SC_BOTTOM 0x165C
+#define DP_CNTL 0x16C0
+#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
+#define DP_DATATYPE 0x16C4
+#define DP_MIX 0x16C8
+#define DP_WRITE_MSK 0x16CC
+#define DP_XOP 0x17F8
#define CLR_CMP_CLR_SRC 0x15C4
#define CLR_CMP_CLR_DST 0x15C8
#define CLR_CMP_CNTL 0x15C0
-#define CLR_CMP_MSK 0x15CC
-#define DSTCACHE_MODE 0x1710
-#define DSTCACHE_CTLSTAT 0x1714
-#define DEFAULT_PITCH_OFFSET 0x16E0
-#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
+#define CLR_CMP_MSK 0x15CC
+#define DSTCACHE_MODE 0x1710
+#define DSTCACHE_CTLSTAT 0x1714
+#define DEFAULT_PITCH_OFFSET 0x16E0
+#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
#define DEFAULT_SC_TOP_LEFT 0x16EC
#define SRC_PITCH_OFFSET 0x1428
#define DST_PITCH_OFFSET 0x142C
-#define DP_GUI_MASTER_CNTL 0x146C
-#define SC_TOP_LEFT 0x16EC
-#define SC_BOTTOM_RIGHT 0x16F0
-#define SRC_SC_BOTTOM_RIGHT 0x16F4
+#define DP_GUI_MASTER_CNTL 0x146C
+#define SC_TOP_LEFT 0x16EC
+#define SC_BOTTOM_RIGHT 0x16F0
+#define SRC_SC_BOTTOM_RIGHT 0x16F4
#define RB2D_DSTCACHE_MODE 0x3428
#define RB2D_DSTCACHE_CTLSTAT_broken 0x342C /* do not use */
#define LVDS_GEN_CNTL 0x02d0
@@ -686,7 +686,7 @@
#define VERT_FP_LOOP_STRETCH (0x7 << 28)
#define VERT_STRETCH_RESERVED 0xf1000000
-/* DAC_CNTL bit constants */
+/* DAC_CNTL bit constants */
#define DAC_8BIT_EN 0x00000100
#define DAC_4BPP_PIX_ORDER 0x00000200
#define DAC_CRC_EN 0x00080000
@@ -700,7 +700,7 @@
#define DAC_CMP_EN (1 << 3)
#define DAC_CMP_OUTPUT (1 << 7)
-/* DAC_CNTL2 bit constants */
+/* DAC_CNTL2 bit constants */
#define DAC2_EXPAND_MODE (1 << 14)
#define DAC2_CMP_EN (1 << 7)
#define DAC2_PALETTE_ACCESS_CNTL (1 << 5)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Linux-fbdev-devel] [PATCH 1/2] atyfb: fix CONFIG_ namespace violations
2009-02-02 23:00 ` [PATCH 1/2] atyfb: fix CONFIG_ namespace violations Randy Dunlap
@ 2009-02-03 8:09 ` Geert Uytterhoeven
2009-02-03 11:06 ` Ville Syrjälä
0 siblings, 1 reply; 6+ messages in thread
From: Geert Uytterhoeven @ 2009-02-03 8:09 UTC (permalink / raw)
To: Randy Dunlap
Cc: Andrew Morton, linux-fbdev-devel, Benjamin Herrenschmidt,
linux-kernel
On Mon, 2 Feb 2009, Randy Dunlap wrote:
> On Sat, 31 Jan 2009 12:10:08 -0800 Andrew Morton wrote:
> > On Sat, 31 Jan 2009 11:53:36 -0800 Randy Dunlap <randy.dunlap@oracle.com> wrote:
> >
> > > so staging adds a new config symbol that conflicts with the
> > > (incorrect namespace) usage in mach64.h.
> > >
> > > mach64 needs to change IMO, even though it is older.
> >
> > Sigh, yes, that file has gone on a rampage through the namespace
> > rules. I'll take a look at it sometime.
> > --
>
> I went ahead with a minimal set of changes, but you can toss them
> and do more if you prefer.
>
> ---
>
> From: Randy Dunlap <randy.dunlap@oracle.com>
>
> [1/2] Fix namespace violations by changing non-kconfig CONFIG_ names
> to CNFG_*.
>
> Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
> cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> drivers/video/aty/aty128fb.c | 8 ++++----
> drivers/video/aty/atyfb_base.c | 22 +++++++++++-----------
> drivers/video/aty/radeon_base.c | 10 +++++-----
> drivers/video/aty/radeon_pm.c | 18 +++++++++---------
> include/video/aty128.h | 4 ++--
> include/video/mach64.h | 24 ++++++++++++------------
> include/video/radeon.h | 18 +++++++++---------
> 7 files changed, 52 insertions(+), 52 deletions(-)
>
> --- linux-2.6.29-rc3-git3.orig/drivers/video/aty/atyfb_base.c
> +++ linux-2.6.29-rc3-git3/drivers/video/aty/atyfb_base.c
> @@ -135,7 +135,7 @@
> #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
> defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
> static const u32 lt_lcd_regs[] = {
> - CONFIG_PANEL_LG,
> + CNFG_PANEL_LG,
These were the official names as used in the ATI docs. After these changes, you
can no longer easily grep for them.
Perhaps it's better to prefix everything with ATI_? yes, I know it's more work
(for the writer), but we want to optimize for the reader, right?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Linux-fbdev-devel] [PATCH 1/2] atyfb: fix CONFIG_ namespace violations
2009-02-03 8:09 ` [Linux-fbdev-devel] " Geert Uytterhoeven
@ 2009-02-03 11:06 ` Ville Syrjälä
2009-02-03 22:23 ` Randy Dunlap
[not found] ` <4988C3E6.5010508@oracle.com>
0 siblings, 2 replies; 6+ messages in thread
From: Ville Syrjälä @ 2009-02-03 11:06 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Randy Dunlap, Benjamin Herrenschmidt, Andrew Morton,
linux-fbdev-devel, linux-kernel
On Tue, Feb 03, 2009 at 09:09:38AM +0100, Geert Uytterhoeven wrote:
> On Mon, 2 Feb 2009, Randy Dunlap wrote:
> > --- linux-2.6.29-rc3-git3.orig/drivers/video/aty/atyfb_base.c
> > +++ linux-2.6.29-rc3-git3/drivers/video/aty/atyfb_base.c
> > @@ -135,7 +135,7 @@
> > #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
> > defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
> > static const u32 lt_lcd_regs[] = {
> > - CONFIG_PANEL_LG,
> > + CNFG_PANEL_LG,
>
> These were the official names as used in the ATI docs. After these changes, you
> can no longer easily grep for them.
>
> Perhaps it's better to prefix everything with ATI_? yes, I know it's more work
> (for the writer), but we want to optimize for the reader, right?
That would be my preference as well.
--
Ville Syrjälä
syrjala@sci.fi
http://www.sci.fi/~syrjala/
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] atyfb: fix CONFIG_ namespace violations
2009-02-03 11:06 ` Ville Syrjälä
@ 2009-02-03 22:23 ` Randy Dunlap
[not found] ` <4988C3E6.5010508@oracle.com>
1 sibling, 0 replies; 6+ messages in thread
From: Randy Dunlap @ 2009-02-03 22:23 UTC (permalink / raw)
To: Geert Uytterhoeven, Randy Dunlap, Benjamin Herrenschmidt,
Andrew Morton
Ville Syrjälä wrote:
> On Tue, Feb 03, 2009 at 09:09:38AM +0100, Geert Uytterhoeven wrote:
>> On Mon, 2 Feb 2009, Randy Dunlap wrote:
>>> --- linux-2.6.29-rc3-git3.orig/drivers/video/aty/atyfb_base.c
>>> +++ linux-2.6.29-rc3-git3/drivers/video/aty/atyfb_base.c
>>> @@ -135,7 +135,7 @@
>>> #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
>>> defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
>>> static const u32 lt_lcd_regs[] = {
>>> - CONFIG_PANEL_LG,
>>> + CNFG_PANEL_LG,
>> These were the official names as used in the ATI docs. After these changes, you
>> can no longer easily grep for them.
>>
>> Perhaps it's better to prefix everything with ATI_? yes, I know it's more work
>> (for the writer), but we want to optimize for the reader, right?
Everything?? not just the CONFIG_* namespace violations?
[If so,] Potentially 3600 changes just in 3 header files, then all of
the corresponding .c files. No thanks.
How about a note in the header files that explains that CONFIG_* register
names are spelled as "CNFG_*" so that there are not kernel kconfig
namespace conflicts?
> That would be my preference as well.
Care to do it?
--
~Randy
------------------------------------------------------------------------------
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Linux-fbdev-devel] [PATCH 1/2] atyfb: fix CONFIG_ namespace violations
[not found] ` <4988C3E6.5010508@oracle.com>
@ 2009-02-03 23:58 ` Ville Syrjälä
0 siblings, 0 replies; 6+ messages in thread
From: Ville Syrjälä @ 2009-02-03 23:58 UTC (permalink / raw)
To: Randy Dunlap
Cc: Geert Uytterhoeven, Benjamin Herrenschmidt, Andrew Morton,
linux-fbdev-devel, linux-kernel
On Tue, Feb 03, 2009 at 02:23:34PM -0800, Randy Dunlap wrote:
> Ville Syrjälä wrote:
> > On Tue, Feb 03, 2009 at 09:09:38AM +0100, Geert Uytterhoeven wrote:
> >> On Mon, 2 Feb 2009, Randy Dunlap wrote:
> >>> --- linux-2.6.29-rc3-git3.orig/drivers/video/aty/atyfb_base.c
> >>> +++ linux-2.6.29-rc3-git3/drivers/video/aty/atyfb_base.c
> >>> @@ -135,7 +135,7 @@
> >>> #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
> >>> defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
> >>> static const u32 lt_lcd_regs[] = {
> >>> - CONFIG_PANEL_LG,
> >>> + CNFG_PANEL_LG,
> >> These were the official names as used in the ATI docs. After these changes, you
> >> can no longer easily grep for them.
> >>
> >> Perhaps it's better to prefix everything with ATI_? yes, I know it's more work
> >> (for the writer), but we want to optimize for the reader, right?
>
> Everything?? not just the CONFIG_* namespace violations?
>
> [If so,] Potentially 3600 changes just in 3 header files, then all of
> the corresponding .c files. No thanks.
That does seem quite a bit of work. But even if you change only the
CONFIG_ violations I'd say adding a prefix is preferable to changing
the register name in a way that makes it more difficult to look it up
in the chip documentation.
--
Ville Syrjälä
syrjala@sci.fi
http://www.sci.fi/~syrjala/
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2009-02-03 23:58 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2009-02-02 23:00 ` [PATCH 1/2] atyfb: fix CONFIG_ namespace violations Randy Dunlap
2009-02-03 8:09 ` [Linux-fbdev-devel] " Geert Uytterhoeven
2009-02-03 11:06 ` Ville Syrjälä
2009-02-03 22:23 ` Randy Dunlap
[not found] ` <4988C3E6.5010508@oracle.com>
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2009-02-02 23:00 ` [PATCH 2/2] atyfb: fix header file trailing whitespace Randy Dunlap
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