Re: [PATCH v14 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver

[kernel test robot <lkp@intel.com>]

Hi Bo-Chen,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm/drm-next pza/reset/next linus/master v5.19-rc6 next-20220715]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Bo-Chen-Chen/drm-mediatek-Add-MT8195-DisplayPort-driver/20220712-191341
base:   git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
config: arm-allyesconfig (https://download.01.org/0day-ci/archive/20220716/202207160102.zyueiI7S-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/a3869f524e16c38015e0f124c6597927fc6d26b0
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Bo-Chen-Chen/drm-mediatek-Add-MT8195-DisplayPort-driver/20220712-191341
        git checkout a3869f524e16c38015e0f124c6597927fc6d26b0
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/gpu/drm/mediatek/ drivers/pci/controller/dwc/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/mediatek/mtk_dp.c: In function 'mtk_dp_train_tps_1':
>> drivers/gpu/drm/mediatek/mtk_dp.c:1092:12: warning: variable 'val' set but not used [-Wunused-but-set-variable]
    1092 |         u8 val;
         |            ^~~
   drivers/gpu/drm/mediatek/mtk_dp.c: In function 'mtk_dp_bridge_atomic_get_output_bus_fmts':
   drivers/gpu/drm/mediatek/mtk_dp.c:1865:26: error: 'MEDIA_BUS_FMT_FIXED' undeclared (first use in this function)
    1865 |         output_fmts[0] = MEDIA_BUS_FMT_FIXED;
         |                          ^~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/mediatek/mtk_dp.c:1865:26: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu/drm/mediatek/mtk_dp.c: At top level:
   drivers/gpu/drm/mediatek/mtk_dp.c:1870:9: error: 'MEDIA_BUS_FMT_RGB888_1X24' undeclared here (not in a function)
    1870 |         MEDIA_BUS_FMT_RGB888_1X24,
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/mediatek/mtk_dp.c:1871:9: error: 'MEDIA_BUS_FMT_YUV8_1X24' undeclared here (not in a function)
    1871 |         MEDIA_BUS_FMT_YUV8_1X24,
         |         ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/mediatek/mtk_dp.c:1872:9: error: 'MEDIA_BUS_FMT_YUYV8_1X16' undeclared here (not in a function)
    1872 |         MEDIA_BUS_FMT_YUYV8_1X16,
         |         ^~~~~~~~~~~~~~~~~~~~~~~~


vim +/val +1092 drivers/gpu/drm/mediatek/mtk_dp.c

  1087	
  1088	static int mtk_dp_train_tps_1(struct mtk_dp *mtk_dp, u8 target_lane_count,
  1089				      int *iteration_count, u8 *lane_adjust,
  1090				      int *status_control, u8 *prev_lane_adjust)
  1091	{
> 1092		u8 val;
  1093		u8 link_status[DP_LINK_STATUS_SIZE] = {};
  1094	
  1095		mtk_dp_training_set_scramble(mtk_dp, false);
  1096	
  1097		if (*status_control == 0) {
  1098			mtk_dp_train_set_pattern(mtk_dp, 1);
  1099			val = DP_LINK_SCRAMBLING_DISABLE |
  1100				DP_TRAINING_PATTERN_1;
  1101			drm_dp_dpcd_writeb(&mtk_dp->aux,
  1102					   DP_TRAINING_PATTERN_SET,
  1103					   DP_LINK_SCRAMBLING_DISABLE |
  1104					   DP_TRAINING_PATTERN_1);
  1105			drm_dp_dpcd_read(&mtk_dp->aux,
  1106					 DP_ADJUST_REQUEST_LANE0_1,
  1107					 lane_adjust,
  1108					 sizeof(*lane_adjust) * 2);
  1109	
  1110			mtk_dp_train_update_swing_pre(mtk_dp,
  1111						      target_lane_count, lane_adjust);
  1112			*status_control = 1;
  1113			(*iteration_count)++;
  1114		}
  1115	
  1116		drm_dp_link_train_clock_recovery_delay(&mtk_dp->aux, mtk_dp->rx_cap);
  1117		drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);
  1118	
  1119		if (drm_dp_clock_recovery_ok(link_status,
  1120					     target_lane_count)) {
  1121			mtk_dp->train_info.cr_done = true;
  1122			*iteration_count = 1;
  1123			dev_dbg(mtk_dp->dev, "Link train CR pass\n");
  1124			return 0;
  1125		} else if (*prev_lane_adjust == link_status[4]) {
  1126			(*iteration_count)++;
  1127			if (*prev_lane_adjust & DP_ADJUST_VOLTAGE_SWING_LANE0_MASK) {
  1128				dev_dbg(mtk_dp->dev, "Link train CQ fail\n");
  1129				return -EINVAL;
  1130			}
  1131		} else {
  1132			*prev_lane_adjust = link_status[4];
  1133		}
  1134		return -EAGAIN;
  1135	}
  1136	

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