From: Joel Fernandes <joelagnelf@nvidia.com>
To: linux-kernel@vger.kernel.org
Cc: "Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Jonathan Corbet" <corbet@lwn.net>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Tvrtko Ursulin" <tursulin@ursulin.net>,
"Huang Rui" <ray.huang@amd.com>,
"Matthew Auld" <matthew.auld@intel.com>,
"Matthew Brost" <matthew.brost@intel.com>,
"Lucas De Marchi" <lucas.demarchi@intel.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
"Helge Deller" <deller@gmx.de>,
"Danilo Krummrich" <dakr@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"Miguel Ojeda" <ojeda@kernel.org>,
"Alex Gaynor" <alex.gaynor@gmail.com>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Benno Lossin" <lossin@kernel.org>,
"Andreas Hindborg" <a.hindborg@kernel.org>,
"Trevor Gross" <tmgross@umich.edu>,
"John Hubbard" <jhubbard@nvidia.com>,
"Alistair Popple" <apopple@nvidia.com>,
"Timur Tabi" <ttabi@nvidia.com>, "Edwin Peer" <epeer@nvidia.com>,
"Alexandre Courbot" <acourbot@nvidia.com>,
"Andrea Righi" <arighi@nvidia.com>,
"Andy Ritger" <aritger@nvidia.com>, "Zhi Wang" <zhiw@nvidia.com>,
"Balbir Singh" <balbirs@nvidia.com>,
"Philipp Stanner" <phasta@kernel.org>,
"Elle Rhumsaa" <elle@weathered-steel.dev>,
"Daniel Almeida" <daniel.almeida@collabora.com>,
"Eliot Courtney" <ecourtney@nvidia.com>,
joel@joelfernandes.org, nouveau@lists.freedesktop.org,
dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org,
linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
linux-fbdev@vger.kernel.org,
"Joel Fernandes" <joelagnelf@nvidia.com>,
"Nikola Djukic" <ndjukic@nvidia.com>
Subject: [PATCH v7 19/23] nova-core: mm: Add PRAMIN aperture self-tests
Date: Wed, 18 Feb 2026 16:20:16 -0500 [thread overview]
Message-ID: <20260218212020.800836-20-joelagnelf@nvidia.com> (raw)
In-Reply-To: <20260218212020.800836-1-joelagnelf@nvidia.com>
Add self-tests for the PRAMIN aperture mechanism to verify correct
operation during GPU probe. The tests validate various alignment
requirements and corner cases.
The tests are default disabled and behind CONFIG_NOVA_PRAMIN_SELFTESTS.
When enabled, tests run after GSP boot during probe.
Cc: Nikola Djukic <ndjukic@nvidia.com>
Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
---
drivers/gpu/nova-core/Kconfig | 4 +-
drivers/gpu/nova-core/gpu.rs | 3 +
drivers/gpu/nova-core/mm/pramin.rs | 161 +++++++++++++++++++++++++++++
3 files changed, 166 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/nova-core/Kconfig b/drivers/gpu/nova-core/Kconfig
index d0d4177adb1b..35de55aabcfc 100644
--- a/drivers/gpu/nova-core/Kconfig
+++ b/drivers/gpu/nova-core/Kconfig
@@ -21,7 +21,7 @@ config NOVA_MM_SELFTESTS
depends on NOVA_CORE
help
Enable self-tests for the memory management subsystem. When enabled,
- tests are run during GPU probe to verify page table walking, and BAR1
- virtual memory mapping functionality.
+ tests are run during GPU probe to verify PRAMIN aperture access,
+ page table walking, and BAR1 virtual memory mapping functionality.
This is a testing option and is default-disabled.
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index f17bf1bf0b12..af5a0ffe78aa 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -338,6 +338,9 @@ fn run_mm_selftests(
let mmu_version = MmuVersion::from(self.spec.chipset.arch());
+ // PRAMIN aperture self-tests.
+ crate::mm::pramin::run_self_test(pdev.as_ref(), self.bar.clone(), mmu_version)?;
+
// BAR1 self-tests.
let bar1 = Arc::pin_init(
pdev.iomap_region_sized::<BAR1_SIZE>(1, c"nova-core/bar1"),
diff --git a/drivers/gpu/nova-core/mm/pramin.rs b/drivers/gpu/nova-core/mm/pramin.rs
index 77916f5b231e..da98208b9cb7 100644
--- a/drivers/gpu/nova-core/mm/pramin.rs
+++ b/drivers/gpu/nova-core/mm/pramin.rs
@@ -291,3 +291,164 @@ fn drop(&mut self) {
// MutexGuard drops automatically, releasing the lock.
}
}
+
+/// Run PRAMIN self-tests during boot if self-tests are enabled.
+#[cfg(CONFIG_NOVA_MM_SELFTESTS)]
+pub(crate) fn run_self_test(
+ dev: &kernel::device::Device,
+ bar: Arc<Devres<Bar0>>,
+ mmu_version: super::pagetable::MmuVersion,
+) -> Result {
+ use super::pagetable::MmuVersion;
+
+ // PRAMIN support is only for MMU v2 for now (Turing/Ampere/Ada).
+ if mmu_version != MmuVersion::V2 {
+ dev_info!(
+ dev,
+ "PRAMIN: Skipping self-tests for MMU {:?} (only V2 supported)\n",
+ mmu_version
+ );
+ return Ok(());
+ }
+
+ dev_info!(dev, "PRAMIN: Starting self-test...\n");
+
+ let pramin = Arc::pin_init(Pramin::new(bar)?, GFP_KERNEL)?;
+ let mut win = pramin.window()?;
+
+ // Use offset 0x1000 as test area.
+ let base: usize = 0x1000;
+
+ // Test 1: Read/write at byte-aligned locations.
+ for i in 0u8..4 {
+ let offset = base + 1 + usize::from(i); // Offsets 0x1001, 0x1002, 0x1003, 0x1004
+ let val = 0xA0 + i;
+ win.try_write8(offset, val)?;
+ let read_val = win.try_read8(offset)?;
+ if read_val != val {
+ dev_err!(
+ dev,
+ "PRAMIN: FAIL - offset {:#x}: wrote {:#x}, read {:#x}\n",
+ offset,
+ val,
+ read_val
+ );
+ return Err(EIO);
+ }
+ }
+
+ // Test 2: Write `u32` and read back as `u8`s.
+ let test2_offset = base + 0x10;
+ let test2_val: u32 = 0xDEADBEEF;
+ win.try_write32(test2_offset, test2_val)?;
+
+ // Read back as individual bytes (little-endian: EF BE AD DE).
+ let expected_bytes: [u8; 4] = [0xEF, 0xBE, 0xAD, 0xDE];
+ for (i, &expected) in expected_bytes.iter().enumerate() {
+ let read_val = win.try_read8(test2_offset + i)?;
+ if read_val != expected {
+ dev_err!(
+ dev,
+ "PRAMIN: FAIL - offset {:#x}: expected {:#x}, read {:#x}\n",
+ test2_offset + i,
+ expected,
+ read_val
+ );
+ return Err(EIO);
+ }
+ }
+
+ // Test 3: Window repositioning across 1MB boundaries.
+ // Write to offset > 1MB to trigger window slide, then verify.
+ let test3_offset_a: usize = base; // First 1MB region.
+ let test3_offset_b: usize = 0x200000 + base; // 2MB + base (different 1MB region).
+ let val_a: u32 = 0x11111111;
+ let val_b: u32 = 0x22222222;
+
+ // Write to first region.
+ win.try_write32(test3_offset_a, val_a)?;
+
+ // Write to second region (triggers window reposition).
+ win.try_write32(test3_offset_b, val_b)?;
+
+ // Read back from second region.
+ let read_b = win.try_read32(test3_offset_b)?;
+ if read_b != val_b {
+ dev_err!(
+ dev,
+ "PRAMIN: FAIL - offset {:#x}: expected {:#x}, read {:#x}\n",
+ test3_offset_b,
+ val_b,
+ read_b
+ );
+ return Err(EIO);
+ }
+
+ // Read back from first region (triggers window reposition again).
+ let read_a = win.try_read32(test3_offset_a)?;
+ if read_a != val_a {
+ dev_err!(
+ dev,
+ "PRAMIN: FAIL - offset {:#x}: expected {:#x}, read {:#x}\n",
+ test3_offset_a,
+ val_a,
+ read_a
+ );
+ return Err(EIO);
+ }
+
+ // Test 4: Invalid offset rejection (beyond 40-bit address space).
+ {
+ // 40-bit address space limit check.
+ let invalid_offset: usize = MAX_VRAM_OFFSET + 1;
+ let result = win.try_read32(invalid_offset);
+ if result.is_ok() {
+ dev_err!(
+ dev,
+ "PRAMIN: FAIL - read at invalid offset {:#x} should have failed\n",
+ invalid_offset
+ );
+ return Err(EIO);
+ }
+ }
+
+ // Test 5: Misaligned multi-byte access rejection.
+ // Verify that misaligned `u16`/`u32`/`u64` accesses are properly rejected.
+ {
+ // `u16` at odd offset (not 2-byte aligned).
+ let offset_u16 = base + 0x21;
+ if win.try_write16(offset_u16, 0xABCD).is_ok() {
+ dev_err!(
+ dev,
+ "PRAMIN: FAIL - misaligned u16 write at {:#x} should have failed\n",
+ offset_u16
+ );
+ return Err(EIO);
+ }
+
+ // `u32` at 2-byte-aligned (not 4-byte-aligned) offset.
+ let offset_u32 = base + 0x32;
+ if win.try_write32(offset_u32, 0x12345678).is_ok() {
+ dev_err!(
+ dev,
+ "PRAMIN: FAIL - misaligned u32 write at {:#x} should have failed\n",
+ offset_u32
+ );
+ return Err(EIO);
+ }
+
+ // `u64` read at 4-byte-aligned (not 8-byte-aligned) offset.
+ let offset_u64 = base + 0x44;
+ if win.try_read64(offset_u64).is_ok() {
+ dev_err!(
+ dev,
+ "PRAMIN: FAIL - misaligned u64 read at {:#x} should have failed\n",
+ offset_u64
+ );
+ return Err(EIO);
+ }
+ }
+
+ dev_info!(dev, "PRAMIN: All self-tests PASSED\n");
+ Ok(())
+}
--
2.34.1
next prev parent reply other threads:[~2026-02-18 21:21 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-18 21:19 [PATCH v7 00/23] nova-core: Add memory management support Joel Fernandes
2026-02-18 21:19 ` [PATCH v7 01/23] nova-core: mm: Add support to use PRAMIN windows to write to VRAM Joel Fernandes
2026-02-18 21:19 ` [PATCH v7 02/23] docs: gpu: nova-core: Document the PRAMIN aperture mechanism Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 03/23] nova-core: Add BAR1 aperture type and size constant Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 04/23] nova-core: gsp: Add BAR1 PDE base accessors Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 05/23] nova-core: mm: Add common memory management types Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 06/23] nova-core: mm: Add common types for all page table formats Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 07/23] nova-core: mm: Add MMU v2 page table types Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 08/23] nova-core: mm: Add MMU v3 " Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 09/23] nova-core: mm: Add unified page table entry wrapper enums Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 10/23] nova-core: mm: Add TLB flush support Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 11/23] nova-core: mm: Add GpuMm centralized memory manager Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 12/23] nova-core: mm: Add page table walker for MMU v2/v3 Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 13/23] nova-core: mm: Add Virtual Memory Manager Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 14/23] nova-core: mm: Add virtual address range tracking to VMM Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 15/23] nova-core: mm: Add multi-page mapping API " Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 16/23] nova-core: mm: Add BAR1 user interface Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 17/23] nova-core: gsp: Return GspStaticInfo and FbLayout from boot() Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 18/23] nova-core: mm: Add BAR1 memory management self-tests Joel Fernandes
2026-02-18 21:20 ` Joel Fernandes [this message]
2026-02-18 21:20 ` [PATCH v7 20/23] nova-core: gsp: Extract usable FB region from GSP Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 21/23] nova-core: fb: Add usable_vram field to FbLayout Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 22/23] nova-core: mm: Use usable VRAM region for buddy allocator Joel Fernandes
2026-02-18 21:20 ` [PATCH v7 23/23] nova-core: mm: Add BarUser to struct Gpu and create at boot Joel Fernandes
2026-02-19 15:20 ` [PATCH v7 00/23] nova-core: Add memory management support Alexandre Courbot
2026-02-19 19:48 ` Joel Fernandes
2026-02-20 1:54 ` Alexandre Courbot
2026-02-20 3:25 ` Alexandre Courbot
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