From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EA644A012B; Tue, 1 Sep 2026 18:51:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788288674; cv=none; b=kKrSMtZnJACxH8clLnQm7IOijm8GQ+qQ6b19mZmSqDSR1UAAbOMRJSEBFDhKQOWBEtqORFfFO2cXO3z8QmPpJIqvSuLKPk0C79bl8jtQOhT2fT5cPi9wtsPu5PI4UXKMTOv9qoVaJC3aKBm7MJQj2n2vKXukm0sKSvlysiqgrn0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788288674; c=relaxed/simple; bh=PsQOYxICkFHONAMa1SotvPoVv5QJ9j94I5evVuz6mdQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=glei8i97AnUQU+8QtUDdW69tyY22gA0kF3WW6d7GydYtUfIl2pps4hccVxjSRGZYgi2i+QjbLUTk0WoiZw88QNi7Lihm5hBejtMydlnI0Pvsp/VCr7itSevbC2vOZIYl/9x1H7b03ynfX03re+h9n+iCFmkSpEKpczWhU+Ca+j8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=US2DkFNZ; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="US2DkFNZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788288668; bh=PsQOYxICkFHONAMa1SotvPoVv5QJ9j94I5evVuz6mdQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=US2DkFNZ9udIhak13OPHmaVgauR1X9EG/LaEdQ6uU6NbLYqJDS4hWOfoEFafb/peX luPYk33yCY6SDA3q1c4msA0r1mS053SCokPfgJDuvwzTuKDAaKI5A3or20qu++0E4q cqg2BNMFhNcYKRiCLlJ7N99wLRhBW+7iJDeg48Gdz32cGYIaW5y347nysmTXV+Dxr2 UCQRIysmR3Aa1O+xRPo27DOtpBv3ruqL4U16P6ojv2MtmtbtJfDo9Y8NrW/Deyvg8O vE9uoS2tRLIPUkdh0ls+V6E+hYeB1NPgECJizl4OOaF3K+dIL/aNZWL+sQLJru9saV cUwSwRL8XdCuA== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 624B917E3C4B; Tue, 01 Sep 2026 20:51:08 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 01 Sep 2026 21:51:01 +0300 Subject: [PATCH v11 37/74] drm/rockchip: dw_hdmi_qp: Implement .{enable,disable}_hpd() PHY ops Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260901-dw-hdmi-qp-scramb-v11-37-bc12954a0688@collabora.com> References: <20260901-dw-hdmi-qp-scramb-v11-0-bc12954a0688@collabora.com> In-Reply-To: <20260901-dw-hdmi-qp-scramb-v11-0-bc12954a0688@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Dave Stevenson , Dmitry Baryshkov , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Chen-Yu Tsai , Samuel Holland , =?utf-8?q?Ma=C3=ADra_Canal?= , Raspberry Pi Kernel Maintenance , Raphael Gallais-Pou , Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Algea Cao , Daniel Stone , Liu Ying , Phong LE , Helge Deller Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-fbdev@vger.kernel.org, Maud Spierings , Diederik de Haas X-Mailer: b4 0.15.2 Implement .enable_hpd() and .disable_hpd() phy ops for RK3576 and RK3588 SoCs, used by the corresponding bridge callbacks for HPD activation control. Consolidate the interrupt clear-and-unmask sequence into enable_hpd() and the mask-only operation into disable_hpd(), replacing the open-coded register writes in the interrupt handlers and io_init(). The .setup_hpd() phy op, which was previously called from dw_hdmi_qp_init_hw(), is no longer needed and its users are removed. Tested-by: Maud Spierings Tested-by: Diederik de Haas # NanoPC-T6 LTS, Rock 5B Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 78 +++++++++++++------------- 1 file changed, 38 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c index bcfa6646546e..9e48ec06eb66 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -277,7 +277,7 @@ dw_hdmi_qp_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) return val ? connector_status_connected : connector_status_disconnected; } -static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +static void dw_hdmi_qp_rk3588_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) { struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; u32 val; @@ -292,11 +292,25 @@ static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); } +static void dw_hdmi_qp_rk3588_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +{ + struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + u32 val; + + if (hdmi->port_id) + val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1); + else + val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1); + + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); +} + static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = { .init = dw_hdmi_qp_rk3588_phy_init, .disable = dw_hdmi_qp_rk3588_phy_disable, .read_hpd = dw_hdmi_qp_rk3588_read_hpd, - .setup_hpd = dw_hdmi_qp_rk3588_setup_hpd, + .enable_hpd = dw_hdmi_qp_rk3588_enable_hpd, + .disable_hpd = dw_hdmi_qp_rk3588_disable_hpd, }; static enum drm_connector_status @@ -311,7 +325,7 @@ dw_hdmi_qp_rk3576_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) connector_status_connected : connector_status_disconnected; } -static void dw_hdmi_qp_rk3576_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +static void dw_hdmi_qp_rk3576_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) { struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; u32 val; @@ -320,14 +334,22 @@ static void dw_hdmi_qp_rk3576_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0)); regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); - regmap_write(hdmi->regmap, 0xa404, 0xffff0102); +} + +static void dw_hdmi_qp_rk3576_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +{ + struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + + regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, + FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1)); } static const struct dw_hdmi_qp_phy_ops rk3576_hdmi_phy_ops = { .init = dw_hdmi_qp_rk3588_phy_init, .disable = dw_hdmi_qp_rk3588_phy_disable, .read_hpd = dw_hdmi_qp_rk3576_read_hpd, - .setup_hpd = dw_hdmi_qp_rk3576_setup_hpd, + .enable_hpd = dw_hdmi_qp_rk3576_enable_hpd, + .disable_hpd = dw_hdmi_qp_rk3576_disable_hpd, }; static void dw_hdmi_qp_rk3588_hpd_work(struct work_struct *work) @@ -348,13 +370,12 @@ static void dw_hdmi_qp_rk3588_hpd_work(struct work_struct *work) static irqreturn_t dw_hdmi_qp_rk3576_hardirq(int irq, void *dev_id) { struct rockchip_hdmi_qp *hdmi = dev_id; - u32 intr_stat, val; + u32 intr_stat; regmap_read(hdmi->regmap, RK3576_IOC_HDMI_HPD_STATUS, &intr_stat); - if (intr_stat & RK3576_HDMI_OHPD_INT) { - val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1); - regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); + if (intr_stat & RK3576_HDMI_OHPD_INT) { + dw_hdmi_qp_rk3576_disable_hpd(NULL, hdmi); return IRQ_WAKE_THREAD; } @@ -364,15 +385,11 @@ static irqreturn_t dw_hdmi_qp_rk3576_hardirq(int irq, void *dev_id) static irqreturn_t dw_hdmi_qp_rk3576_irq(int irq, void *dev_id) { struct rockchip_hdmi_qp *hdmi = dev_id; - u32 val; - val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1); - regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); mod_delayed_work(system_percpu_wq, &hdmi->hpd_work, msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); - val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0); - regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); + dw_hdmi_qp_rk3576_enable_hpd(NULL, hdmi); return IRQ_HANDLED; } @@ -380,18 +397,14 @@ static irqreturn_t dw_hdmi_qp_rk3576_irq(int irq, void *dev_id) static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id) { struct rockchip_hdmi_qp *hdmi = dev_id; - u32 intr_stat, val; + u32 intr_stat; regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); intr_stat &= hdmi->port_id ? RK3588_HDMI1_OHPD_INT : RK3588_HDMI0_OHPD_INT; if (intr_stat) { - if (hdmi->port_id) - val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1); - else - val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1); - regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + dw_hdmi_qp_rk3588_disable_hpd(NULL, hdmi); return IRQ_WAKE_THREAD; } @@ -401,22 +414,11 @@ static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id) static irqreturn_t dw_hdmi_qp_rk3588_irq(int irq, void *dev_id) { struct rockchip_hdmi_qp *hdmi = dev_id; - u32 val; - - if (hdmi->port_id) - val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1); - else - val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_CLR, 1); - regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); mod_delayed_work(system_percpu_wq, &hdmi->hpd_work, msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); - if (hdmi->port_id) - val |= FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0); - else - val |= FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 0); - regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + dw_hdmi_qp_rk3588_enable_hpd(NULL, hdmi); return IRQ_HANDLED; } @@ -429,11 +431,11 @@ static void dw_hdmi_qp_rk3576_io_init(struct rockchip_hdmi_qp *hdmi) FIELD_PREP_WM16(RK3576_SDAIN_MASK, 1) | FIELD_PREP_WM16(RK3576_HDMI_GRANT_SEL, 1) | FIELD_PREP_WM16(RK3576_I2S_SEL_MASK, 1); - regmap_write(hdmi->vo_regmap, RK3576_VO0_GRF_SOC_CON14, val); - val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1); - regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); + regmap_write(hdmi->regmap, 0xa404, 0xffff0102); + + dw_hdmi_qp_rk3576_disable_hpd(NULL, hdmi); } static void dw_hdmi_qp_rk3588_io_init(struct rockchip_hdmi_qp *hdmi) @@ -458,11 +460,7 @@ static void dw_hdmi_qp_rk3588_io_init(struct rockchip_hdmi_qp *hdmi) val = FIELD_PREP_WM16(RK3588_HDMI0_GRANT_SEL, 1); regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val); - if (hdmi->port_id) - val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1); - else - val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1); - regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + dw_hdmi_qp_rk3588_disable_hpd(NULL, hdmi); } static void dw_hdmi_qp_rk3576_enc_init(struct rockchip_hdmi_qp *hdmi, -- 2.55.0