From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27F85C433EF for ; Tue, 26 Jul 2022 08:46:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232243AbiGZIqs (ORCPT ); Tue, 26 Jul 2022 04:46:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231187AbiGZIqr (ORCPT ); Tue, 26 Jul 2022 04:46:47 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5C862F66C; Tue, 26 Jul 2022 01:46:45 -0700 (PDT) X-UUID: 63514b995795457cac9035d883ae8191-20220726 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:c2016e17-6c6a-4d78-baec-69e09740b5c2,OB:0,LO B:0,IP:0,URL:25,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:70 X-CID-INFO: VERSION:1.1.8,REQID:c2016e17-6c6a-4d78-baec-69e09740b5c2,OB:0,LOB: 0,IP:0,URL:25,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:70 X-CID-META: VersionHash:0f94e32,CLOUDID:ac460dee-db04-4499-9fdf-04ef44b9468c,C OID:cd19d327659d,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 63514b995795457cac9035d883ae8191-20220726 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 284345635; Tue, 26 Jul 2022 16:46:41 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 26 Jul 2022 16:46:40 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 26 Jul 2022 16:46:40 +0800 Message-ID: <38f785af2815e45d175f02d9970e3401e700a645.camel@mediatek.com> Subject: Re: [PATCH v14 01/10] dt-bindings: mediatek,dp: Add Display Port binding From: CK Hu To: Rex-BC Chen , , , , , , , , , , CC: , , , , , , , , , , , , Date: Tue, 26 Jul 2022 16:46:40 +0800 In-Reply-To: References: <20220712111223.13080-1-rex-bc.chen@mediatek.com> <20220712111223.13080-2-rex-bc.chen@mediatek.com> <0e1d4cef6b7e72813300eb9be5650066166ac763.camel@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org On Tue, 2022-07-26 at 14:18 +0800, Rex-BC Chen wrote: > On Wed, 2022-07-13 at 15:56 +0800, CK Hu wrote: > > Hi, Bo-Chen: > > > > On Tue, 2022-07-12 at 19:12 +0800, Bo-Chen Chen wrote: > > > From: Markus Schneider-Pargmann > > > > > > This controller is present on several mediatek hardware. > > > Currently > > > mt8195 and mt8395 have this controller without a functional > > > difference, > > > so only one compatible field is added. > > > > > > The controller can have two forms, as a normal display port and > > > as > > > an > > > embedded display port. > > > > > > Signed-off-by: Markus Schneider-Pargmann > > > Signed-off-by: Guillaume Ranquet > > > Signed-off-by: Bo-Chen Chen > > > --- > > > .../display/mediatek/mediatek,dp.yaml | 115 > > > ++++++++++++++++++ > > > 1 file changed, 115 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > > ml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp. > > > ya > > > ml > > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp. > > > ya > > > ml > > > new file mode 100644 > > > index 000000000000..e2d6cb314297 > > > --- /dev/null > > > +++ > > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp. > > > ya > > > ml > > > @@ -0,0 +1,115 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: > > > http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: MediaTek Display Port Controller > > > + > > > +maintainers: > > > + - Chun-Kuang Hu > > > + - Jitao shi > > > + > > > +description: | > > > + Device tree bindings for the MediaTek display port TX (DP) and > > > + embedded display port TX (eDP) controller present on some > > > MediaTek > > > SoCs. > > > + MediaTek DP and eDP are different hardwares and they have > > > different > > > + base address for registers, so we need two different > > > compatibles > > > to > > > + separate them. > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - mediatek,mt8195-dp-tx > > > + - mediatek,mt8195-edp-tx > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + nvmem-cells: > > > + maxItems: 1 > > > + description: efuse data for display port calibration > > > + > > > + nvmem-cell-names: > > > + const: dp_calibration_data > > > + > > > + power-domains: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: Input endpoint of the controller, usually > > > dp_intf > > > + > > > + port@1: > > > + $ref: /schemas/graph.yaml#/$defs/port-base > > > + unevaluatedProperties: false > > > + description: Output endpoint of the controller > > > + properties: > > > + endpoint: > > > + $ref: /schemas/media/video-interfaces.yaml# > > > + unevaluatedProperties: false > > > + properties: > > > + data-lanes: > > > + description: | > > > + number of lanes supported by the hardware. > > > + The possible values: > > > + 0 - For 1 lane enabled in IP. > > > + 0 1 - For 2 lanes enabled in IP. > > > + 0 1 2 3 - For 4 lanes enabled in IP. > > > + minItems: 1 > > > + maxItems: 4 > > > + required: > > > + - data-lanes > > > + > > > + required: > > > + - port@0 > > > + - port@1 > > > + > > > + max-linkrate-mhz: > > > + enum: [ 1620, 2700, 5400, 8100 ] > > > + description: maximum link rate supported by the hardware. > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - interrupts > > > + - ports > > > + - max-linkrate-mhz > > > + > > > +additionalProperties: false > > > + > > > +examples: > > > + - | > > > + #include > > > + #include > > > + dp_tx@1c600000 { > > > + compatible = "mediatek,mt8195-dp-tx"; > > > + reg = <0x1c600000 0x8000>; > > > + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; > > > + interrupts = ; > > > + max-linkrate-mhz = <8100>; > > > > Why dp-tx has no clock property? I think this device should work > > with > > a > > clock. > > > > Regards, > > CK > > > > Hello CK, > > We just need to enable the power domain of dp. > The clock of dp is generated by itself and we are not using the > global > pll to generate clocks. Add this to description because this is not trivial. Regards, CK > > BRs, > Bo-Chen > > > > + > > > + ports { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + port@0 { > > > + reg = <0>; > > > + dptx_in: endpoint { > > > + remote-endpoint = <&dp_intf0_out>; > > > + }; > > > + }; > > > + port@1 { > > > + reg = <1>; > > > + dptx_out: endpoint { > > > + data-lanes = <0 1 2 3>; > > > + }; > > > + }; > > > + }; > > > + }; > > > > > >