[PATCH] [git tree] Intel i9xx support for intelfb

[PATCH] [git tree] Intel i9xx support for intelfb

[Dave Airlie]

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This patch adds support for i915G, i915GM and i945G to the intelfb
driver in the kernel.

It comes from work done by me on an X.org driver to support some
non-VBE modesetting.

This code isn't perfect but I've got no documentation so I cannot
answer some questions on what exactly is going on just yet...

The code is also available in the i915fb branch or
git://git.kernel.org/pub/scm/linux/kernel/git/airlied/intelfb-2.6

It may need more testing on the i945G, and I think adding i945GM
support might only be a few lines of code...

Is there a framebuffer git tree this could go in?

Dave.

[-- Attachment #2: intelfb_i9xx.diff --]
[-- Type: text/x-patch, Size: 24509 bytes --]

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index f5079c7..bc8ec78 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -725,7 +725,7 @@ config FB_I810_I2C
 
 config FB_INTEL
 	tristate "Intel 830M/845G/852GM/855GM/865G support (EXPERIMENTAL)"
-	depends on FB && EXPERIMENTAL && PCI && X86_32
+	depends on FB && EXPERIMENTAL && PCI && X86
 	select AGP
 	select AGP_INTEL
 	select FB_MODE_HELPERS
diff --git a/drivers/video/intelfb/intelfb.h b/drivers/video/intelfb/intelfb.h
index da29d00..de9875c 100644
--- a/drivers/video/intelfb/intelfb.h
+++ b/drivers/video/intelfb/intelfb.h
@@ -8,9 +8,9 @@
 
 
 /*** Version/name ***/
-#define INTELFB_VERSION			"0.9.2"
+#define INTELFB_VERSION			"0.9.3"
 #define INTELFB_MODULE_NAME		"intelfb"
-#define SUPPORTED_CHIPSETS		"830M/845G/852GM/855GM/865G/915G/915GM"
+#define SUPPORTED_CHIPSETS		"830M/845G/852GM/855GM/865G/915G/915GM/945G"
 
 
 /*** Debug/feature defines ***/
@@ -52,6 +52,7 @@
 #define PCI_DEVICE_ID_INTEL_865G	0x2572
 #define PCI_DEVICE_ID_INTEL_915G	0x2582
 #define PCI_DEVICE_ID_INTEL_915GM	0x2592
+#define PCI_DEVICE_ID_INTEL_945G	0x2772
 
 /* Size of MMIO region */
 #define INTEL_REG_SIZE			0x80000
@@ -125,7 +126,8 @@ enum intel_chips {
 	INTEL_855GME,
 	INTEL_865G,
 	INTEL_915G,
-	INTEL_915GM
+	INTEL_915GM,
+	INTEL_945G
 };
 
 struct intelfb_hwstate {
@@ -277,8 +279,13 @@ struct intelfb_info {
 
 	/* driver registered */
 	int registered;
+	
+	/* index into plls */
+	int pll_index;
 };
 
+#define IS_I9xx(dinfo) (((dinfo)->chipset == INTEL_915G)||(dinfo->chipset == INTEL_915GM)||((dinfo)->chipset == INTEL_945G))
+
 /*** function prototypes ***/
 
 extern int intelfb_var_to_depth(const struct fb_var_screeninfo *var);
diff --git a/drivers/video/intelfb/intelfbdrv.c b/drivers/video/intelfb/intelfbdrv.c
index 995b47c..b96001b 100644
--- a/drivers/video/intelfb/intelfbdrv.c
+++ b/drivers/video/intelfb/intelfbdrv.c
@@ -1,11 +1,12 @@
 /*
  * intelfb
  *
- * Linux framebuffer driver for Intel(R) 830M/845G/852GM/855GM/865G/915G/915GM
- * integrated graphics chips.
+ * Linux framebuffer driver for Intel(R) 830M/845G/852GM/855GM/865G/915G/915GM/
+ * 945G integrated graphics chips.
  *
  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
  *                   2004 Sylvain Meyer
+ *                   2006 David Airlie
  *
  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  * the basic fbdev interfaces, is derived in part from the radeonfb and
@@ -182,6 +183,7 @@ static struct pci_device_id intelfb_pci_
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_865G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_865G },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_915G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_915G },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_915GM, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_915GM },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_945G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_945G },
 	{ 0, }
 };
 
@@ -546,11 +548,10 @@ intelfb_pci_register(struct pci_dev *pde
 
 	/* Set base addresses. */
 	if ((ent->device == PCI_DEVICE_ID_INTEL_915G) ||
-			(ent->device == PCI_DEVICE_ID_INTEL_915GM)) {
+	    (ent->device == PCI_DEVICE_ID_INTEL_915GM) ||
+	    (ent->device == PCI_DEVICE_ID_INTEL_945G)) {
 		aperture_bar = 2;
 		mmio_bar = 0;
-		/* Disable HW cursor on 915G/M (not implemented yet) */
-		hwcursor = 0;
 	}
 	dinfo->aperture.physical = pci_resource_start(pdev, aperture_bar);
 	dinfo->aperture.size     = pci_resource_len(pdev, aperture_bar);
@@ -584,8 +585,7 @@ intelfb_pci_register(struct pci_dev *pde
 	/* Get the chipset info. */
 	dinfo->pci_chipset = pdev->device;
 
-	if (intelfbhw_get_chipset(pdev, &dinfo->name, &dinfo->chipset,
-				  &dinfo->mobile)) {
+	if (intelfbhw_get_chipset(pdev, dinfo)) {
 		cleanup(dinfo);
 		return -ENODEV;
 	}
@@ -1467,7 +1467,7 @@ static int
 intelfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 {
         struct intelfb_info *dinfo = GET_DINFO(info);
-
+	int ret;
 #if VERBOSE > 0
 	DBG_MSG("intelfb_cursor\n");
 #endif
@@ -1478,7 +1478,12 @@ intelfb_cursor(struct fb_info *info, str
 	intelfbhw_cursor_hide(dinfo);
 
 	/* If XFree killed the cursor - restore it */
-	if (INREG(CURSOR_A_BASEADDR) != dinfo->cursor.offset << 12) {
+	if (dinfo->mobile || IS_I9xx(dinfo))
+	  ret = (INREG(CURSOR_A_BASEADDR) != dinfo->cursor.physical);
+	else
+	  ret = (INREG(CURSOR_A_BASEADDR) != dinfo->cursor.offset << 12);
+
+	if (ret) {
 		u32 fg, bg;
 
 		DBG_MSG("the cursor was killed - restore it !!\n");
diff --git a/drivers/video/intelfb/intelfbhw.c b/drivers/video/intelfb/intelfbhw.c
index 624c4bc..92bdde8 100644
--- a/drivers/video/intelfb/intelfbhw.c
+++ b/drivers/video/intelfb/intelfbhw.c
@@ -40,68 +40,99 @@
 #include "intelfb.h"
 #include "intelfbhw.h"
 
+struct pll_min_max {
+	int min_m, max_m;
+	int min_m1, max_m1;
+	int min_m2, max_m2;
+	int min_n, max_n;
+	int min_p, max_p;
+	int min_p1, max_p1;
+	int min_vco_freq, max_vco_freq;
+	int p_transition_clock;
+	int p_inc_lo, p_inc_hi;
+};
+
+#define PLLS_I8xx 0
+#define PLLS_I9xx 1
+#define PLLS_MAX 2
+
+struct pll_min_max plls[PLLS_MAX] = {
+	{ 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 4, 22 }, //I8xx
+	{  75, 120, 10, 20, 5, 9, 4,  7, 5, 80, 1, 8, 930000, 2800000, 200000, 10, 5 }  //I9xx
+};
+
 int
-intelfbhw_get_chipset(struct pci_dev *pdev, const char **name, int *chipset,
-		      int *mobile)
+intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
 {
 	u32 tmp;
-
-	if (!pdev || !name || !chipset || !mobile)
+	if (!pdev || !dinfo)
 		return 1;
 
 	switch (pdev->device) {
 	case PCI_DEVICE_ID_INTEL_830M:
-		*name = "Intel(R) 830M";
-		*chipset = INTEL_830M;
-		*mobile = 1;
+		dinfo->name = "Intel(R) 830M";
+		dinfo->chipset = INTEL_830M;
+		dinfo->mobile = 1;
+		dinfo->pll_index = PLLS_I8xx;
 		return 0;
 	case PCI_DEVICE_ID_INTEL_845G:
-		*name = "Intel(R) 845G";
-		*chipset = INTEL_845G;
-		*mobile = 0;
+		dinfo->name = "Intel(R) 845G";
+		dinfo->chipset = INTEL_845G;
+		dinfo->mobile = 0;
+		dinfo->pll_index = PLLS_I8xx;
 		return 0;
 	case PCI_DEVICE_ID_INTEL_85XGM:
 		tmp = 0;
-		*mobile = 1;
+		dinfo->mobile = 1;
+		dinfo->pll_index = PLLS_I8xx;
 		pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
 		switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
 			INTEL_85X_VARIANT_MASK) {
 		case INTEL_VAR_855GME:
-			*name = "Intel(R) 855GME";
-			*chipset = INTEL_855GME;
+			dinfo->name = "Intel(R) 855GME";
+			dinfo->chipset = INTEL_855GME;
 			return 0;
 		case INTEL_VAR_855GM:
-			*name = "Intel(R) 855GM";
-			*chipset = INTEL_855GM;
+			dinfo->name = "Intel(R) 855GM";
+			dinfo->chipset = INTEL_855GM;
 			return 0;
 		case INTEL_VAR_852GME:
-			*name = "Intel(R) 852GME";
-			*chipset = INTEL_852GME;
+			dinfo->name = "Intel(R) 852GME";
+			dinfo->chipset = INTEL_852GME;
 			return 0;
 		case INTEL_VAR_852GM:
-			*name = "Intel(R) 852GM";
-			*chipset = INTEL_852GM;
+			dinfo->name = "Intel(R) 852GM";
+			dinfo->chipset = INTEL_852GM;
 			return 0;
 		default:
-			*name = "Intel(R) 852GM/855GM";
-			*chipset = INTEL_85XGM;
+			dinfo->name = "Intel(R) 852GM/855GM";
+			dinfo->chipset = INTEL_85XGM;
 			return 0;
 		}
 		break;
 	case PCI_DEVICE_ID_INTEL_865G:
-		*name = "Intel(R) 865G";
-		*chipset = INTEL_865G;
-		*mobile = 0;
+		dinfo->name = "Intel(R) 865G";
+		dinfo->chipset = INTEL_865G;
+		dinfo->mobile = 0;
+		dinfo->pll_index = PLLS_I8xx;
 		return 0;
 	case PCI_DEVICE_ID_INTEL_915G:
-		*name = "Intel(R) 915G";
-		*chipset = INTEL_915G;
-		*mobile = 0;
+		dinfo->name = "Intel(R) 915G";
+		dinfo->chipset = INTEL_915G;
+		dinfo->mobile = 0;
+		dinfo->pll_index = PLLS_I9xx;
 		return 0;
 	case PCI_DEVICE_ID_INTEL_915GM:
-		*name = "Intel(R) 915GM";
-		*chipset = INTEL_915GM;
-		*mobile = 1;
+		dinfo->name = "Intel(R) 915GM";
+		dinfo->chipset = INTEL_915GM;
+		dinfo->mobile = 1;
+		dinfo->pll_index = PLLS_I9xx;
+		return 0;
+	case PCI_DEVICE_ID_INTEL_945G:
+		dinfo->name = "Intel(R) 945G";
+		dinfo->chipset = INTEL_945G;
+		dinfo->mobile = 0;
+		dinfo->pll_index = PLLS_I9xx;
 		return 0;
 	default:
 		return 1;
@@ -529,14 +560,37 @@ intelfbhw_read_hw_state(struct intelfb_i
 }
 
 
+static int calc_vclock3(int index, int m, int n, int p)
+{
+	if (p == 0 || n == 0)
+		return 0;
+	return PLL_REFCLK * m / n / p;
+}
+		       
+static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
+{
+	switch(index)
+	{
+	case PLLS_I9xx:
+		if (p1 == 0)
+			return 0;
+		return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
+			 ((p1)) * (p2 ? 10 : 5)));
+	case PLLS_I8xx:
+	default:
+		return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / 
+			 ((p1+2) * (1 << (p2 + 1)))));
+	}
+}
+
 void
 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 {
 #if REGDUMP
 	int i, m1, m2, n, p1, p2;
-
+	int index = dinfo->pll_index;
 	DBG_MSG("intelfbhw_print_hw_state\n");
-
+	
 	if (!hw || !dinfo)
 		return;
 	/* Read in as much of the HW state as possible. */
@@ -553,9 +607,10 @@ intelfbhw_print_hw_state(struct intelfb_
 		p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
 	p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
 	printk("	VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
-		m1, m2, n, p1, p2);
-	printk("	VGA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
-
+	       m1, m2, n, p1, p2);
+	printk("	VGA0: clock is %d\n", 
+	       calc_vclock(index, m1, m2, n, p1, p2));
+	
 	n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 	m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 	m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
@@ -565,16 +620,16 @@ intelfbhw_print_hw_state(struct intelfb_
 		p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
 	p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
 	printk("	VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
-		m1, m2, n, p1, p2);
-	printk("	VGA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
-
+	       m1, m2, n, p1, p2);
+	printk("	VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
+	
 	printk("	DPLL_A:			0x%08x\n", hw->dpll_a);
 	printk("	DPLL_B:			0x%08x\n", hw->dpll_b);
 	printk("	FPA0:			0x%08x\n", hw->fpa0);
 	printk("	FPA1:			0x%08x\n", hw->fpa1);
 	printk("	FPB0:			0x%08x\n", hw->fpb0);
 	printk("	FPB1:			0x%08x\n", hw->fpb1);
-
+	
 	n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 	m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 	m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
@@ -584,9 +639,9 @@ intelfbhw_print_hw_state(struct intelfb_
 		p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 	p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 	printk("	PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
-		m1, m2, n, p1, p2);
-	printk("	PLLA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
-
+	       m1, m2, n, p1, p2);
+	printk("	PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
+	
 	n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 	m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 	m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
@@ -596,16 +651,16 @@ intelfbhw_print_hw_state(struct intelfb_
 		p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 	p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 	printk("	PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
-		m1, m2, n, p1, p2);
-	printk("	PLLA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
-
+	       m1, m2, n, p1, p2);
+	printk("	PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
+	
 #if 0
 	printk("	PALETTE_A:\n");
 	for (i = 0; i < PALETTE_8_ENTRIES)
-		printk("	%3d:	0x%08x\n", i, hw->palette_a[i];
+		printk("	%3d:	0x%08x\n", i, hw->palette_a[i]);
 	printk("	PALETTE_B:\n");
 	for (i = 0; i < PALETTE_8_ENTRIES)
-		printk("	%3d:	0x%08x\n", i, hw->palette_b[i];
+		printk("	%3d:	0x%08x\n", i, hw->palette_b[i]);
 #endif
 
 	printk("	HTOTAL_A:		0x%08x\n", hw->htotal_a);
@@ -680,12 +735,12 @@ intelfbhw_print_hw_state(struct intelfb_
 	}
 	for (i = 0; i < 3; i++) {
 		printk("	SWF3%d			0x%08x\n", i,
-			hw->swf3x[i]);
+		       hw->swf3x[i]);
 	}
 	for (i = 0; i < 8; i++)
 		printk("	FENCE%d			0x%08x\n", i,
-			hw->fence[i]);
-
+		       hw->fence[i]);
+		       
 	printk("	INSTPM			0x%08x\n", hw->instpm);
 	printk("	MEM_MODE		0x%08x\n", hw->mem_mode);
 	printk("	FW_BLC_0		0x%08x\n", hw->fw_blc_0);
@@ -695,57 +750,87 @@ intelfbhw_print_hw_state(struct intelfb_
 #endif
 }
 
+	       
+
 /* Split the M parameter into M1 and M2. */
 static int
-splitm(unsigned int m, unsigned int *retm1, unsigned int *retm2)
+splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 {
 	int m1, m2;
-
-	m1 = (m - 2 - (MIN_M2 + MAX_M2) / 2) / 5 - 2;
-	if (m1 < MIN_M1)
-		m1 = MIN_M1;
-	if (m1 > MAX_M1)
-		m1 = MAX_M1;
-	m2 = m - 5 * (m1 + 2) - 2;
-	if (m2 < MIN_M2 || m2 > MAX_M2 || m2 >= m1) {
-		return 1;
-	} else {
+	int testm;
+	/* no point optimising too much - brute force m */
+	for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++)
+	{
+	  for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++)
+	  {
+	    testm  = ( 5 * ( m1 + 2 )) + (m2 + 2);
+	    if (testm == m)
+	    {
 		*retm1 = (unsigned int)m1;
-		*retm2 = (unsigned int)m2;
+		*retm2 = (unsigned int)m2;	      
 		return 0;
+	    }
+	  }
 	}
+	return 1;
 }
 
 /* Split the P parameter into P1 and P2. */
 static int
-splitp(unsigned int p, unsigned int *retp1, unsigned int *retp2)
+splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 {
 	int p1, p2;
 
-	if (p % 4 == 0)
-		p2 = 1;
-	else
-		p2 = 0;
-	p1 = (p / (1 << (p2 + 1))) - 2;
-	if (p % 4 == 0 && p1 < MIN_P1) {
-		p2 = 0;
-		p1 = (p / (1 << (p2 + 1))) - 2;
-	}
-	if (p1  < MIN_P1 || p1 > MAX_P1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
-		return 1;
-	} else {
+	if (index == PLLS_I9xx)
+	{
+		switch (p) {
+		case 10:
+			p1 = 2;
+			p2 = 0;
+			break;
+		case 20:
+			p1 = 1;
+			p2 = 0;
+			break;
+		default:
+			p1 = (p / 10) + 1;
+			p2 = 0;
+			break;
+		}
+		
 		*retp1 = (unsigned int)p1;
 		*retp2 = (unsigned int)p2;
 		return 0;
 	}
+
+	if (index == PLLS_I8xx)
+	{
+		if (p % 4 == 0)
+			p2 = 1;
+		else
+			p2 = 0;
+		p1 = (p / (1 << (p2 + 1))) - 2;
+		if (p % 4 == 0 && p1 < plls[index].min_p1) {
+			p2 = 0;
+			p1 = (p / (1 << (p2 + 1))) - 2;
+		}
+		if (p1  < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
+			return 1;
+		} else {
+			*retp1 = (unsigned int)p1;
+			*retp2 = (unsigned int)p2;
+			return 0;
+		}
+	}
+	return 1;
 }
 
 static int
-calc_pll_params(int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
+calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 		u32 *retp2, u32 *retclock)
 {
-	u32 m1, m2, n, p1, p2, n1;
-	u32 f_vco, p, p_best = 0, m, f_out;
+	u32 m1, m2, n, p1, p2, n1, testm;
+	u32 f_vco, p, p_best = 0, m, f_out = 0;
 	u32 err_max, err_target, err_best = 10000000;
 	u32 n_best = 0, m_best = 0, f_best, f_err;
 	u32 p_min, p_max, p_inc, div_min, div_max;
@@ -756,58 +841,73 @@ calc_pll_params(int clock, u32 *retm1, u
 
 	DBG_MSG("Clock is %d\n", clock);
 
-	div_max = MAX_VCO_FREQ / clock;
-	div_min = ROUND_UP_TO(MIN_VCO_FREQ, clock) / clock;
+	div_max = plls[index].max_vco_freq / clock;
+	if (index == PLLS_I9xx)
+		div_min = 5;
+	else
+		div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
 
-	if (clock <= P_TRANSITION_CLOCK)
-		p_inc = 4;
+	if (clock <= plls[index].p_transition_clock)
+		p_inc = plls[index].p_inc_lo;
 	else
-		p_inc = 2;
+		p_inc = plls[index].p_inc_hi;
 	p_min = ROUND_UP_TO(div_min, p_inc);
 	p_max = ROUND_DOWN_TO(div_max, p_inc);
-	if (p_min < MIN_P)
-		p_min = 4;
-	if (p_max > MAX_P)
-		p_max = 128;
+	if (p_min < plls[index].min_p)
+		p_min = plls[index].min_p;
+	if (p_max > plls[index].max_p)
+		p_max = plls[index].max_p;
+
+	if (clock < PLL_REFCLK && index==PLLS_I9xx)
+	{
+	  p_min = 10;
+	  p_max = 20;
+	  /* this makes 640x480 work it really shouldn't 
+	     - SOMEONE WITHOUT DOCS WOZ HERE */
+	  if (clock < 30000)
+	    clock *= 4;
+	}
 
 	DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 
 	p = p_min;
 	do {
-		if (splitp(p, &p1, &p2)) {
+		if (splitp(index, p, &p1, &p2)) {
 			WRN_MSG("cannot split p = %d\n", p);
 			p += p_inc;
 			continue;
 		}
-		n = MIN_N;
+		n = plls[index].min_n;
 		f_vco = clock * p;
 
 		do {
 			m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
-			if (m < MIN_M)
-				m = MIN_M;
-			if (m > MAX_M)
-				m = MAX_M;
-			f_out = CALC_VCLOCK3(m, n, p);
-			if (splitm(m, &m1, &m2)) {
-				WRN_MSG("cannot split m = %d\n", m);
-				n++;
-				continue;
-			}
-			if (clock > f_out)
-				f_err = clock - f_out;
-			else
-				f_err = f_out - clock;
-
-			if (f_err < err_best) {
-				m_best = m;
-				n_best = n;
-				p_best = p;
-				f_best = f_out;
-				err_best = f_err;
+			if (m < plls[index].min_m)
+				m = plls[index].min_m + 1;
+			if (m > plls[index].max_m)
+				m = plls[index].max_m - 1;
+			for (testm = m - 1; testm <= m; testm++) {
+				f_out = calc_vclock3(index, m, n, p);
+				if (splitm(index, m, &m1, &m2)) {
+					WRN_MSG("cannot split m = %d\n", m);
+					n++;
+					continue;
+				}
+				if (clock > f_out)
+					f_err = clock - f_out;
+				else/* slightly bias the error for bigger clocks */
+					f_err = f_out - clock + 1;
+				
+				if (f_err < err_best) {
+					m_best = m;
+					n_best = n;
+					p_best = p;
+					f_best = f_out;
+					err_best = f_err;
+				}
 			}
 			n++;
-		} while ((n <= MAX_N) && (f_out >= clock));
+		} while ((n <= plls[index].max_n) && (f_out >= clock));
 		p += p_inc;
 	} while ((p <= p_max));
 
@@ -818,21 +918,22 @@ calc_pll_params(int clock, u32 *retm1, u
 	m = m_best;
 	n = n_best;
 	p = p_best;
-	splitm(m, &m1, &m2);
-	splitp(p, &p1, &p2);
+	splitm(index, m, &m1, &m2);
+	splitp(index, p, &p1, &p2);
 	n1 = n - 2;
 
 	DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 		"f: %d (%d), VCO: %d\n",
 		m, m1, m2, n, n1, p, p1, p2,
-		CALC_VCLOCK3(m, n, p), CALC_VCLOCK(m1, m2, n1, p1, p2),
-		CALC_VCLOCK3(m, n, p) * p);
+		calc_vclock3(index, m, n, p), 
+		calc_vclock(index, m1, m2, n1, p1, p2),
+		calc_vclock3(index, m, n, p) * p);
 	*retm1 = m1;
 	*retm2 = m2;
 	*retn = n1;
 	*retp1 = p1;
 	*retp2 = p2;
-	*retclock = CALC_VCLOCK(m1, m2, n1, p1, p2);
+	*retclock = calc_vclock(index, m1, m2, n1, p1, p2);
 
 	return 0;
 }
@@ -929,7 +1030,7 @@ intelfbhw_mode_to_hw(struct intelfb_info
 	/* Desired clock in kHz */
 	clock_target = 1000000000 / var->pixclock;
 
-	if (calc_pll_params(clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
+	if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
 		WRN_MSG("calc_pll_params failed\n");
 		return 1;
 	}
@@ -1087,6 +1188,7 @@ intelfbhw_program_mode(struct intelfb_in
 	u32 hsync_reg, htotal_reg, hblank_reg;
 	u32 vsync_reg, vtotal_reg, vblank_reg;
 	u32 src_size_reg;
+	u32 count, tmp_val[3];
 
 	/* Assume single pipe, display plane A, analog CRT. */
 
@@ -1155,6 +1257,28 @@ intelfbhw_program_mode(struct intelfb_in
 		src_size_reg = SRC_SIZE_A;
 	}
 
+	/* turn off pipe */
+	tmp = INREG(pipe_conf_reg);
+	tmp &= ~PIPECONF_ENABLE;
+	OUTREG(pipe_conf_reg, tmp);
+	
+	count = 0;
+	do{
+	  tmp_val[count%3] = INREG(0x70000);
+	  if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
+	    break;
+	  count++;
+	  udelay(1);
+	  if (count % 200 == 0)
+	  {
+	    tmp = INREG(pipe_conf_reg);
+	    tmp &= ~PIPECONF_ENABLE;
+	    OUTREG(pipe_conf_reg, tmp);
+	  }
+	} while(count < 2000);
+
+	OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
+
 	/* Disable planes A and B. */
 	tmp = INREG(DSPACNTR);
 	tmp &= ~DISPPLANE_PLANE_ENABLE;
@@ -1172,10 +1296,8 @@ intelfbhw_program_mode(struct intelfb_in
 	tmp |= ADPA_DPMS_D3;
 	OUTREG(ADPA, tmp);
 
-	/* turn off pipe */
-	tmp = INREG(pipe_conf_reg);
-	tmp &= ~PIPECONF_ENABLE;
-	OUTREG(pipe_conf_reg, tmp);
+	/* do some funky magic - xyzzy */
+	OUTREG(0x61204, 0xabcd0000);
 
 	/* turn off PLL */
 	tmp = INREG(dpll_reg);
@@ -1187,26 +1309,30 @@ intelfbhw_program_mode(struct intelfb_in
 	OUTREG(fp0_reg, *fp0);
 	OUTREG(fp1_reg, *fp1);
 
-	/* Set pipe parameters */
-	OUTREG(hsync_reg, *hs);
-	OUTREG(hblank_reg, *hb);
-	OUTREG(htotal_reg, *ht);
-	OUTREG(vsync_reg, *vs);
-	OUTREG(vblank_reg, *vb);
-	OUTREG(vtotal_reg, *vt);
-	OUTREG(src_size_reg, *ss);
+	/* Enable PLL */
+	tmp = INREG(dpll_reg);
+	tmp |= DPLL_VCO_ENABLE;
+	OUTREG(dpll_reg, tmp);
 
 	/* Set DVOs B/C */
 	OUTREG(DVOB, hw->dvob);
 	OUTREG(DVOC, hw->dvoc);
 
+	/* undo funky magic */
+	OUTREG(0x61204, 0x00000000);
+
 	/* Set ADPA */
+	OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
 	OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
 
-	/* Enable PLL */
-	tmp = INREG(dpll_reg);
-	tmp |= DPLL_VCO_ENABLE;
-	OUTREG(dpll_reg, tmp);
+	/* Set pipe parameters */
+	OUTREG(hsync_reg, *hs);
+	OUTREG(hblank_reg, *hb);
+	OUTREG(htotal_reg, *ht);
+	OUTREG(vsync_reg, *vs);
+	OUTREG(vblank_reg, *vb);
+	OUTREG(vtotal_reg, *vt);
+	OUTREG(src_size_reg, *ss);
 
 	/* Enable pipe */
 	OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
@@ -1616,7 +1742,7 @@ intelfbhw_cursor_init(struct intelfb_inf
 	DBG_MSG("intelfbhw_cursor_init\n");
 #endif
 
-	if (dinfo->mobile) {
+	if (dinfo->mobile || IS_I9xx(dinfo)) {
 		if (!dinfo->cursor.physical)
 			return;
 		tmp = INREG(CURSOR_A_CONTROL);
@@ -1649,7 +1775,7 @@ intelfbhw_cursor_hide(struct intelfb_inf
 #endif
 
 	dinfo->cursor_on = 0;
-	if (dinfo->mobile) {
+	if (dinfo->mobile || IS_I9xx(dinfo)) {
 		if (!dinfo->cursor.physical)
 			return;
 		tmp = INREG(CURSOR_A_CONTROL);
@@ -1679,7 +1805,7 @@ intelfbhw_cursor_show(struct intelfb_inf
 	if (dinfo->cursor_blanked)
 		return;
 
-	if (dinfo->mobile) {
+	if (dinfo->mobile || IS_I9xx(dinfo)) {
 		if (!dinfo->cursor.physical)
 			return;
 		tmp = INREG(CURSOR_A_CONTROL);
@@ -1713,6 +1839,10 @@ intelfbhw_cursor_setpos(struct intelfb_i
 	tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
 	      ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
 	OUTREG(CURSOR_A_POSITION, tmp);
+
+	if (IS_I9xx(dinfo)) {
+		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
+	}
 }
 
 void
diff --git a/drivers/video/intelfb/intelfbhw.h b/drivers/video/intelfb/intelfbhw.h
index ba19201..a3ec8f9 100644
--- a/drivers/video/intelfb/intelfbhw.h
+++ b/drivers/video/intelfb/intelfbhw.h
@@ -155,29 +155,8 @@
 /* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */
 /* Clock values are in units of kHz */
 #define PLL_REFCLK		48000
-#define MIN_VCO_FREQ		930000
-#define MAX_VCO_FREQ		1400000
 #define MIN_CLOCK		25000
 #define MAX_CLOCK		350000
-#define P_TRANSITION_CLOCK	165000
-#define MIN_M			108
-#define MAX_M			140
-#define MIN_M1			18
-#define MAX_M1			26
-#define MIN_M2			6
-#define MAX_M2			16
-#define MIN_P			4
-#define MAX_P			128
-#define MIN_P1			0
-#define MAX_P1			31
-#define MIN_N			3
-#define MAX_N			16
-
-#define CALC_VCLOCK(m1, m2, n, p1, p2) \
-        ((PLL_REFCLK * (5 * ((m1) + 2) + ((m2) + 2)) / ((n) + 2)) / \
-        (((p1) + 2) * (1 << (p2 + 1))))
-
-#define CALC_VCLOCK3(m, n, p)	((PLL_REFCLK * (m) / (n)) / (p))
 
 /* Two pipes */
 #define PIPE_A			0
@@ -522,8 +501,7 @@
 
 
 /* function protoypes */
-extern int intelfbhw_get_chipset(struct pci_dev *pdev, const char **name,
-				 int *chipset, int *mobile);
+extern int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo);
 extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 				int *stolen_size);
 extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo);

Re: [Linux-fbdev-devel] [PATCH] [git tree] Intel i9xx support for intelfb

[Antonino Daplas]

On 3/23/06, Dave Airlie <airlied@gmail.com> wrote:
> This patch adds support for i915G, i915GM and i945G to the intelfb
> driver in the kernel.
>
> It comes from work done by me on an X.org driver to support some
> non-VBE modesetting.
>
> This code isn't perfect but I've got no documentation so I cannot
> answer some questions on what exactly is going on just yet...

Better than nothing, and if it works for digital displays, then that
would be great.

>
> The code is also available in the i915fb branch or
> git://git.kernel.org/pub/scm/linux/kernel/git/airlied/intelfb-2.6
>
> It may need more testing on the i945G, and I think adding i945GM
> support might only be a few lines of code...
>
> Is there a framebuffer git tree this could go in?

There's no git tree for the framebuffer layer, I just send updates
directly to akpm. Andrew?

Tony

Re: [PATCH] [git tree] Intel i9xx support for intelfb

[Andrew Morton]

"Antonino Daplas" <adaplas@gmail.com> wrote:
>
> > The code is also available in the i915fb branch or
> > git://git.kernel.org/pub/scm/linux/kernel/git/airlied/intelfb-2.6
> >
> > It may need more testing on the i945G, and I think adding i945GM
> > support might only be a few lines of code...
> >
> > Is there a framebuffer git tree this could go in?
> 
> There's no git tree for the framebuffer layer, I just send updates
> directly to akpm. Andrew?
> 

I added Dave's git tree to the -mm lineup.  Haven't tried fetching it
it yet though.

If you're OK with it all then Dave can ask Linus to pull it direct when
he's ready.


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Re: [PATCH] [git tree] Intel i9xx support for intelfb

[Dave Airlie]

> >
> > This code isn't perfect but I've got no documentation so I cannot
> > answer some questions on what exactly is going on just yet...
>
> Better than nothing, and if it works for digital displays, then that
> would be great.

It doesn't support LVDS or DVI yet but I'm hoping to make it go in
that direction, I've no LVDS h/w, and some chipsets have it integrated
and some don't, but this is a better basis for future work, and I'll
have no problems keeping it updated with fixes as they come from the
X.org driver... I'd like to get at least LVDS support working for
laptop users with these chipsets, getting DVI working is a bit more
work as there are external chips that need to be driven over i2c, so
I'll need to at least add i2c support to the i8xx driver. (I noticed
Sylvain has done some of this work before)..... I'd like to expose i2c
buses to userspace anyways....

> There's no git tree for the framebuffer layer, I just send updates
> directly to akpm. Andrew?
>

I'd like to keep the git history if possible, so maybe we can pull
this tree into -mm and I can get it pulled by Linus later.

Regards,
Dave


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Re: [Linux-fbdev-devel] [PATCH] [git tree] Intel i9xx support for intelfb

[Antonino A. Daplas]

Dave Airlie wrote:

> laptop users with these chipsets, getting DVI working is a bit more
> work as there are external chips that need to be driven over i2c, so
> I'll need to at least add i2c support to the i8xx driver. (I noticed
> Sylvain has done some of this work before)..... I'd like to expose i2c
> buses to userspace anyways....

Someone mentioned (I think it was Nicholas Boichat) that the i2c code
of i810fb works for intelfb too, but I cannot verify that.

Tony

Re: [Linux-fbdev-devel] [PATCH] [git tree] Intel i9xx support for intelfb

[Sylvain Meyer]

        Sorry for my very long silence.

For i2c support. I've done it to have a workable tv-out on my hardware. 
It was the main reason  why i ported the driver to kernels 2.6 as i use 
my computer as a set-top-box only connected to a tv. I've it on my own 
tree (very old).
I can send you the code. I did it in a way not accepted by kernel 
reviewers as my tv driver (for chrontel ch7011 chipset) is all in kernel 
space. But it can be a base for a better scheme.

Regards
Sylvain

Dave Airlie a écrit:

>>>This code isn't perfect but I've got no documentation so I cannot
>>>answer some questions on what exactly is going on just yet...
>>>      
>>>
>>Better than nothing, and if it works for digital displays, then that
>>would be great.
>>    
>>
>
>It doesn't support LVDS or DVI yet but I'm hoping to make it go in
>that direction, I've no LVDS h/w, and some chipsets have it integrated
>and some don't, but this is a better basis for future work, and I'll
>have no problems keeping it updated with fixes as they come from the
>X.org driver... I'd like to get at least LVDS support working for
>laptop users with these chipsets, getting DVI working is a bit more
>work as there are external chips that need to be driven over i2c, so
>I'll need to at least add i2c support to the i8xx driver. (I noticed
>Sylvain has done some of this work before)..... I'd like to expose i2c
>buses to userspace anyways....
>
>  
>
>>There's no git tree for the framebuffer layer, I just send updates
>>directly to akpm. Andrew?
>>
>>    
>>
>
>I'd like to keep the git history if possible, so maybe we can pull
>this tree into -mm and I can get it pulled by Linus later.
>
>Regards,
>Dave
>
>
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>_______________________________________________
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>Linux-fbdev-devel@lists.sourceforge.net
>https://lists.sourceforge.net/lists/listinfo/linux-fbdev-devel
>
>  
>

Re: [Linux-fbdev-devel] [PATCH] [git tree] Intel i9xx support for intelfb

[Dave Airlie]

On 3/24/06, Sylvain Meyer <sylvain.meyer@worldonline.fr> wrote:
>         Sorry for my very long silence.
>
> For i2c support. I've done it to have a workable tv-out on my hardware.
> It was the main reason  why i ported the driver to kernels 2.6 as i use
> my computer as a set-top-box only connected to a tv. I've it on my own
> tree (very old).
> I can send you the code. I did it in a way not accepted by kernel
> reviewers as my tv driver (for chrontel ch7011 chipset) is all in kernel
> space. But it can be a base for a better scheme.

I actually have your code already, I picked it up on directfb-dev
quite a while back :-)

The i810 i2c code is nearly exactly the same as intelfb, they use the
same scheme, i9xx also support GMBUS, which means the chipset takes
over the bitbanging, you just give it a byte count and register... but
I'm not having the greatest luck reverse engineering it, hopefully
Intel will tell us how it might work at some point..

Im trying to figure out the architecture for moving a lot of stuff
into userspace, but keeping enough in kernel for people to do what
works now..

Dave.

Re: [PATCH] [git tree] Intel i9xx support for intelfb

[Sylvain Meyer]

        Not for all the i2c ports. I will post my code tomorrow.

Regards
Sylvain

Antonino A. Daplas a écrit:

>Dave Airlie wrote:
>
>  
>
>>laptop users with these chipsets, getting DVI working is a bit more
>>work as there are external chips that need to be driven over i2c, so
>>I'll need to at least add i2c support to the i8xx driver. (I noticed
>>Sylvain has done some of this work before)..... I'd like to expose i2c
>>buses to userspace anyways....
>>    
>>
>
>Someone mentioned (I think it was Nicholas Boichat) that the i2c code
>of i810fb works for intelfb too, but I cannot verify that.
>
>Tony
>
>  
>





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Re: [Linux-fbdev-devel] [PATCH] [git tree] Intel i9xx support for intelfb

[Sylvain Meyer]

 Dave Airlie a écrit:

>On 3/24/06, Sylvain Meyer <sylvain.meyer@worldonline.fr> wrote:
>  
>
>>        Sorry for my very long silence.
>>
>>For i2c support. I've done it to have a workable tv-out on my hardware.
>>It was the main reason  why i ported the driver to kernels 2.6 as i use
>>my computer as a set-top-box only connected to a tv. I've it on my own
>>tree (very old).
>>I can send you the code. I did it in a way not accepted by kernel
>>reviewers as my tv driver (for chrontel ch7011 chipset) is all in kernel
>>space. But it can be a base for a better scheme.
>>    
>>
>
>I actually have your code already, I picked it up on directfb-dev
>quite a while back :-)
>
>  
>
        Ok. Not needed then. No change so far.

Sylvain

Re: [PATCH] [git tree] Intel i9xx support for intelfb

[Dave Airlie]

On 3/24/06, Sylvain Meyer <sylvain.meyer@worldonline.fr> wrote:
>  Dave Airlie a écrit:
>
> >On 3/24/06, Sylvain Meyer <sylvain.meyer@worldonline.fr> wrote:
> >
> >
> >>        Sorry for my very long silence.
> >>
> >>For i2c support. I've done it to have a workable tv-out on my hardware.
> >>It was the main reason  why i ported the driver to kernels 2.6 as i use
> >>my computer as a set-top-box only connected to a tv. I've it on my own
> >>tree (very old).
> >>I can send you the code. I did it in a way not accepted by kernel
> >>reviewers as my tv driver (for chrontel ch7011 chipset) is all in kernel
> >>space. But it can be a base for a better scheme.
> >>
> >>
> >
> >I actually have your code already, I picked it up on directfb-dev
> >quite a while back :-)
> >
> >
> >
>         Ok. Not needed then. No change so far.
>
> Sylvain
>
>
>
>
>
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