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From: "Krzysztof Helt" <krzysztof.h1@wp.pl>
To: linux-fbdev-devel <linux-fbdev-devel@lists.sourceforge.net>
Cc: ben-linux@fluff.org
Subject: [PATCH] s3c2410fb: byte ordering fixes
Date: Tue, 14 Aug 2007 18:26:38 +0200	[thread overview]
Message-ID: <46c1d7beb3dd8@wp.pl> (raw)

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From: Krzysztof Helt <krzysztof.h1@wp.pl>

This patch sets correct bits related to the byte ordering
of the framebuffer. This was tested on little endian kernel
only. The big endian kernel may require different settings.

The patch also adds 32 bpp mode which is called 24 bpp by
Samsung. One pixel takes 32 bits but only 24 bits are used
in this mode.

Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>

---

This patch requires all s3c2410fb patches sent to this list.

The patch was tested on iPAQ rx1950 (TFT display only).
The 1, 2 and 4 bpp modes do not work on little endian kernel
(wrong order of pixels in byte). 1bpp is not stable for
unknown reason.

diff -urp linux-2.6.23.old/drivers/video/s3c2410fb.c linux-2.6.
23/drivers/video/s3c2410fb.c
--- linux-2.6.23.old/drivers/video/s3c2410fb.c	2007-08-13 20:
21:57.000000000 +0200
+++ linux-2.6.23/drivers/video/s3c2410fb.c	2007-08-13 20:46:
18.000000000 +0200
@@ -270,8 +270,8 @@ static int s3c2410fb_check_var(struct fb
 			var->blue.length	= 5;
 		}
 		break;
-	case 24:
-		/* 24 bpp 888 */
+	case 32:
+		/* 24 bpp 888 and 8 dummy */
 		var->red.length		= 8;
 		var->red.offset		= 16;
 		var->green.length	= 8;
@@ -279,8 +279,6 @@ static int s3c2410fb_check_var(struct fb
 		var->blue.length	= 8;
 		var->blue.offset	= 0;
 		break;
-
-
 	}
 	return 0;
 }
@@ -379,11 +377,21 @@ static void s3c2410fb_calculate_tft_lcd_
 		break;
 	case 8:
 		regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
+		regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
+				 S3C2410_LCDCON5_FRM565;
+		regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 		break;
 	case 16:
 		regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
+		regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
+		regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
+		break;
+	case 32:
+		regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
+		regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
+				   S3C2410_LCDCON5_HWSWP |
+				   S3C2410_LCDCON5_BPP24BL);
 		break;
-
 	default:
 		/* invalid pixel depth */
 		dev_err(fbi->dev, "invalid bpp %d\n",
@@ -475,7 +483,9 @@ static int s3c2410fb_set_par(struct fb_i
 	struct fb_var_screeninfo *var = &info->var;
 
 	switch (var->bits_per_pixel) {
+	case 32:
 	case 16:
+	case 12:
 		info->fix.visual = FB_VISUAL_TRUECOLOR;
 		break;
 	case 1:


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From: Krzysztof Helt <krzysztof.h1@wp.pl>

This patch sets correct bits related to the byte ordering
of the framebuffer. This was tested on little endian kernel
only. The big endian kernel may require different settings.

The patch also adds 32 bpp mode which is called 24 bpp by
Samsung. One pixel takes 32 bits but only 24 bits are used
in this mode.

Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>

---

This patch requires all s3c2410fb patches sent to this list.

The patch was tested on iPAQ rx1950 (TFT display only).
The 1, 2 and 4 bpp modes do not work on little endian kernel
(wrong order of pixels in byte).

diff -urp linux-2.6.23.old/drivers/video/s3c2410fb.c linux-2.6.23/drivers/video/s3c2410fb.c
--- linux-2.6.23.old/drivers/video/s3c2410fb.c	2007-08-13 20:21:57.000000000 +0200
+++ linux-2.6.23/drivers/video/s3c2410fb.c	2007-08-13 20:46:18.000000000 +0200
@@ -270,8 +270,8 @@ static int s3c2410fb_check_var(struct fb
 			var->blue.length	= 5;
 		}
 		break;
-	case 24:
-		/* 24 bpp 888 */
+	case 32:
+		/* 24 bpp 888 and 8 dummy */
 		var->red.length		= 8;
 		var->red.offset		= 16;
 		var->green.length	= 8;
@@ -279,8 +279,6 @@ static int s3c2410fb_check_var(struct fb
 		var->blue.length	= 8;
 		var->blue.offset	= 0;
 		break;
-
-
 	}
 	return 0;
 }
@@ -379,11 +377,21 @@ static void s3c2410fb_calculate_tft_lcd_
 		break;
 	case 8:
 		regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
+		regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
+				 S3C2410_LCDCON5_FRM565;
+		regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 		break;
 	case 16:
 		regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
+		regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
+		regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
+		break;
+	case 32:
+		regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
+		regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
+				   S3C2410_LCDCON5_HWSWP |
+				   S3C2410_LCDCON5_BPP24BL);
 		break;
-
 	default:
 		/* invalid pixel depth */
 		dev_err(fbi->dev, "invalid bpp %d\n",
@@ -475,7 +483,9 @@ static int s3c2410fb_set_par(struct fb_i
 	struct fb_var_screeninfo *var = &info->var;
 
 	switch (var->bits_per_pixel) {
+	case 32:
 	case 16:
+	case 12:
 		info->fix.visual = FB_VISUAL_TRUECOLOR;
 		break;
 	case 1:

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             reply	other threads:[~2007-08-14 16:26 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-08-14 16:26 Krzysztof Helt [this message]
2007-09-09  9:28 ` [PATCH] s3c2410fb: byte ordering fixes Krzysztof Helt
2007-09-15  0:17   ` Antonino A. Daplas
2007-09-15  5:52     ` Krzysztof Helt
2007-09-15 23:17       ` Antonino A. Daplas
  -- strict thread matches above, loose matches on Subject: below --
2007-09-15 23:22 Antonino A. Daplas

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