* Seg fault on any FB write (Epson S1D13A04 on Coldfire running 2.6.25)
@ 2008-11-11 1:54 James Kimble
2008-11-11 9:57 ` Hinko Kocevar
2008-11-11 18:50 ` Seg fault on any FB write (Epson S1D13A04 on " Kristoffer Ericson
0 siblings, 2 replies; 18+ messages in thread
From: James Kimble @ 2008-11-11 1:54 UTC (permalink / raw)
To: linux-fbdev-devel
I've been working on porting the s1d13xxxfb driver from the latest
kernel from Freescale for Coldfire to work with the S1D13A04 chip. I was
able to get things working to the point that I do get a little TUX logo
up on the screen at boot up. Seemed like a good start but none of my
user space applications will work. I can open the /dev/fb0 device and
the data in the info structure is correct but if I try to write to any
register or area in the frame buffer (or write to the device at all) I
get a seg fault.
I had an earlier driver working with the 2.6.10 kernel with the same
hardware. The same application space program should work ( I would
think...) but I get the seg fault on the first write to fb0. I tried a
different memory location (ox4400 0000 to 0x7400 0000) for the CS
associated with the video chip, no difference. Permissions for
/dev/fb0 are "rw". No other process using fb0. This is really weird.
Any help or suggestions MUCH appreciated.
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04 on Coldfire running 2.6.25)
2008-11-11 1:54 Seg fault on any FB write (Epson S1D13A04 on Coldfire running 2.6.25) James Kimble
@ 2008-11-11 9:57 ` Hinko Kocevar
2008-11-11 14:50 ` Seg fault on any FB write (Epson S1D13A04on " jkimble
2008-11-11 18:50 ` Seg fault on any FB write (Epson S1D13A04 on " Kristoffer Ericson
1 sibling, 1 reply; 18+ messages in thread
From: Hinko Kocevar @ 2008-11-11 9:57 UTC (permalink / raw)
To: James Kimble; +Cc: linux-fbdev-devel
James Kimble wrote:
> I've been working on porting the s1d13xxxfb driver from the latest
> kernel from Freescale for Coldfire to work with the S1D13A04 chip. I was
> able to get things working to the point that I do get a little TUX logo
> up on the screen at boot up. Seemed like a good start but none of my
> user space applications will work. I can open the /dev/fb0 device and
> the data in the info structure is correct but if I try to write to any
> register or area in the frame buffer (or write to the device at all) I
> get a seg fault.
>
> I had an earlier driver working with the 2.6.10 kernel with the same
> hardware. The same application space program should work ( I would
> think...) but I get the seg fault on the first write to fb0. I tried a
> different memory location (ox4400 0000 to 0x7400 0000) for the CS
> associated with the video chip, no difference. Permissions for
> /dev/fb0 are "rw". No other process using fb0. This is really weird.
>
> Any help or suggestions MUCH appreciated.
>
You are probably not reserving and/or translating physical memory space
to virtual if you get a segfault on every access. Try cat /proc/iomem. Is
your device listed?
OTOH, a lot of arch specific code has probably changed since 2.6.10 -
2.6.25 that might not even be directly related to fb. Is your arch port
up to date?
Also you might post your fb driver and someone might spot the fault faster..
HTH,
HK
--
Hinko Kočevar, OSS developer
ČETRTA POT, d.o.o.
Planina 3, 4000 Kranj, SI EU
tel ++386 (0) 4 280 66 03
e-mail hinko.kocevar@cetrtapot.si
http www.cetrtapot.si
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04on Coldfire running 2.6.25)
2008-11-11 9:57 ` Hinko Kocevar
@ 2008-11-11 14:50 ` jkimble
2008-11-11 15:04 ` Hinko Kocevar
2008-11-11 15:06 ` jkimble
0 siblings, 2 replies; 18+ messages in thread
From: jkimble @ 2008-11-11 14:50 UTC (permalink / raw)
To: Hinko Kocevar; +Cc: linux-fbdev-devel
[-- Attachment #1: Type: text/plain, Size: 2228 bytes --]
> James Kimble wrote:
>> I've been working on porting the s1d13xxxfb driver from the latest
>> kernel from Freescale for Coldfire to work with the S1D13A04 chip. I was
>> able to get things working to the point that I do get a little TUX logo
>> up on the screen at boot up. Seemed like a good start but none of my
>> user space applications will work. I can open the /dev/fb0 device and
>> the data in the info structure is correct but if I try to write to any
>> register or area in the frame buffer (or write to the device at all) I
>> get a seg fault.
>>
>> I had an earlier driver working with the 2.6.10 kernel with the same
>> hardware. The same application space program should work ( I would
>> think...) but I get the seg fault on the first write to fb0. I tried a
>> different memory location (ox4400 0000 to 0x7400 0000) for the CS
>> associated with the video chip, no difference. Permissions for
>> /dev/fb0 are "rw". No other process using fb0. This is really weird.
>>
>> Any help or suggestions MUCH appreciated.
>>
>
> You are probably not reserving and/or translating physical memory space
> to virtual if you get a segfault on every access. Try cat /proc/iomem. Is
> your device listed?
>
> OTOH, a lot of arch specific code has probably changed since 2.6.10 -
> 2.6.25 that might not even be directly related to fb. Is your arch port
> up to date?
>
> Also you might post your fb driver and someone might spot the fault
> faster..
>
/proc/iomem shows:
74000000-74009000 : s1d13a04fb.0
74000000-74009000 : s1d13xxxfb regs
74040000-74068000 : s1d13a04fb.0
74040000-74068000 : s1d13xxxfb mem
f000070c-f000070c : spi-int-mask
f0000740-f000075f : spi-int-level
f0000a50-f0000a50 : spi-par
f0008a00-f0008ab8 : spi-module
f0008f00-f0008f20 : MCF548X-i2c
f000a000-f000a7ff : mcf548x-flexcan.0
f000a000-f000a7ff : mcf548x-flexcan
f000a800-f000afff : mcf548x-flexcan.1
f000a800-f000afff : mcf548x-flexcan
f0020000-f0033000 : fsl-sec1
fc000000-ffffffff : physmap-flash.0
Which looks fine to me. The s1d13 lines match the mapping I set up. I've
attached the driver. It is the driver for this family of chips that was
included in the Freescale release of the 2.6.25 kernel for Coldfire. It
includes my changes.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: s1d13xxxfb.c --]
[-- Type: text/x-csrc; name="s1d13xxxfb.c", Size: 28509 bytes --]
///////////////////////////////////////////////////////////////////////////////
//
// drivers/video/s1d13xxxfb.c
//
// (c) 2004 Simtec Electronics
// (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
//
// Driver for Epson S1D13xxx series framebuffer chips
//
// Adapted from:
// linux/drivers/video/skeletonfb.c
// linux/drivers/video/epson1355fb.c
// linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson)
//
// Note: Currently only tested on S1D13806 with 16bit CRT. As such, this
// driver might still contain some hardcoded bits relating to
// S1D13806.
//
// Making it work on other S1D13XXX chips should merely be a matter of adding
// a few switch()s, some missing glue here and there maybe, and split header
// files.
//
// TODO: - handle dual screen display (CRT and LCD at the same time).
// - check_var(), mode change, etc.
// - PM untested.
// - Accelerated interfaces.
// - Probably not SMP safe :)
//
// This file is subject to the terms and conditions of the GNU General Public
// License. See the file COPYING in the main directory of this archive for
// more details.
//
///////////////////////////////////////////////////////////////////////////////
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/mman.h>
#include <linux/fb.h>
#include <asm/io.h>
#include <video/s1d13xxxfb.h>
#include <video/palette.h>
#define S1D_DISPLAY_PCLK 0x5F5E10
typedef unsigned long S1D_VALUE;
#define PFX "s1d13xxxfb: "
#if 1
#define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0)
#else
#define dbg(fmt, args...) do { } while (0)
#endif
//
// Here we define the default struct fb_fix_screeninfo
//
static struct fb_fix_screeninfo __devinitdata s1d13xxxfb_fix =
{
.id = S1D_FBID,
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 0,
.ypanstep = 1,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
///////////////////////////////////////////////////////////////////////////////
//
// Read chip registers defined in /arch/<chip>/xxxx-devices.c
//
///////////////////////////////////////////////////////////////////////////////
static inline u32
s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u8 regno)
{
//return readb(par->regs + regno);
return ((S1D_VALUE*)par->regs)[regno/sizeof(S1D_VALUE)];
}
///////////////////////////////////////////////////////////////////////////////
//
// Write chip registers defined in /arch/<chip>/xxxx-devices.c
//
///////////////////////////////////////////////////////////////////////////////
static inline void
s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u8 regno, u32 value)
{
//writeb(value, par->regs + regno);
((S1D_VALUE*)par->regs)[regno/sizeof(S1D_VALUE)] = value;
}
///////////////////////////////////////////////////////////////////////////////
//
// Read register values from device or setup file and write them to the
// the device.
//
///////////////////////////////////////////////////////////////////////////////
static inline void
s1d13xxxfb_runinit( struct s1d13xxxfb_par *par,
const struct s1d13xxxfb_regval *initregs,
const unsigned int size )
{
int i;
u32 value;
printk("In s1d13xxxfb_runinit()\n");
printk("size = %d\n", size);
for (i = 0; i < size; i++)
{
if ((initregs[i].addr == S1DREG_DELAYOFF) ||
(initregs[i].addr == S1DREG_DELAYON))
{
mdelay((int)initregs[i].value);
}
else
{
s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value);
mdelay(10);
}
//printk("Tried to write: ");
//printk("initregs[i].addr: 0x%0.8x ", initregs[i].addr);
//printk("value: 0x%0.8x\n", initregs[i].value);
//value = s1d13xxxfb_readreg(par, initregs[i].addr);
//printk("Actually wrote: ");
//printk("initregs[i].addr: 0x%0.8x ", initregs[i].addr);
//printk("value: 0x%0.8x\n", value);
}
/* make sure the hardware can cope with us */
mdelay(1);
}
///////////////////////////////////////////////////////////////////////////////
//
// Set enable bit in device register
//
///////////////////////////////////////////////////////////////////////////////
static inline void
lcd_enable(struct s1d13xxxfb_par *par, int enable)
{
u32 mode = s1d13xxxfb_readreg(par, 0x10);
mode &= 0xff7fffff;
s1d13xxxfb_writereg(par, 0x10, mode);
}
/////////////////// FRAMEBUFFER CONTROL ROUTINES /////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Setup pseudocolor settings
//
///////////////////////////////////////////////////////////////////////////////
static inline void
s1d13xxxfb_setup_pseudocolour(struct fb_info *info)
{
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
//info->var.red.length = 4;
//info->var.green.length = 4;
//info->var.blue.length = 4;
info->var.red.length = 8;
info->var.green.length = 8;
info->var.blue.length = 8;
}
///////////////////////////////////////////////////////////////////////////////
//
// Setup true color settings
//
///////////////////////////////////////////////////////////////////////////////
static inline void
s1d13xxxfb_setup_truecolour(struct fb_info *info)
{
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->var.bits_per_pixel = 16;
info->var.red.length = 5;
info->var.red.offset = 11;
info->var.green.length = 6;
info->var.green.offset = 5;
info->var.blue.length = 5;
info->var.blue.offset = 0;
}
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_set_par - Alters the hardware state.
// @info: frame buffer structure
//
// Using the fb_var_screeninfo in fb_info we set the depth of the
// framebuffer. This function alters the par AND the
// fb_fix_screeninfo stored in fb_info. It doesn't not alter var in
// fb_info since we are using that data. This means we depend on the
// data in var inside fb_info to be supported by the hardware.
// xxxfb_check_var is always called before xxxfb_set_par to ensure this.
//
// XXX TODO: write proper s1d13xxxfb_check_var(), without which that
// function is quite useless.
//
///////////////////////////////////////////////////////////////////////////////
static int
s1d13xxxfb_set_par(struct fb_info *info)
{
struct s1d13xxxfb_par *s1dfb = info->par;
unsigned int val;
dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel);
// Read colour control
//val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE);
//val &= ~0x07;
switch (info->var.bits_per_pixel)
{
case 4:
dbg("pseudo colour 4\n");
s1d13xxxfb_setup_pseudocolour(info);
val |= 2;
break;
case 8:
dbg("pseudo colour 8\n");
s1d13xxxfb_setup_pseudocolour(info);
//val |= 3;
break;
case 16:
dbg("true colour\n");
s1d13xxxfb_setup_truecolour(info);
val |= 5;
break;
default:
dbg("bpp not supported!\n");
return -EINVAL;
}
dbg("writing %02x to display mode register\n", val);
// Write color control
//s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val);
//info->fix.line_length = info->var.xres * info->var.bits_per_pixel;
//info->fix.line_length /= 8;
info->fix.line_length = 320;
dbg("setting line_length to %d\n", info->fix.line_length);
dbg("done setup\n");
return 0;
}
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_setcolreg - sets a color register.
// @regno: Which register in the CLUT we are programming
// @red: The red value which can be up to 16 bits wide
// @green: The green value which can be up to 16 bits wide
// @blue: The blue value which can be up to 16 bits wide.
// @transp: If supported the alpha value which can be up to 16 bits wide.
// @info: frame buffer info structure
//
// Returns negative errno on error, or zero on success.
//
///////////////////////////////////////////////////////////////////////////////
static int
s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct s1d13xxxfb_par *s1dfb = info->par;
unsigned int pseudo_val;
unsigned long lutdata;
if (regno >= S1D_PALETTE_SIZE)
{
return -EINVAL;
}
dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n",
regno, red, green, blue, transp);
if (info->var.grayscale)
{
red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16;
}
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
switch (info->fix.visual)
{
case FB_VISUAL_TRUECOLOR:
if (regno >= 16)
{
return -EINVAL;
}
// Deal with creating pseudo-palette entries
pseudo_val = (red >> 11) << info->var.red.offset;
pseudo_val |= (green >> 10) << info->var.green.offset;
pseudo_val |= (blue >> 11) << info->var.blue.offset;
dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n",
regno, pseudo_val);
((u32 *)info->pseudo_palette)[regno] = pseudo_val;
break;
case FB_VISUAL_PSEUDOCOLOR:
//s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno);
//s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red);
//s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green);
//s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue);
lutdata =(regno << 24) | color_palette[regno*4] |
(color_palette[regno*4+1] << 8) |
(color_palette[regno*4+2] << 16);
s1d13xxxfb_writereg(s1dfb, 0x18, lutdata);
break;
default:
return -ENOSYS;
}
//dbg("s1d13xxxfb_setcolreg: done\n");
return 0;
}
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_blank - blanks the display.
// @blank_mode: the blank mode we want.
// @info: frame buffer structure that represents a single frame buffer
//
// Blank the screen if blank_mode != 0, else unblank. Return 0 if
// blanking succeeded, != 0 if un-/blanking failed due to e.g. a
// video mode which doesn't support it. Implements VESA suspend
// and powerdown modes on hardware that supports disabling hsync/vsync:
// blank_mode == 2: suspend vsync
// blank_mode == 3: suspend hsync
// blank_mode == 4: powerdown
//
// Returns negative errno on error, or zero on success.
//
///////////////////////////////////////////////////////////////////////////////
static int
s1d13xxxfb_blank(int blank_mode, struct fb_info *info)
{
struct s1d13xxxfb_par *par = info->par;
dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info);
switch (blank_mode)
{
case FB_BLANK_UNBLANK:
case FB_BLANK_NORMAL:
if ((par->display & 0x01) != 0)
{
lcd_enable(par, 1);
}
break;
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
break;
case FB_BLANK_POWERDOWN:
lcd_enable(par, 0);
break;
default:
return -EINVAL;
}
// Let fbcon do a soft blank for us
return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
}
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_pan_display - Pans the display.
// @var: frame buffer variable screen structure
// @info: frame buffer structure that represents a single frame buffer
//
// Pan (or wrap, depending on the `vmode' field) the display using the
// `yoffset' field of the `var' structure (`xoffset' not yet supported).
// If the values don't fit, return -EINVAL.
//
// Returns negative errno on error, or zero on success.
//
///////////////////////////////////////////////////////////////////////////////
static int
s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct s1d13xxxfb_par *par = info->par;
u32 start;
if (var->xoffset != 0) // not yet ...
{
return -EINVAL;
}
if (var->yoffset + info->var.yres > info->var.yres_virtual)
{
return -EINVAL;
}
start = (info->fix.line_length >> 1) * var->yoffset;
//s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff));
//s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff));
//s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f));
return 0;
}
/////////////////// FRAMEBUFFER INFORMATION STRUCTURES //////////////////////
static struct fb_ops s1d13xxxfb_fbops =
{
.owner = THIS_MODULE,
.fb_set_par = s1d13xxxfb_set_par,
.fb_setcolreg = s1d13xxxfb_setcolreg,
.fb_blank = s1d13xxxfb_blank,
.fb_pan_display = s1d13xxxfb_pan_display,
// To be replaced by any acceleration we can
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static int s1d13xxxfb_width_tab[2][4] __devinitdata =
{
{4, 8, 16, -1},
{9, 12, 18, -1},
};
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
// hardware setup.
// @info: frame buffer structure
//
// We setup the framebuffer structures according to the current
// hardware setup. On some machines, the BIOS will have filled
// the chip registers with such info, on others, these values will
// have been written in some init procedure. In any case, the
// software values needs to match the hardware ones. This is what
// this function ensures.
//
// Note: some of the hardcoded values here might need some love to
// work on various chips, and might need to no longer be hardcoded.
//
///////////////////////////////////////////////////////////////////////////////
static void __devinit
s1d13xxxfb_fetch_hw_state(struct fb_info *info)
{
struct fb_var_screeninfo *var = &info->var;
struct fb_fix_screeninfo *fix = &info->fix;
struct s1d13xxxfb_par *par = info->par;
u8 panel, display;
u16 offset;
u32 xres, yres;
u32 xres_virtual, yres_virtual;
int bpp, lcd_bpp;
int is_color, is_dual, is_tft;
int lcd_enabled, crt_enabled;
printk("In fetch_hw_state()\n");
fix->type = FB_TYPE_PACKED_PIXELS;
printk("1\n");
// General info
//par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
par->display = s1d13xxxfb_readreg(par, 0x0);
printk("par->display: 0x%x\n", par->display);
printk("2\n");
crt_enabled = (par->display & 0x02) != 0;
printk("3\n");
lcd_enabled = (par->display & 0x01) != 0;
printk("4\n");
crt_enabled = 0;
lcd_enabled = 1;
printk("5\n");
//display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE);
display = s1d13xxxfb_readreg(par, 0x10);
printk("dispay: 0x%x\n", display);
printk("6\n");
//bpp = display & 0x07;
bpp = 3;
printk("bpp: %d\n", bpp);
switch (bpp)
{
case 2: /* 4 bpp */
case 3: /* 8 bpp */
var->bits_per_pixel = 8;
var->red.offset = var->green.offset = var->blue.offset = 0;
var->red.length = var->green.length = var->blue.length = 8;
break;
case 5: /* 16 bpp */
s1d13xxxfb_setup_truecolour(info);
break;
default:
dbg("bpp: %i\n", bpp);
}
fb_alloc_cmap(&info->cmap, 256, 0);
printk("7\n");
/* LCD info */
//panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE);
//is_color = (panel & 0x04) != 0;
//is_dual = (panel & 0x02) != 0;
//is_tft = (panel & 0x01) != 0;
//lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3];
is_color = 1;
is_dual = 0;
is_tft = 0;
lcd_bpp = 8;
printk("8\n");
printk("lcd_enabled: %d\n", lcd_enabled);
//xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8;
xres = 320;
//yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) +
// ((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1);
yres = 240;
//offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) +
// ((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8));
offset = 0;
printk("9\n");
printk("var->bits_per_pixel: 0x%x\n", var->bits_per_pixel);
printk("fix->smem_len: 0x%x\n", fix->smem_len);
printk("offset: 0x%x\n", offset);
//xres_virtual = offset * 16 / var->bits_per_pixel;
xres_virtual = xres;
//yres_virtual = fix->smem_len / (offset * 2);
yres_virtual = yres;
printk("10\n");
var->xres = xres;
var->yres = yres;
var->xres_virtual = xres_virtual;
var->yres_virtual = yres_virtual;
var->xoffset = var->yoffset = 0;
//fix->line_length = offset * 2;
fix->line_length = 320;
var->grayscale = !is_color;
var->activate = FB_ACTIVATE_NOW;
/////////////////////////////////////////////////////////////
var->xres = 320;
var->yres = 240;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
var->xoffset = var->yoffset = 0;
var->bits_per_pixel = 8;
var->grayscale = 0;
var->nonstd = 0; /* != 0 Non standard pixel format */
var->activate = FB_ACTIVATE_NOW; /* see FB_ACTIVATE_* */
var->height = -1; /* height of picture in mm */
var->width = -1; /* width of picture in mm */
var->accel_flags = 0; /* acceleration flags (hints */
var->pixclock = S1D_DISPLAY_PCLK;
var->right_margin = 0;
var->lower_margin = 0;
var->hsync_len = 0;
var->vsync_len = 0;
var->left_margin = 0;
var->upper_margin = 0;
var->sync = 0;
var->vmode = FB_VMODE_NONINTERLACED;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
var->transp.offset = var->transp.length = var->transp.msb_right = 0;
/////////////////////////////////////////////////////////////
dbg ("bpp=%d, lcd_bpp=%d, crt_enabled=%d, lcd_enabled=%d\n",
var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled);
dbg ("xres=%d, yres=%d, vxres=%d, vyres=%d "
"is_color=%d, is_dual=%d, is_tft=%d\n",
xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft);
}
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_remove - Unregister frame buffer device from kernel
//
///////////////////////////////////////////////////////////////////////////////
static int
s1d13xxxfb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct s1d13xxxfb_par *par = NULL;
if (info)
{
par = info->par;
if (par && par->regs)
{
// Disable output & enable powersave
//s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00);
//s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11);
iounmap(par->regs);
}
fb_dealloc_cmap(&info->cmap);
if (info->screen_base)
{
iounmap(info->screen_base);
}
framebuffer_release(info);
}
release_mem_region(pdev->resource[0].start,
pdev->resource[0].end - pdev->resource[0].start +1);
release_mem_region(pdev->resource[1].start,
pdev->resource[1].end - pdev->resource[1].start +1);
return 0;
}
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_probe - Initialize and load frame buffer for use by kernel
//
///////////////////////////////////////////////////////////////////////////////
static int __devinit
s1d13xxxfb_probe(struct platform_device *pdev)
{
struct s1d13xxxfb_par *default_par;
struct fb_info *info;
struct s1d13xxxfb_pdata *pdata = NULL;
int ret = 0;
u8 revision;
dbg("probe called: device is %p\n", pdev);
printk(KERN_INFO "Epson S1D13XXX FB Driver\n");
// Enable platform-dependent hardware glue, if any
if (pdev->dev.platform_data)
{
pdata = pdev->dev.platform_data;
printk(KERN_INFO "pdata set\n");
}
if (pdata && pdata->platform_init_video)
{
pdata->platform_init_video();
printk(KERN_INFO "pdata->platform_init_video() called\n");
}
if (pdev->num_resources != 2)
{
dev_err(&pdev->dev, "invalid num_resources: %i\n", pdev->num_resources);
ret = -ENODEV;
goto bail;
}
// resource[0] is VRAM, resource[1] is registers
if (pdev->resource[0].flags != IORESOURCE_MEM ||
pdev->resource[1].flags != IORESOURCE_MEM)
{
dev_err(&pdev->dev, "invalid resource type\n");
ret = -ENODEV;
goto bail;
}
if (!request_mem_region(pdev->resource[0].start,
pdev->resource[0].end - pdev->resource[0].start +1, "s1d13xxxfb mem"))
{
dev_dbg(&pdev->dev, "request_mem_region failed\n");
ret = -EBUSY;
goto bail;
}
if (!request_mem_region(pdev->resource[1].start,
pdev->resource[1].end - pdev->resource[1].start +1, "s1d13xxxfb regs"))
{
dev_dbg(&pdev->dev, "request_mem_region failed\n");
ret = -EBUSY;
goto bail;
}
info = framebuffer_alloc(
sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev);
if (!info)
{
ret = -ENOMEM;
goto bail;
}
platform_set_drvdata(pdev, info);
default_par = info->par;
default_par->regs = ioremap_nocache(pdev->resource[1].start,
pdev->resource[1].end - pdev->resource[1].start +1);
if (!default_par->regs)
{
printk(KERN_ERR PFX "unable to map registers\n");
ret = -ENOMEM;
goto bail;
}
info->pseudo_palette = default_par->pseudo_palette;
info->screen_base = ioremap_nocache(pdev->resource[0].start,
pdev->resource[0].end - pdev->resource[0].start +1);
if (!info->screen_base)
{
printk(KERN_ERR PFX "unable to map framebuffer\n");
ret = -ENOMEM;
goto bail;
}
// Turn BitBLT off
s1d13xxxfb_writereg(info->par, 0x8000, 0x00000000);
printk ("revision = 0x%x\n", revision);
info->fix = s1d13xxxfb_fix;
info->fix.mmio_start = pdev->resource[1].start;
info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start +1;
info->fix.smem_start = pdev->resource[0].start;
info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start +1;
printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
default_par->regs, info->fix.smem_len / 1024, info->screen_base);
info->par = default_par;
info->fbops = &s1d13xxxfb_fbops;
//info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
info->flags = FBINFO_DEFAULT;
// Perform "manual" chip initialization, if needed
if (pdata && pdata->initregs)
{
s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize);
}
s1d13xxxfb_fetch_hw_state(info);
// Enable device
u32 mode = s1d13xxxfb_readreg(info->par, 0x10);
mode &= 0xff7fffff;
s1d13xxxfb_writereg(info->par, 0x10, mode);
if (register_framebuffer(info) < 0)
{
ret = -EINVAL;
goto bail;
}
printk(KERN_INFO "fb%d: %s frame buffer device\n",info->node,info->fix.id);
return 0;
bail:
s1d13xxxfb_remove(pdev);
return ret;
}
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_suspend -
//
///////////////////////////////////////////////////////////////////////////////
#ifdef CONFIG_PM
static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state)
{
struct fb_info *info = platform_get_drvdata(dev);
struct s1d13xxxfb_par *s1dfb = info->par;
struct s1d13xxxfb_pdata *pdata = NULL;
// Disable display
lcd_enable(s1dfb, 0);
if (dev->dev.platform_data)
{
pdata = dev->dev.platform_data;
}
#if 0
if (!s1dfb->disp_save)
s1dfb->disp_save = kmalloc(info->fix.smem_len, GFP_KERNEL);
if (!s1dfb->disp_save) {
printk(KERN_ERR PFX "no memory to save screen");
return -ENOMEM;
}
memcpy_fromio(s1dfb->disp_save, info->screen_base, info->fix.smem_len);
#else
s1dfb->disp_save = NULL;
#endif
if (!s1dfb->regs_save)
{
s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL);
}
if (!s1dfb->regs_save)
{
printk(KERN_ERR PFX "no memory to save registers");
return -ENOMEM;
}
/* backup all registers */
memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len);
/* now activate power save mode */
//s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11);
if (pdata && pdata->platform_suspend_video)
{
return pdata->platform_suspend_video();
}
else
{
return 0;
}
}
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_resume -
//
///////////////////////////////////////////////////////////////////////////////
static int s1d13xxxfb_resume(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
struct s1d13xxxfb_par *s1dfb = info->par;
struct s1d13xxxfb_pdata *pdata = NULL;
// Awaken the chip
//s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10);
// Do not let go until SDRAM "wakes up"
while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01))
{
udelay(10);
}
if (dev->dev.platform_data)
{
pdata = dev->dev.platform_data;
}
if (s1dfb->regs_save)
{
// Will write RO regs, *should* get away with it :)
memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len);
kfree(s1dfb->regs_save);
}
if (s1dfb->disp_save)
{
memcpy_toio(info->screen_base, s1dfb->disp_save, info->fix.smem_len);
kfree(s1dfb->disp_save); // XXX kmalloc()'d when?
}
if ((s1dfb->display & 0x01) != 0)
{
lcd_enable(s1dfb, 1);
}
if (pdata && pdata->platform_resume_video)
{
return pdata->platform_resume_video();
}
else
{
return 0;
}
}
#endif /* CONFIG_PM */
//
// Here we define the platform struct s1d13xxxfb_driver
//
static struct platform_driver s1d13xxxfb_driver =
{
.probe = s1d13xxxfb_probe,
.remove = s1d13xxxfb_remove,
#ifdef CONFIG_PM
.suspend = s1d13xxxfb_suspend,
.resume = s1d13xxxfb_resume,
#endif
.driver =
{
.name = S1D_DEVICENAME,
},
};
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_init - Start intitialization of frame buffer
//
///////////////////////////////////////////////////////////////////////////////
static int __init
s1d13xxxfb_init(void)
{
#ifndef MODULE
if (fb_get_options("s1d13xxxfb", NULL))
{
return -ENODEV;
}
#endif
return platform_driver_register(&s1d13xxxfb_driver);
}
///////////////////////////////////////////////////////////////////////////////
//
// s1d13xxxfb_exit - Unregister driver
//
///////////////////////////////////////////////////////////////////////////////
static void __exit
s1d13xxxfb_exit(void)
{
platform_driver_unregister(&s1d13xxxfb_driver);
}
module_init(s1d13xxxfb_init);
module_exit(s1d13xxxfb_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices");
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Thibaut VARENE <varenet@parisc-linux.org>");
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #3: mcf5445x-devices.c --]
[-- Type: text/x-csrc; name="mcf5445x-devices.c", Size: 3258 bytes --]
/*
* arch/m68k/coldfire/mcf5445x-devices.c
*
* Coldfire M5445x Platform Device Configuration
*
* Based on the Freescale MXC devices.c
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
* Kurt Mahan <kmahan@freescale.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/* ATA Interrupt */
#define IRQ_ATA (64 + 64 + 54)
/* ATA Base */
#define BASE_IO_ATA 0x90000000
#define ATA_IER MCF_REG08(BASE_IO_ATA+0x2c) /* int enable reg */
#define ATA_ICR MCF_REG08(BASE_IO_ATA+0x30) /* int clear reg */
/*
* On-chip PATA
*/
#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE)
static int ata_init(struct platform_device *pdev)
{
/* clear ints */
ATA_IER = 0x00;
ATA_ICR = 0xff;
/* setup shared pins */
MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & MCF_GPIO_PAR_FEC_FEC1_MASK) |
MCF_GPIO_PAR_FEC_FEC1_ATA;
MCF_GPIO_PAR_FECI2C = (MCF_GPIO_PAR_FECI2C &
(MCF_GPIO_PAR_FECI2C_MDC1_MASK &
MCF_GPIO_PAR_FECI2C_MDIO1_MASK)) |
MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW;
MCF_GPIO_PAR_ATA = MCF_GPIO_PAR_ATA_BUFEN |
MCF_GPIO_PAR_ATA_CS1 |
MCF_GPIO_PAR_ATA_CS0 |
MCF_GPIO_PAR_ATA_DA2 |
MCF_GPIO_PAR_ATA_DA1 |
MCF_GPIO_PAR_ATA_DA0 |
MCF_GPIO_PAR_ATA_RESET_RESET |
MCF_GPIO_PAR_ATA_DMARQ_DMARQ |
MCF_GPIO_PAR_ATA_IORDY_IORDY;
MCF_GPIO_PAR_PCI = (MCF_GPIO_PAR_PCI &
(MCF_GPIO_PAR_PCI_GNT3_MASK &
MCF_GPIO_PAR_PCI_REQ3_MASK)) |
MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK |
MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ;
return 0;
}
static void ata_exit(void)
{
printk(KERN_INFO "** ata_exit\n");
}
static int ata_get_clk_rate(void)
{
return MCF_BUSCLK;
}
/* JKM -- move these to a header file */
#define MCF_IDE_DMA_WATERMARK 32 /* DMA watermark level in bytes */
#define MCF_IDE_DMA_BD_NR (512/3/4) /* number of BDs per channel */
static struct fsl_ata_platform_data ata_data = {
.init = ata_init,
.exit = ata_exit,
.get_clk_rate = ata_get_clk_rate,
#ifdef CONFIG_PATA_FSL_USE_DMA
.udma_mask = 0x0F, /* the board handles up to UDMA3 */
.fifo_alarm = MCF_IDE_DMA_WATERMARK / 2,
.max_sg = MCF_IDE_DMA_BD_NR,
#endif
};
static struct resource pata_fsl_resources[] = {
[0] = { /* I/O */
.start = BASE_IO_ATA,
.end = BASE_IO_ATA + 0x000000d8,
.flags = IORESOURCE_MEM,
},
[2] = { /* IRQ */
.start = IRQ_ATA,
.end = IRQ_ATA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device pata_fsl_device = {
.name = "pata_fsl",
.id = -1,
.num_resources = ARRAY_SIZE(pata_fsl_resources),
.resource = pata_fsl_resources,
.dev = {
.platform_data = &ata_data,
.coherent_dma_mask = ~0, /* $$$ REVISIT */
},
};
static inline void mcf5445x_init_pata(void)
{
(void)platform_device_register(&pata_fsl_device);
}
#else
static inline void mcf5445x_init_pata(void)
{
}
#endif
static int __init mcf5445x_init_devices(void)
{
printk(KERN_INFO "MCF5445x INIT_DEVICES\n");
#if 0
mcf5445x_init_pata();
#endif
return 0;
}
arch_initcall(mcf5445x_init_devices);
[-- Attachment #4: s1d13xxxfb.h --]
[-- Type: application/octet-stream, Size: 10054 bytes --]
/* include/video/s1d13xxxfb.h
*
* (c) 2004 Simtec Electronics
* (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
*
* Header file for Epson S1D13XXX driver code
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#ifndef S1D13XXXFB_H
#define S1D13XXXFB_H
#define S1D_PALETTE_SIZE 256
#define S1D_CHIP_REV 7 /* expected chip revision number for s1d13806 */
#define S1D_FBID "S1D13806"
/* #define S1D_DEVICENAME "s1d13806fb" */
#define S1D_DEVICENAME "s1d13a04fb"
/* register definitions (tested on s1d13896) */
#define S1DREG_REV_CODE 0x0000 /* Revision Code Register */
#define S1DREG_MISC 0x0001 /* Miscellaneous Register */
#define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
#define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
#define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
#define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
#define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
#define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
#define S1DREG_LCD_CLK_CNF 0x0014 /* LCD Pixel Clock Configuration Register */
#define S1DREG_CRT_CLK_CNF 0x0018 /* CRT/TV Pixel Clock Configuration Register */
#define S1DREG_MPLUG_CLK_CNF 0x001C /* MediaPlug Clock Configuration Register */
#define S1DREG_CPU2MEM_WST_SEL 0x001E /* CPU To Memory Wait State Select Register */
#define S1DREG_MEM_CNF 0x0020 /* Memory Configuration Register */
#define S1DREG_SDRAM_REF_RATE 0x0021 /* SDRAM Refresh Rate Register */
#define S1DREG_SDRAM_TC0 0x002A /* SDRAM Timing Control Register 0 */
#define S1DREG_SDRAM_TC1 0x002B /* SDRAM Timing Control Register 1 */
#define S1DREG_PANEL_TYPE 0x0030 /* Panel Type Register */
#define S1DREG_MOD_RATE 0x0031 /* MOD Rate Register */
#define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/line */
#define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=NDpix/line */
#define S1DREG_TFT_FPLINE_START 0x0035 /* TFT FPLINE Start Position Register */
#define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
#define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */
#define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */
#define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines */
#define S1DREG_TFT_FPFRAME_START 0x003B /* TFT FPFRAME Start Position Register */
#define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
#define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
#define S1DREG_LCD_MISC 0x0041 /* LCD Miscellaneous Register */
#define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
#define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
#define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
#define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
#define S1DREG_LCD_MEM_OFF1 0x0047 /* LCD Memory Address Offset Register 1 */
#define S1DREG_LCD_PIX_PAN 0x0048 /* LCD Pixel Panning Register */
#define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
#define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */
#define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pix/line */
#define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
#define S1DREG_CRT_HRTC_START 0x0053 /* CRT/TV HRTC Start Position Register */
#define S1DREG_CRT_HRTC_PWIDTH 0x0054 /* CRT/TV HRTC Pulse Width Register */
#define S1DREG_CRT_DISP_VHEIGHT0 0x0056 /* CRT/TV Vertical Display Height Register 0 */
#define S1DREG_CRT_DISP_VHEIGHT1 0x0057 /* CRT/TV Vertical Display Height Register 1 */
#define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */
#define S1DREG_CRT_VRTC_START 0x0059 /* CRT/TV VRTC Start Position Register */
#define S1DREG_CRT_VRTC_PWIDTH 0x005A /* CRT/TV VRTC Pulse Width Register */
#define S1DREG_TV_OUT_CTL 0x005B /* TV Output Control Register */
#define S1DREG_CRT_DISP_MODE 0x0060 /* CRT/TV Display Mode Register */
#define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */
#define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */
#define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */
#define S1DREG_CRT_MEM_OFF0 0x0066 /* CRT/TV Memory Address Offset Register 0 */
#define S1DREG_CRT_MEM_OFF1 0x0067 /* CRT/TV Memory Address Offset Register 1 */
#define S1DREG_CRT_PIX_PAN 0x0068 /* CRT/TV Pixel Panning Register */
#define S1DREG_CRT_DISP_FIFO_HTC 0x006A /* CRT/TV Display FIFO High Threshold Control Register */
#define S1DREG_CRT_DISP_FIFO_LTC 0x006B /* CRT/TV Display FIFO Low Threshold Control Register */
#define S1DREG_LCD_CUR_CTL 0x0070 /* LCD Ink/Cursor Control Register */
#define S1DREG_LCD_CUR_START 0x0071 /* LCD Ink/Cursor Start Address Register */
#define S1DREG_LCD_CUR_XPOS0 0x0072 /* LCD Cursor X Position Register 0 */
#define S1DREG_LCD_CUR_XPOS1 0x0073 /* LCD Cursor X Position Register 1 */
#define S1DREG_LCD_CUR_YPOS0 0x0074 /* LCD Cursor Y Position Register 0 */
#define S1DREG_LCD_CUR_YPOS1 0x0075 /* LCD Cursor Y Position Register 1 */
#define S1DREG_LCD_CUR_BCTL0 0x0076 /* LCD Ink/Cursor Blue Color 0 Register */
#define S1DREG_LCD_CUR_GCTL0 0x0077 /* LCD Ink/Cursor Green Color 0 Register */
#define S1DREG_LCD_CUR_RCTL0 0x0078 /* LCD Ink/Cursor Red Color 0 Register */
#define S1DREG_LCD_CUR_BCTL1 0x007A /* LCD Ink/Cursor Blue Color 1 Register */
#define S1DREG_LCD_CUR_GCTL1 0x007B /* LCD Ink/Cursor Green Color 1 Register */
#define S1DREG_LCD_CUR_RCTL1 0x007C /* LCD Ink/Cursor Red Color 1 Register */
#define S1DREG_LCD_CUR_FIFO_HTC 0x007E /* LCD Ink/Cursor FIFO High Threshold Register */
#define S1DREG_CRT_CUR_CTL 0x0080 /* CRT/TV Ink/Cursor Control Register */
#define S1DREG_CRT_CUR_START 0x0081 /* CRT/TV Ink/Cursor Start Address Register */
#define S1DREG_CRT_CUR_XPOS0 0x0082 /* CRT/TV Cursor X Position Register 0 */
#define S1DREG_CRT_CUR_XPOS1 0x0083 /* CRT/TV Cursor X Position Register 1 */
#define S1DREG_CRT_CUR_YPOS0 0x0084 /* CRT/TV Cursor Y Position Register 0 */
#define S1DREG_CRT_CUR_YPOS1 0x0085 /* CRT/TV Cursor Y Position Register 1 */
#define S1DREG_CRT_CUR_BCTL0 0x0086 /* CRT/TV Ink/Cursor Blue Color 0 Register */
#define S1DREG_CRT_CUR_GCTL0 0x0087 /* CRT/TV Ink/Cursor Green Color 0 Register */
#define S1DREG_CRT_CUR_RCTL0 0x0088 /* CRT/TV Ink/Cursor Red Color 0 Register */
#define S1DREG_CRT_CUR_BCTL1 0x008A /* CRT/TV Ink/Cursor Blue Color 1 Register */
#define S1DREG_CRT_CUR_GCTL1 0x008B /* CRT/TV Ink/Cursor Green Color 1 Register */
#define S1DREG_CRT_CUR_RCTL1 0x008C /* CRT/TV Ink/Cursor Red Color 1 Register */
#define S1DREG_CRT_CUR_FIFO_HTC 0x008E /* CRT/TV Ink/Cursor FIFO High Threshold Register */
#define S1DREG_BBLT_CTL0 0x0100 /* BitBLT Control Register 0 */
#define S1DREG_BBLT_CTL1 0x0101 /* BitBLT Control Register 1 */
#define S1DREG_BBLT_CC_EXP 0x0102 /* BitBLT Code/Color Expansion Register */
#define S1DREG_BBLT_OP 0x0103 /* BitBLT Operation Register */
#define S1DREG_BBLT_SRC_START0 0x0104 /* BitBLT Source Start Address Register 0 */
#define S1DREG_BBLT_SRC_START1 0x0105 /* BitBLT Source Start Address Register 1 */
#define S1DREG_BBLT_SRC_START2 0x0106 /* BitBLT Source Start Address Register 2 */
#define S1DREG_BBLT_DST_START0 0x0108 /* BitBLT Destination Start Address Register 0 */
#define S1DREG_BBLT_DST_START1 0x0109 /* BitBLT Destination Start Address Register 1 */
#define S1DREG_BBLT_DST_START2 0x010A /* BitBLT Destination Start Address Register 2 */
#define S1DREG_BBLT_MEM_OFF0 0x010C /* BitBLT Memory Address Offset Register 0 */
#define S1DREG_BBLT_MEM_OFF1 0x010D /* BitBLT Memory Address Offset Register 1 */
#define S1DREG_BBLT_WIDTH0 0x0110 /* BitBLT Width Register 0 */
#define S1DREG_BBLT_WIDTH1 0x0111 /* BitBLT Width Register 1 */
#define S1DREG_BBLT_HEIGHT0 0x0112 /* BitBLT Height Register 0 */
#define S1DREG_BBLT_HEIGHT1 0x0113 /* BitBLT Height Register 1 */
#define S1DREG_BBLT_BGC0 0x0114 /* BitBLT Background Color Register 0 */
#define S1DREG_BBLT_BGC1 0x0115 /* BitBLT Background Color Register 1 */
#define S1DREG_BBLT_FGC0 0x0118 /* BitBLT Foreground Color Register 0 */
#define S1DREG_BBLT_FGC1 0x0119 /* BitBLT Foreground Color Register 1 */
#define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */
#define S1DREG_LKUP_ADDR 0x01E2 /* Look-Up Table Address Register */
#define S1DREG_LKUP_DATA 0x01E4 /* Look-Up Table Data Register */
#define S1DREG_PS_CNF 0x01F0 /* Power Save Configuration Register */
#define S1DREG_PS_STATUS 0x01F1 /* Power Save Status Register */
#define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */
#define S1DREG_COM_DISP_MODE 0x01FC /* Common Display Mode Register */
#define S1DREG_DELAYOFF 0xFFFE
#define S1DREG_DELAYON 0xFFFF
/* Note: all above defines should go in separate header files
when implementing other S1D13xxx chip support. */
struct s1d13xxxfb_regval {
//u16 addr;
//u8 value;
u8 addr;
u32 value;
};
struct s1d13xxxfb_par {
void __iomem *regs;
unsigned char display;
unsigned int pseudo_palette[16];
#ifdef CONFIG_PM
void *regs_save; /* pm saves all registers here */
void *disp_save; /* pm saves entire screen here */
#endif
};
struct s1d13xxxfb_pdata {
const struct s1d13xxxfb_regval *initregs;
const unsigned int initregssize;
void (*platform_init_video)(void);
#ifdef CONFIG_PM
int (*platform_suspend_video)(void);
int (*platform_resume_video)(void);
#endif
};
#endif
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04on Coldfire running 2.6.25)
2008-11-11 14:50 ` Seg fault on any FB write (Epson S1D13A04on " jkimble
@ 2008-11-11 15:04 ` Hinko Kocevar
2008-11-11 16:10 ` Seg fault on any FB write (Epson S1D13A04onColdfire " jkimble
2008-11-11 18:52 ` Seg fault on any FB write (Epson S1D13A04on Coldfire " Kristoffer Ericson
2008-11-11 15:06 ` jkimble
1 sibling, 2 replies; 18+ messages in thread
From: Hinko Kocevar @ 2008-11-11 15:04 UTC (permalink / raw)
To: jkimble; +Cc: linux-fbdev-devel
jkimble@one.net wrote:
>> James Kimble wrote:
>
> /proc/iomem shows:
>
> 74000000-74009000 : s1d13a04fb.0
> 74000000-74009000 : s1d13xxxfb regs
> 74040000-74068000 : s1d13a04fb.0
> 74040000-74068000 : s1d13xxxfb mem
I'm not sure if this is correct - two drivers mapped the same region twice !?
Maybe the experts will shed some light on this..
> f000070c-f000070c : spi-int-mask
> f0000740-f000075f : spi-int-level
> f0000a50-f0000a50 : spi-par
> f0008a00-f0008ab8 : spi-module
> f0008f00-f0008f20 : MCF548X-i2c
> f000a000-f000a7ff : mcf548x-flexcan.0
> f000a000-f000a7ff : mcf548x-flexcan
> f000a800-f000afff : mcf548x-flexcan.1
> f000a800-f000afff : mcf548x-flexcan
> f0020000-f0033000 : fsl-sec1
> fc000000-ffffffff : physmap-flash.0
>
I haven't took a long look at your driver, but here is our driver for S13706FB that
we use on our embedded platform. Hope it helps.
Regards,
Hinko
--
Hinko Kočevar, OSS developer
ČETRTA POT, d.o.o.
Planina 3, 4000 Kranj, SI EU
tel ++386 (0) 4 280 66 03
e-mail hinko.kocevar@cetrtapot.si
http www.cetrtapot.si
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* Re: Seg fault on any FB write (Epson S1D13A04on Coldfire running 2.6.25)
2008-11-11 14:50 ` Seg fault on any FB write (Epson S1D13A04on " jkimble
2008-11-11 15:04 ` Hinko Kocevar
@ 2008-11-11 15:06 ` jkimble
1 sibling, 0 replies; 18+ messages in thread
From: jkimble @ 2008-11-11 15:06 UTC (permalink / raw)
To: jkimble; +Cc: linux-fbdev-devel
[-- Attachment #1: Type: text/plain, Size: 2385 bytes --]
>> James Kimble wrote:
>>> I've been working on porting the s1d13xxxfb driver from the latest
>>> kernel from Freescale for Coldfire to work with the S1D13A04 chip. I
>>> was
>>> able to get things working to the point that I do get a little TUX logo
>>> up on the screen at boot up. Seemed like a good start but none of my
>>> user space applications will work. I can open the /dev/fb0 device and
>>> the data in the info structure is correct but if I try to write to any
>>> register or area in the frame buffer (or write to the device at all) I
>>> get a seg fault.
>>>
>>> I had an earlier driver working with the 2.6.10 kernel with the same
>>> hardware. The same application space program should work ( I would
>>> think...) but I get the seg fault on the first write to fb0. I tried a
>>> different memory location (ox4400 0000 to 0x7400 0000) for the CS
>>> associated with the video chip, no difference. Permissions for
>>> /dev/fb0 are "rw". No other process using fb0. This is really weird.
>>>
>>> Any help or suggestions MUCH appreciated.
>>>
>>
>> You are probably not reserving and/or translating physical memory space
>> to virtual if you get a segfault on every access. Try cat /proc/iomem.
>> Is
>> your device listed?
>>
>> OTOH, a lot of arch specific code has probably changed since 2.6.10 -
>> 2.6.25 that might not even be directly related to fb. Is your arch port
>> up to date?
>>
>> Also you might post your fb driver and someone might spot the fault
>> faster..
>>
>
> /proc/iomem shows:
>
> 74000000-74009000 : s1d13a04fb.0
> 74000000-74009000 : s1d13xxxfb regs
> 74040000-74068000 : s1d13a04fb.0
> 74040000-74068000 : s1d13xxxfb mem
> f000070c-f000070c : spi-int-mask
> f0000740-f000075f : spi-int-level
> f0000a50-f0000a50 : spi-par
> f0008a00-f0008ab8 : spi-module
> f0008f00-f0008f20 : MCF548X-i2c
> f000a000-f000a7ff : mcf548x-flexcan.0
> f000a000-f000a7ff : mcf548x-flexcan
> f000a800-f000afff : mcf548x-flexcan.1
> f000a800-f000afff : mcf548x-flexcan
> f0020000-f0033000 : fsl-sec1
> fc000000-ffffffff : physmap-flash.0
>
> Which looks fine to me. The s1d13 lines match the mapping I set up. I've
> attached the driver. It is the driver for this family of chips that was
> included in the Freescale release of the 2.6.25 kernel for Coldfire. It
> includes my changes.
>
Sorry, wrong devices file. Should have been mcf438x-devices.c. See attached..
[-- Attachment #2: mcf548x-devices.c --]
[-- Type: application/octet-stream, Size: 5878 bytes --]
/*
* arch/m68k/coldfire/mcf5445x-devices.c
*
* Coldfire M5445x Platform Device Configuration
*
* Based on the Freescale MXC devices.c
*
* Copyright (c) 2007 Freescale Semiconductor, Inc.
* Kurt Mahan <kmahan@freescale.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <video/s1d13xxxfb.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/* memory space (line 52 of HP's doc) */
#define EPSONREGSTART 0x74000000
#define EPSONREGLEN 0x00009000
#define EPSONFBSTART 0x74040000
/* 160kB framebuffer */
#define EPSONFBLEN 0x00028000
/*
#define EPSONREGSTART 0x44000000
#define EPSONREGLEN 0x00009000
#define EPSONFBSTART 0x44040000
// 160kB framebuffer
#define EPSONFBLEN 0x00028000
*/
static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] =
{
{0x14, 0x00000000}, /* Power Save Configuration Register */
{0x64, 0x00000000}, /* GPIO Status and Control Register */
{0x04, 0x00000000}, /* Memory Clock Configuration Register */
{0x08, 0x00000032}, /* Pixel Clock Configuration Register */
{0x0C, 0x000000D0}, /* Panel Type and MOD Rate Register */
{0x10, 0x00800008}, /* Display Settings Register */
{0x20, 0x0000002B}, /* Horizontal Total Register */
{0x24, 0x00000027}, /* Horiz Display Period Register */
{0x28, 0x00000000}, /* Horiz Display Period Start Position Register */
{0x2C, 0x00870156}, /* FPLINE Register */
{0x30, 0x000000FA}, /* Vert Total Register */
{0x34, 0x000000EF}, /* Vert Display Period Register */
{0x38, 0x00000000}, /* Vert Display Period Start Position Register */
{0x3C, 0x00800000}, /* FPFRAME Register */
{0x40, 0x00000000}, /* Main Window Display Start Address Register */
{0x44, 0x00000050}, /* Main Window Line Address Offset Register */
{0x50, 0x00000000}, /* PIP+ Window Display Start Address Register */
{0x54, 0x00000050}, /* PIP+ Window Line Address Offset Register */
{0x58, 0x00000000}, /* PIP+ Window X Positions Register */
{0x5C, 0x00000000}, /* PIP+ Window Y Positions Register */
{0x60, 0x00000000}, /* Special Purpose Register */
{0x70, 0x00000000}, /* PWM Clock Configuration Register */
{0x74, 0x00000010}, /* PWMOUT Duty Cycle Register */
{0x80, 0x00000000}, /* Scratch Pad A Register */
{0x84, 0x00000000}, /* Scratch Pad B Register */
{0x88, 0x00000000}, /* Scratch Pad C Register */
{0x64, 0x08060000}, /* GPIO Status and Control Register */
{0x14, 0x00000000}, /* Power Save Configuration Register */
};
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
.initregs = s1d13xxxfb_initregs,
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
.platform_init_video = NULL
};
static struct resource s1d13xxxfb_resources[] = {
[0] = {
.start = EPSONFBSTART,
.end = EPSONFBSTART + EPSONFBLEN,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = EPSONREGSTART,
.end = EPSONREGSTART + EPSONREGLEN,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device s1d13xxxfb_device = {
.name = S1D_DEVICENAME,
.id = 0,
.dev = {
.platform_data = &s1d13xxxfb_data,
},
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
.resource = s1d13xxxfb_resources,
};
static struct resource coldfire_i2c_resources[] = {
[0] = { /* I/O */
.start = MCF_MBAR + 0x008F00,
.end = MCF_MBAR + 0x008F20,
.flags = IORESOURCE_MEM,
},
[2] = { /* IRQ */
.start = 40,
.end = 40,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device coldfire_i2c_device = {
.name = "MCF548X-i2c",
.id = -1,
.num_resources = ARRAY_SIZE(coldfire_i2c_resources),
.resource = coldfire_i2c_resources,
};
static struct resource coldfire_sec_resources[] = {
[0] = { /* I/O */
.start = MCF_MBAR + 0x00020000,
.end = MCF_MBAR + 0x00033000,
.flags = IORESOURCE_MEM,
},
[2] = { /* IRQ */
.start = ISC_SEC,
.end = ISC_SEC,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device coldfire_sec_device = {
.name = "fsl-sec1",
.id = -1,
.num_resources = ARRAY_SIZE(coldfire_sec_resources),
.resource = coldfire_sec_resources,
};
#if defined(CONFIG_MTD_PHYSMAP)
static struct physmap_flash_data mcf5485_flash_data = {
.width = 2,
};
static struct resource mcf5485_flash_resource = {
.start = 0xf8000000,
.end = 0xf80fffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device mcf5485_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &mcf5485_flash_data,
},
.num_resources = 1,
.resource = &mcf5485_flash_resource,
};
#endif
static int __init mcf5485_init_devices(void)
{
printk(KERN_INFO "MCF5485x INIT_DEVICES\n");
platform_device_register(&coldfire_i2c_device);
platform_device_register(&coldfire_sec_device);
platform_device_register(&s1d13xxxfb_device);
/*#if defined(CONFIG_MTD_PHYSMAP)
platform_device_register(&mcf5485_flash_device);
#endif*/
return 0;
}
arch_initcall(mcf5485_init_devices);
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04onColdfire running 2.6.25)
2008-11-11 15:04 ` Hinko Kocevar
@ 2008-11-11 16:10 ` jkimble
2008-11-12 8:25 ` Hinko Kocevar
2008-11-11 18:52 ` Seg fault on any FB write (Epson S1D13A04on Coldfire " Kristoffer Ericson
1 sibling, 1 reply; 18+ messages in thread
From: jkimble @ 2008-11-11 16:10 UTC (permalink / raw)
To: Hinko Kocevar; +Cc: linux-fbdev-devel
I thought it looked OK because it looks the same as the flexCAN stuff.
However I just noticed that flexCAN has a .0 and .1 whereas the s1d13 are
both .0. Yeah, I hope an expert weighs in on this because I'm not sure
now.
I didn't get your attachement.
Thanks for your help!
> jkimble@one.net wrote:
>>> James Kimble wrote:
>>
>> /proc/iomem shows:
>>
>> 74000000-74009000 : s1d13a04fb.0
>> 74000000-74009000 : s1d13xxxfb regs
>> 74040000-74068000 : s1d13a04fb.0
>> 74040000-74068000 : s1d13xxxfb mem
>
> I'm not sure if this is correct - two drivers mapped the same region twice
> !?
> Maybe the experts will shed some light on this..
>
>> f000070c-f000070c : spi-int-mask
>> f0000740-f000075f : spi-int-level
>> f0000a50-f0000a50 : spi-par
>> f0008a00-f0008ab8 : spi-module
>> f0008f00-f0008f20 : MCF548X-i2c
>> f000a000-f000a7ff : mcf548x-flexcan.0
>> f000a000-f000a7ff : mcf548x-flexcan
>> f000a800-f000afff : mcf548x-flexcan.1
>> f000a800-f000afff : mcf548x-flexcan
>> f0020000-f0033000 : fsl-sec1
>> fc000000-ffffffff : physmap-flash.0
>>
>
> I haven't took a long look at your driver, but here is our driver for
> S13706FB that
> we use on our embedded platform. Hope it helps.
>
> Regards,
> Hinko
> --
> Hinko Kočevar, OSS developer
> ČETRTA POT, d.o.o.
> Planina 3, 4000 Kranj, SI EU
> tel ++386 (0) 4 280 66 03
> e-mail hinko.kocevar@cetrtapot.si
> http www.cetrtapot.si
>
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04onColdfire running 2.6.25)
2008-11-11 18:52 ` Seg fault on any FB write (Epson S1D13A04on Coldfire " Kristoffer Ericson
@ 2008-11-11 18:02 ` jkimble
2008-11-11 19:14 ` Kristoffer Ericson
2008-11-12 8:34 ` Seg fault on any FB write (Epson S1D13A04on Coldfire " Hinko Kocevar
1 sibling, 1 reply; 18+ messages in thread
From: jkimble @ 2008-11-11 18:02 UTC (permalink / raw)
To: Kristoffer Ericson; +Cc: linux-fbdev-devel
Sorry, I was hacking around just to get something to work. If you look at
the two side by side you'll see that I've not changed that much. The
changes are mostly just plugging in my specific info for the panel I'm
using.
I've not worked with patches much so I'll have to figure out how to do that.
> On Tue, 11 Nov 2008 16:04:03 +0100
> Hinko Kocevar <hinko.kocevar@cetrtapot.si> wrote:
>
>> jkimble@one.net wrote:
>> >> James Kimble wrote:
>> >
>> > /proc/iomem shows:
>> >
>> > 74000000-74009000 : s1d13a04fb.0
>> > 74000000-74009000 : s1d13xxxfb regs
>> > 74040000-74068000 : s1d13a04fb.0
>> > 74040000-74068000 : s1d13xxxfb mem
>>
>> I'm not sure if this is correct - two drivers mapped the same region
>> twice !?
>> Maybe the experts will shed some light on this..
>>
>> > f000070c-f000070c : spi-int-mask
>> > f0000740-f000075f : spi-int-level
>> > f0000a50-f0000a50 : spi-par
>> > f0008a00-f0008ab8 : spi-module
>> > f0008f00-f0008f20 : MCF548X-i2c
>> > f000a000-f000a7ff : mcf548x-flexcan.0
>> > f000a000-f000a7ff : mcf548x-flexcan
>> > f000a800-f000afff : mcf548x-flexcan.1
>> > f000a800-f000afff : mcf548x-flexcan
>> > f0020000-f0033000 : fsl-sec1
>> > fc000000-ffffffff : physmap-flash.0
>> >
>>
>> I haven't took a long look at your driver, but here is our driver for
>> S13706FB that
>> we use on our embedded platform. Hope it helps.
>
> Any chance of getting a patch against s1d13xxxfb?
>
>>
>> Regards,
>> Hinko
>> --
>> Hinko Kočevar, OSS developer
>> ČETRTA POT, d.o.o.
>> Planina 3, 4000 Kranj, SI EU
>> tel ++386 (0) 4 280 66 03
>> e-mail hinko.kocevar@cetrtapot.si
>> http www.cetrtapot.si
>>
>>
>> -------------------------------------------------------------------------
>> This SF.Net email is sponsored by the Moblin Your Move Developer's
>> challenge
>> Build the coolest Linux based applications with Moblin SDK & win great
>> prizes
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>
>
> --
> Kristoffer Ericson <kristoffer.ericson@gmail.com>
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04onColdfire running 2.6.25)
2008-11-11 19:14 ` Kristoffer Ericson
@ 2008-11-11 18:20 ` jkimble
2008-11-11 19:29 ` Kristoffer Ericson
0 siblings, 1 reply; 18+ messages in thread
From: jkimble @ 2008-11-11 18:20 UTC (permalink / raw)
To: Kristoffer Ericson; +Cc: linux-fbdev-devel
[-- Attachment #1: Type: text/plain, Size: 3473 bytes --]
The 2.6.10 driver is considerably different. There's no platform device
structure. I tried taking the 2.6.10 forward to the 2.6.25 kernel but
found so many differences I thought getting the 2.6.25 driver working
would be easier.
Again, I've never made a patch for it. I've attached the actual driver
code here.
Not to make excuses (but here I go) this is the first foray I've made into
the kernel in any real way so I'm still figuring out the right way to do
things (after I get them to work at all).
Thanks again.
> On Tue, 11 Nov 2008 13:02:11 -0500 (EST)
> jkimble@one.net wrote:
>
>>
>> Sorry, I was hacking around just to get something to work. If you look
>> at
>> the two side by side you'll see that I've not changed that much. The
>> changes are mostly just plugging in my specific info for the panel I'm
>> using.
>>
>> I've not worked with patches much so I'll have to figure out how to do
>> that.
>
> Perhaps you should include the old patch to 2.6.10 since
> we know that worked and take it from there? In theory
> all you should need are the basic mappings and
> perhaps and reg init structure.
>
>>
>>
>> > On Tue, 11 Nov 2008 16:04:03 +0100
>> > Hinko Kocevar <hinko.kocevar@cetrtapot.si> wrote:
>> >
>> >> jkimble@one.net wrote:
>> >> >> James Kimble wrote:
>> >> >
>> >> > /proc/iomem shows:
>> >> >
>> >> > 74000000-74009000 : s1d13a04fb.0
>> >> > 74000000-74009000 : s1d13xxxfb regs
>> >> > 74040000-74068000 : s1d13a04fb.0
>> >> > 74040000-74068000 : s1d13xxxfb mem
>> >>
>> >> I'm not sure if this is correct - two drivers mapped the same region
>> >> twice !?
>> >> Maybe the experts will shed some light on this..
>> >>
>> >> > f000070c-f000070c : spi-int-mask
>> >> > f0000740-f000075f : spi-int-level
>> >> > f0000a50-f0000a50 : spi-par
>> >> > f0008a00-f0008ab8 : spi-module
>> >> > f0008f00-f0008f20 : MCF548X-i2c
>> >> > f000a000-f000a7ff : mcf548x-flexcan.0
>> >> > f000a000-f000a7ff : mcf548x-flexcan
>> >> > f000a800-f000afff : mcf548x-flexcan.1
>> >> > f000a800-f000afff : mcf548x-flexcan
>> >> > f0020000-f0033000 : fsl-sec1
>> >> > fc000000-ffffffff : physmap-flash.0
>> >> >
>> >>
>> >> I haven't took a long look at your driver, but here is our driver for
>> >> S13706FB that
>> >> we use on our embedded platform. Hope it helps.
>> >
>> > Any chance of getting a patch against s1d13xxxfb?
>> >
>> >>
>> >> Regards,
>> >> Hinko
>> >> --
>> >> Hinko KoÄevar, OSS developer
>> >> ÄŒETRTA POT, d.o.o.
>> >> Planina 3, 4000 Kranj, SI EU
>> >> tel ++386 (0) 4 280 66 03
>> >> e-mail hinko.kocevar@cetrtapot.si
>> >> http www.cetrtapot.si
>> >>
>> >>
>> >> -------------------------------------------------------------------------
>> >> This SF.Net email is sponsored by the Moblin Your Move Developer's
>> >> challenge
>> >> Build the coolest Linux based applications with Moblin SDK & win
>> great
>> >> prizes
>> >> Grand prize is a trip for two to an Open Source event anywhere in the
>> >> world
>> >> http://moblin-contest.org/redirect.php?banner_id=100&url=/
>> >> _______________________________________________
>> >> Linux-fbdev-devel mailing list
>> >> Linux-fbdev-devel@lists.sourceforge.net
>> >> https://lists.sourceforge.net/lists/listinfo/linux-fbdev-devel
>> >
>> >
>> > --
>> > Kristoffer Ericson <kristoffer.ericson@gmail.com>
>> >
>>
>>
>
>
> --
> Kristoffer Ericson <kristoffer.ericson@gmail.com>
>
[-- Attachment #2: s1d13a0x.h --]
[-- Type: application/octet-stream, Size: 4681 bytes --]
/*==================================================================
** Generic Header information generated by 13A04CFG.EXE (Build 155)
** Copyright (c) 2000,2001 Epson Research and Development, Inc.
** All rights reserved.
**
** Panel: 320x240x8bpp 70Hz Color 8-Bit STN, Format 2 (PCLK=6.250MHz)
**
** This file defines the configuration environment and registers,
** which can be used by any software, such as display drivers.
**
** Note: If you transfer this file to any non-PC system, use ASCII
** mode (not BINARY) to maintain system-specific line terminators.
**==================================================================*/
#define S1D_13A04
#define S1D_DISPLAY_WIDTH 320
#define S1D_DISPLAY_HEIGHT 240
#define S1D_DISPLAY_BPP 8
#define S1D_DISPLAY_SCANLINE_BYTES 320
#define S1D_DISPLAY_FRAME_RATE 70
#define S1D_DISPLAY_PCLK 6250000L
#define S1D_PHYSICAL_REG_ADDR 0x44000000L
#define S1D_PHYSICAL_BLT_ADDR 0x44050000L
#define S1D_PHYSICAL_VMEM_ADDR 0x44040000L
#define S1D_PHYSICAL_REG_SIZE 36864L
#define S1D_PHYSICAL_VMEM_SIZE 163840L
#define S1D_PHYSICAL_VMEM_REQUIRED 76800L
#define S1D_PALETTE_SIZE 256
#define S1D_POWER_DELAY_OFF 1200
#define S1D_POWER_DELAY_ON 50
#define S1D_HWBLT
#define S1D_SWBLT
#define S1D_REGRESERVED 0xF0
#define S1D_REGDELAYOFF 0xFD
#define S1D_REGDELAYON 0xFE
#define S1D_WRITE_PALETTE(p,i,r,g,b) \
(((volatile S1D_VALUE*)(p))[0x18/sizeof(S1D_VALUE)] = (S1D_VALUE)(i)<<24 | (S1D_VALUE)(r)<<16 | (S1D_VALUE)(g)<<8 | (b))
#define S1D_READ_PALETTE(p,i,r,g,b) \
{ \
S1D_VALUE reg; \
((volatile S1D_VALUE*)(p))[0x1C/sizeof(S1D_VALUE)] = (S1D_VALUE)(i)<<24; \
reg = ((volatile S1D_VALUE*)(p))[0x1C/sizeof(S1D_VALUE)]; \
(r) = (reg>>16)&0xFF; \
(g) = (reg>>8)&0xFF; \
(b) = reg&0xFF; \
}
typedef unsigned char S1D_INDEX;
typedef unsigned long S1D_VALUE;
typedef unsigned char VMEM_VALUE;
typedef struct
{
S1D_INDEX Index;
S1D_VALUE Value;
} S1D_REGS;
#define S1D_INSTANTIATE_REGISTERS(scope_prefix,variable_name) \
scope_prefix S1D_REGS variable_name[] = \
{ \
{0x14, 0x00000000}, /* Power Save Configuration Register */ \
{0x64, 0x00000000}, /* GPIO Status and Control Register */ \
{0x04, 0x00000000}, /* Memory Clock Configuration Register */ \
{0x08, 0x00000032}, /* Pixel Clock Configuration Register */ \
{0x0C, 0x000000D0}, /* Panel Type and MOD Rate Register */ \
{0x10, 0x00800008}, /* Display Settings Register */ \
{0x20, 0x0000002B}, /* Horizontal Total Register */ \
{0x24, 0x00000027}, /* Horiz Display Period Register */ \
{0x28, 0x00000000}, /* Horiz Display Period Start Position Register */ \
{0x2C, 0x00870156}, /* FPLINE Register */ \
{0x30, 0x000000FA}, /* Vert Total Register */ \
{0x34, 0x000000EF}, /* Vert Display Period Register */ \
{0x38, 0x00000000}, /* Vert Display Period Start Position Register */ \
{0x3C, 0x00800000}, /* FPFRAME Register */ \
{0x40, 0x00000000}, /* Main Window Display Start Address Register */ \
{0x44, 0x00000050}, /* Main Window Line Address Offset Register */ \
{0x50, 0x00000000}, /* PIP+ Window Display Start Address Register */ \
{0x54, 0x00000050}, /* PIP+ Window Line Address Offset Register */ \
{0x58, 0x00000000}, /* PIP+ Window X Positions Register */ \
{0x5C, 0x00000000}, /* PIP+ Window Y Positions Register */ \
{0x60, 0x00000000}, /* Special Purpose Register */ \
{0x70, 0x00000001}, /* PWM Clock Configuration Register */ \
{0x74, 0x00000010}, /* PWMOUT Duty Cycle Register */ \
{0x80, 0x00000000}, /* Scratch Pad A Register */ \
{0x84, 0x00000000}, /* Scratch Pad B Register */ \
{0x88, 0x00000000}, /* Scratch Pad C Register */ \
{0x64, 0x08060000}, /* GPIO Status and Control Register */ \
{0x14, 0x00000000}, /* Power Save Configuration Register */ \
}
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #3: s1d13xxxfb.c --]
[-- Type: text/x-csrc; name="s1d13xxxfb.c", Size: 26146 bytes --]
//-----------------------------------------------------------------------------
//
// linux/drivers/video/epson/s1d13xxxfb.c -- frame buffer driver for Epson
// S1D13xxx series of LCD/CRT/TV controllers.
//
// Copyright(c) Seiko Epson Corporation 2000-2005.
// All rights reserved.
//
// This file is subject to the terms and conditions of the GNU General Public
// License. See the file COPYING in the main directory of this archive for
// more details.
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//
// WARNING: This file uses a chip specific include file. The include file
// contains all hardware information needed to generate proper timings, color
// depth, screen resolution etc.
//
// This driver supports one of the following Epson CRT/TV/LCD controllers:
//
// S1D13706
// S1D13717
// S1D13A05
//
//-----------------------------------------------------------------------------
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/smp_lock.h>
#include "s1d13xxxfb.h"
#include "palette.h"
// S1D13706
#ifdef CONFIG_FBCON_EPSON_S1D13706
#endif
// S1D13717
#ifdef CONFIG_FBCON_EPSON_S1D13717
S1D_INSTANTIATE_REGISTERS(static,aS1DRegs);
#ifdef CONFIG_FBCON_EPSON_RAM_BASED_LCD
#include "s1d13xxxlcd.h"
LCD_INSTANTIATE_REGISTERS(static,aLCDRegs);
#endif
#endif
// S1D13A05
#ifdef CONFIG_FBCON_EPSON_S1D13A05
S1D_INSTANTIATE_REGISTERS(static,aS1DRegs);
#endif
#ifdef CONFIG_FBCON_EPSON_INDIRECT
#include <linux/timer.h>
#include "s1d13xxxfb_indirect.h"
#endif
#ifdef CONFIG_FBCON_EPSON_USB
#include "s1d13xxxfb_usb.h"
#endif
//-----------------------------------------------------------------------------
//
// Local Definitions
//
//---------------------------------------------------------------------------
typedef struct
{
unsigned char *VmemAddr;
volatile unsigned char *RegAddr;
#ifdef CONFIG_FBCON_EPSON_PCI
u32 PhysAddr;
#endif
#ifdef CONFIG_FBCON_EPSON_INDIRECT
void* fb;
u32 VirtualVmemAddr;
#endif
#ifdef CONFIG_FBCON_EPSON_2D
volatile u16* BltAddr;
#endif
u32 pseudo_palette[16];
}FB_INFO_S1D13xxx;
#ifdef CONFIG_FBCON_EPSON_RAM_BASED_LCD
#define LOOP_LIMIT 1000 // to prevent endless loop
#endif
#if defined(CONFIG_FBCON_EPSON_RAM_BASED_LCD) || defined(CONFIG_FBCON_EPSON_INDIRECT)
// This is the refresh period for updating the display for RAM based LCDs
// and/or indirect interfaces. It is set to (1 second / X). This value can
// modified by the end-user. Be aware that decreasing the refresh period
// increases CPU usage as well.
#define VIDEO_REFRESH_PERIOD HZ/40
#endif
// Some chipset header files do not have S1D_REGDELAYPLL defined. Use the S1D_REGDELAYON to
// simulate it.
#ifndef S1D_REGDELAYPLL
#define S1D_REGDELAYPLL S1D_REGDELAYON
#endif
#ifdef CONFIG_FBCON_EPSON_2D
// BitBlit data reg address
#define REG10000_BLT_DATA 0x10000
#endif
//-----------------------------------------------------------------------------
//
// Function Prototypes
//
//-----------------------------------------------------------------------------
int __init s1d13xxxfb_setup(char *options, int *ints);
int __init s1d13xxxfb_init(char*);
unsigned long __init s1d13xxxfb_get_physical_address(void);
static int s1d13xxxfb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info);
static int s1d13xxxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
static int s1d13xxxfb_set_par(struct fb_info *info);
#ifdef CONFIG_FBCON_EPSON_INDIRECT
static int s1d13xxxfb_mmap( struct fb_info *fb, struct file *file, struct vm_area_struct *vma );
static int s1d13xxxfb_set_virtual_vmem(void);
static void s1d13xxxfb_flush_virtual_vmem(void);
#endif
#ifdef CONFIG_FBCON_EPSON_RAM_BASED_LCD
void s1d13xxxfb_transfer_frame(void);
#endif
#if defined(CONFIG_FBCON_EPSON_RAM_BASED_LCD) || defined(CONFIG_FBCON_EPSON_INDIRECT)
void s1d13xxx_refresh_display( unsigned long dummy );
#endif
#ifdef CONFIG_FBCON_EPSON_CLOCK_CHIP
extern int s1d13xxxfb_SetClock(void);
#endif
// 2D HW accelerated functions
#ifdef CONFIG_FBCON_EPSON_2D
extern void s1d13xxxfb_2DEngineInit( volatile u16* bltDataAddr, struct fb_info *info, struct fb_ops *ops );
extern void s1d13xxxfb_fillrect (struct fb_info *info, const struct fb_fillrect *rect);
extern void s1d13xxxfb_copyarea (struct fb_info *info, const struct fb_copyarea *region);
extern void s1d13xxxfb_imageblit (struct fb_info *info, const struct fb_image *image);
extern int s1d13xxxfb_sync (struct fb_info *info );
#endif
//-----------------------------------------------------------------------------
//
// Local globals
//
//-----------------------------------------------------------------------------
static struct fb_ops s1d13xxxfb_ops =
{
.owner = THIS_MODULE,
.fb_set_par = s1d13xxxfb_set_par,
.fb_check_var = s1d13xxxfb_check_var,
.fb_setcolreg = s1d13xxxfb_setcolreg,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_cursor = soft_cursor,
#ifdef CONFIG_FBCON_EPSON_INDIRECT
.fb_mmap = s1d13xxxfb_mmap,
#endif
};
static struct fb_fix_screeninfo s1d13xxxfb_fix __initdata =
{
.id = "s1d13xxx",
.type = FB_TYPE_PACKED_PIXELS,
.type_aux = 0,
.xpanstep = 0,
.ypanstep = 0,
.ywrapstep = 0,
.mmio_len = S1D_PHYSICAL_REG_SIZE,
.smem_len = S1D_PHYSICAL_VMEM_SIZE,
.line_length = S1D_DISPLAY_SCANLINE_BYTES,
#ifndef CONFIG_FBCON_EPSON_2D
.accel = FB_ACCEL_NONE,
#else
.accel = FB_ACCEL_EPSON_S1D13XXX,
#endif
};
static struct fb_info s1d13xxx_fb;
static FB_INFO_S1D13xxx s1d13xxx_info;
#if defined(CONFIG_FBCON_EPSON_RAM_BASED_LCD) || defined(CONFIG_FBCON_EPSON_INDIRECT)
struct timer_list s1d13xxx_timer;
#endif
//----------------------------------------------------------------------------
//
// Set a single color register. The values supplied have a 16 bit
// magnitude.
// Return != 0 for invalid regno.
//
// We get called even if we specified that we don't have a programmable palette
// or in direct/true color modes!
//----------------------------------------------------------------------------
static int s1d13xxxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *info)
{
if (regno >= S1D_PALETTE_SIZE)
return 1;
#ifdef CONFIG_FBCON_EPSON_INDIRECT
S1D_INDIRECT_WRITE_PALETTE(regno,red>>8,green>>8,blue>>8);
#else
S1D_WRITE_PALETTE(s1d13xxx_info.RegAddr,regno,red>>8,green>>8,blue>>8);
#endif
switch (info->var.bits_per_pixel) {
case 16:
if (regno < 16)
{ /* RGB 565 */
((u32*)info->pseudo_palette)[regno] =
(red & 0xf800)|((green & 0xfc00) >> 5)|((blue & 0xf800) >> 11);
}
break;
case 32:
if (regno < 16)
{ /* RGB 888 */
red >>= 8;
green >>= 8;
blue >>= 8;
((u32*)info->pseudo_palette)[regno] = (red << 16) | (green << 8) | (blue);
}
break;
}
return 0;
}
//-----------------------------------------------------------------------------
//
// Fill in the 'var' and 'fix' structure.
//
//-----------------------------------------------------------------------------
static int s1d13xxxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
var->xres = S1D_DISPLAY_WIDTH;
var->yres = S1D_DISPLAY_HEIGHT;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
var->xoffset = var->yoffset = 0;
var->bits_per_pixel = S1D_DISPLAY_BPP;
var->grayscale = 0;
var->nonstd = 0; /* != 0 Non standard pixel format */
var->activate = FB_ACTIVATE_NOW; /* see FB_ACTIVATE_* */
var->height = -1; /* height of picture in mm */
var->width = -1; /* width of picture in mm */
var->accel_flags = 0; /* acceleration flags (hints */
var->pixclock = S1D_DISPLAY_PCLK;
var->right_margin = 0;
var->lower_margin = 0;
var->hsync_len = 0;
var->vsync_len = 0;
var->left_margin = 0;
var->upper_margin = 0;
var->sync = 0;
var->vmode = FB_VMODE_NONINTERLACED;
var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
var->transp.offset = var->transp.length = var->transp.msb_right = 0;
// switch (info->var.bits_per_pixel)
switch (S1D_DISPLAY_BPP)
{
case 1:
case 2:
case 4:
case 8:
var->red.offset = var->green.offset = var->blue.offset = 0;
var->red.length = var->green.length = var->blue.length = S1D_DISPLAY_BPP;
s1d13xxxfb_fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 16:
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
s1d13xxxfb_fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 32:
var->red.length = var->green.length = var->blue.length = 8;
var->blue.offset = 0;
var->green.offset = 8;
var->red.offset = 16;
var->transp.offset = 24;
var->transp.length = 8;
s1d13xxxfb_fix.visual = FB_VISUAL_TRUECOLOR;
break;
default:
printk( KERN_WARNING "%dbpp is not supported.\n",
info->var.bits_per_pixel );
return -EINVAL;
}
return 0;
}
//-----------------------------------------------------------------------------
//
// Set the hardware.
//
//-----------------------------------------------------------------------------
static int s1d13xxxfb_set_par(struct fb_info *info)
{
info->fix = s1d13xxxfb_fix;
#ifdef CONFIG_FBCON_EPSON_PCI
#ifdef CONFIG_FBCON_EPSON_INDIRECT
info->fix.smem_start = virt_to_phys((void *)s1d13xxx_info.VirtualVmemAddr);
info->fix.mmio_start = s1d13xxx_info.PhysAddr; // This address is not used in indirect mode
info->screen_base = (unsigned char*)s1d13xxx_info.VirtualVmemAddr;
#else
info->fix.smem_start = (u32)(s1d13xxx_info.PhysAddr+0x200000);
info->fix.mmio_start = (u32)s1d13xxx_info.RegAddr;
info->screen_base = s1d13xxx_info.VmemAddr;
#endif
#else
#ifdef CONFIG_FBCON_EPSON_INDIRECT
info->fix.smem_start = virt_to_phys((void *)s1d13xxx_info.VirtualVmemAddr);
info->fix.mmio_start = S1D_PHYSICAL_REG_ADDR; // This address is not used in indirect mode
info->screen_base = (unsigned char*)s1d13xxx_info.VirtualVmemAddr;
#else
info->fix.smem_start = (u32)S1D_PHYSICAL_VMEM_ADDR;
info->fix.mmio_start = (u32)S1D_PHYSICAL_REG_ADDR;
info->screen_base = s1d13xxx_info.VmemAddr;
#endif
#endif
#if defined(CONFIG_FBCON_EPSON_RAM_BASED_LCD) || defined(CONFIG_FBCON_EPSON_INDIRECT)
// Set timer to trigger a refresh of the display
s1d13xxx_timer.expires = jiffies+VIDEO_REFRESH_PERIOD;
add_timer(&s1d13xxx_timer);
#endif
return 0;
}
#ifdef CONFIG_FBCON_EPSON_INDIRECT
//----------------------------------------------------------------------------
//
// Remaps virtual/shadow video memory buffer from virtual mem space to a physical space
//----------------------------------------------------------------------------
static int s1d13xxxfb_mmap( struct fb_info *fb, struct file *file, struct vm_area_struct *vma )
{
vma->vm_flags |= VM_RESERVED;
if( remap_page_range( vma, vma->vm_start, virt_to_phys( (void*)s1d13xxx_info.VirtualVmemAddr ),
vma->vm_end - vma->vm_start, vma->vm_page_prot ) )
return -EINVAL;
// NOTE: remap_page_range will be deprecated in kernel 2.6.11. The replacement function,
// remap_pfn_range(), is not introduced until 2.6.10. This code is written for 2.6.8.
return 0;
}
//----------------------------------------------------------------------------
//
// Allocates virtual video memory buffer to be used with the indirect interface
//----------------------------------------------------------------------------
static int s1d13xxxfb_set_virtual_vmem(void)
{
u32 order = 0;
u32 size = S1D_DISPLAY_WIDTH*S1D_DISPLAY_HEIGHT;
u32 addr;
while ( size > (PAGE_SIZE * (1 << order)))
order++;
s1d13xxx_info.VirtualVmemAddr = __get_free_pages( GFP_KERNEL, order );
if( s1d13xxx_info.VirtualVmemAddr==0 )
return 1;
for( addr=s1d13xxx_info.VirtualVmemAddr; addr<(s1d13xxx_info.VirtualVmemAddr+size); addr+=PAGE_SIZE )
SetPageReserved( virt_to_page( addr ) );
return 0;
}
//----------------------------------------------------------------------------
// PRIVATE FUNCTION:
// Flushes the virtual frame buffer to the display frame buffer via Indirect interface
//----------------------------------------------------------------------------
static void s1d13xxxfb_flush_virtual_vmem( void )
{
u32 size = S1D_DISPLAY_WIDTH*S1D_DISPLAY_HEIGHT;
S1D_VALUE* pSource = (S1D_VALUE*) s1d13xxx_info.VirtualVmemAddr;;
u32 pDest = 0;
// Copy virtual vmem buffer to vmem via indirect interface burst mode write
s1d13xxxfb_IndirectWriteData( pDest, pSource, size );
}
#endif // CONFIG_FBCON_EPSON_INDIRECT
#ifdef CONFIG_FBCON_EPSON_RAM_BASED_LCD
//----------------------------------------------------------------------------
// PRIVATE FUNCTION:
// Triggers a transfer of 1 frame of data to the LCD interface
//----------------------------------------------------------------------------
void s1d13xxxfb_transfer_frame( void )
{
u16 timeout=LOOP_LIMIT;
while( ( s1d13xxxfb_read_reg(REG0038_LCDINTSTATUS) & 0x0001 ) && timeout--);
{
// transfer one frame
s1d13xxxfb_write_reg(REG003A_LCDINTFRAMEXFER, 0x0001);
}
}
#endif
#if defined(CONFIG_FBCON_EPSON_RAM_BASED_LCD) || defined(CONFIG_FBCON_EPSON_INDIRECT)
//----------------------------------------------------------------------------
// PRIVATE FUNCTION:
// This function updates the display
//----------------------------------------------------------------------------
void s1d13xxx_refresh_display( unsigned long dummy )
{
#ifdef CONFIG_FBCON_EPSON_INDIRECT
// Copy virtual vmem buffer to display vmem with indirect interface
s1d13xxxfb_flush_virtual_vmem();
#endif
#ifdef CONFIG_FBCON_EPSON_RAM_BASED_LCD
// Transfer frame to LCD
s1d13xxxfb_transfer_frame();
#endif
// Reset the timer
s1d13xxx_timer.expires = jiffies+VIDEO_REFRESH_PERIOD;
add_timer(&s1d13xxx_timer);
}
#endif
//----------------------------------------------------------------------------
// Writes S1D_VALUE-sized value to register
//----------------------------------------------------------------------------
void s1d13xxxfb_write_reg(u32 reg, S1D_VALUE val)
{
#ifdef CONFIG_FBCON_EPSON_INDIRECT
s1d13xxxfb_IndirectWriteReg(reg, val);
#else
((S1D_VALUE*)s1d13xxx_info.RegAddr)[reg/sizeof(S1D_VALUE)] = val;
#endif
}
//----------------------------------------------------------------------------
// Writes 16-bit value to register
//----------------------------------------------------------------------------
void s1d13xxxfb_write_reg16(u32 reg, u16 val)
{
#ifdef CONFIG_FBCON_EPSON_INDIRECT
s1d13xxxfb_IndirectWriteReg(reg, val);
#else
((u16*)s1d13xxx_info.RegAddr)[reg/sizeof(u16)] = val;
#endif
}
//----------------------------------------------------------------------------
// Writes 8-bit value to register
//----------------------------------------------------------------------------
void s1d13xxxfb_write_reg8(u32 reg, u8 val)
{
#ifdef CONFIG_FBCON_EPSON_INDIRECT
s1d13xxxfb_IndirectWriteReg(reg, val);
#else
((u8*)s1d13xxx_info.RegAddr)[reg/sizeof(u8)] = val;
#endif
}
//----------------------------------------------------------------------------
// Reads S1D_VALUE-sized value from register
//----------------------------------------------------------------------------
S1D_VALUE s1d13xxxfb_read_reg(u32 reg)
{
#ifdef CONFIG_FBCON_EPSON_INDIRECT
return (S1D_VALUE)s1d13xxxfb_IndirectReadReg(reg);
#else
return ((S1D_VALUE*)s1d13xxx_info.RegAddr)[reg/sizeof(S1D_VALUE)];
#endif
}
//----------------------------------------------------------------------------
// Reads 16-bit value from register
//----------------------------------------------------------------------------
u16 s1d13xxxfb_read_reg16(u32 reg)
{
#ifdef CONFIG_FBCON_EPSON_INDIRECT
return (u16)s1d13xxxfb_IndirectReadReg(reg);
#else
return ((u16*)s1d13xxx_info.RegAddr)[reg/sizeof(u16)];
#endif
}
//----------------------------------------------------------------------------
// Reads 16-bit value from register
//----------------------------------------------------------------------------
u8 s1d13xxxfb_read_reg8(u32 reg)
{
#ifdef CONFIG_FBCON_EPSON_INDIRECT
return (u8)s1d13xxxfb_IndirectReadReg(reg);
#else
return ((u8*)s1d13xxx_info.RegAddr)[reg/sizeof(u8)];
#endif
}
//-----------------------------------------------------------------------------
//
// Detect our PCI bridge adapter card, get the BAR[0]. Card is assumed to be
// enabled.
//
//-----------------------------------------------------------------------------
#ifdef CONFIG_FBCON_EPSON_PCI
static int __init
s1d13xxx_IsOurID(unsigned vID, unsigned dID)
{
if (vID == 0x10F4 && dID == 0x1300)
return 1;
if (vID == 0x14EB)
{
if (dID >= 0x0000 && dID < 0x002A)
return 1;
if (dID > 0x002A && dID <= 0x002F)
return 1;
}
return 0;
}
unsigned long __init s1d13xxxfb_get_physical_address(void)
{
struct pci_dev *pdev;
pdev = NULL;
for(pdev = pci_dev_g(pci_devices.next); pdev != pci_dev_g(&pci_devices); pdev = pci_dev_g(pdev->global_list.next))
{
if (s1d13xxx_IsOurID(pdev->vendor,pdev->device))
return (pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK);
}
return 0;
}
#endif
//-----------------------------------------------------------------------------
// Initialize the chip and the frame buffer driver.
//-----------------------------------------------------------------------------
int __init s1d13xxxfb_init(char *dummy)
{
int i;
char pixel;
S1D_INDEX s1dReg;
S1D_VALUE s1dValue;
#ifdef CONFIG_FBCON_EPSON_RAM_BASED_LCD
int timeout = LOOP_LIMIT;
#endif
#ifdef CONFIG_FBCON_EPSON_PCI
unsigned long phAddr = s1d13xxxfb_get_physical_address();
s1d13xxx_info.RegAddr = (unsigned char*) ioremap(phAddr,S1D_PHYSICAL_REG_SIZE);
s1d13xxx_info.VmemAddr = (unsigned char*) ioremap_nocache(phAddr+0x200000,S1D_PHYSICAL_VMEM_SIZE);
s1d13xxx_info.PhysAddr = phAddr;
#ifdef CONFIG_FBCON_EPSON_2D
s1d13xxx_info.BltAddr = (u16*)ioremap(phAddr+REG10000_BLT_DATA+2,0x10000);
#endif
#else
s1d13xxx_info.RegAddr = (unsigned char*) ioremap(S1D_PHYSICAL_REG_ADDR,S1D_PHYSICAL_REG_SIZE);
s1d13xxx_info.VmemAddr = (unsigned char*) ioremap_nocache(S1D_PHYSICAL_VMEM_ADDR,S1D_PHYSICAL_VMEM_SIZE);
#ifdef CONFIG_FBCON_EPSON_2D
s1d13xxx_info.BltAddr = (u16*)ioremap(S1D_PHYSICAL_BLT_ADDR,0x10000);
#endif
#endif
if (!s1d13xxx_info.VmemAddr || !s1d13xxx_info.RegAddr)
{
printk("s1d13xxxfb_init: ioremap() returned NULL\n");
return -EINVAL;
}
#ifdef CONFIG_FBCON_EPSON_2D
if (!s1d13xxx_info.BltAddr)
{
printk("s1d13xxxfb_init: ioremap() for 2D space returned NULL\n");
return -EINVAL;
}
#endif
// Turn 2D BitBLT off
s1d13xxxfb_write_reg(0x8000, 0x00000000);
#ifdef CONFIG_FBCON_EPSON_INDIRECT
// Initialize the chip to use Indirect Interface
s1d13xxxfb_IndirectInit( (u32)s1d13xxx_info.RegAddr );
// Allocate the virtual video memory
if(s1d13xxxfb_set_virtual_vmem())
{
printk("s1d13xxxfb_init: _get_free_pages() failed.\n");
return -EINVAL;
}
#endif
#ifdef CONFIG_FBCON_EPSON_CLOCK_CHIP
// Program the chip clock for the S1D13A05 eval board
if( !s1d13xxxfb_SetClock() )
{
printk("s1d13xxxfb_init: cannot set clock chip\n");
return -EINVAL;
}
#endif
//-------------------------------------------------------------------------
// Set the controller registers and initialize LCD
//-------------------------------------------------------------------------
// initializing controller registers
for (i = 0; i < sizeof(aS1DRegs)/sizeof(aS1DRegs[0]); i++)
{
s1dReg = aS1DRegs[i].Index;
s1dValue = aS1DRegs[i].Value;
#ifdef CONFIG_FBCON_EPSON_RAM_BASED_LCD
if (s1dReg == REG0034_LCDINTCMD || s1dReg == REG0036_LCDINTPARAM)
{
timeout = LOOP_LIMIT;
while ((( s1d13xxxfb_read_reg(REG0038_LCDINTSTATUS) & 0x0001) != 0) && timeout--)
continue;
}
#endif
if ( s1dReg == S1D_REGDELAYOFF ||
s1dReg == S1D_REGDELAYON ||
s1dReg == S1D_REGDELAYPLL )
{
mdelay((int)s1dValue);
}
else
{
s1d13xxxfb_write_reg(s1dReg, s1dValue);
}
}
// initializing LCD
#ifdef CONFIG_FBCON_EPSON_RAM_BASED_LCD
for (i = 0; i < sizeof(aLCDRegs)/sizeof(aLCDRegs[0]); i++)
{
s1dReg = aLCDRegs[i].Index;
s1dValue = aLCDRegs[i].Value;
if (s1dReg == REG0034_LCDINTCMD || s1dReg == REG0036_LCDINTPARAM)
{
timeout= LOOP_LIMIT;
while ((( s1d13xxxfb_read_reg(REG0038_LCDINTSTATUS) & 0x0001) != 0) && timeout--)
continue;
}
if (s1dReg == S1D_REGDELAYOFF || s1dReg == S1D_REGDELAYON || s1dReg == S1D_REGDELAYPLL
)
mdelay((int)s1dValue);
else
s1d13xxxfb_write_reg(s1dReg, s1dValue);
}
#else
// Setup fb_info data structures
s1d13xxxfb_set_par(&s1d13xxx_fb);
// Intialize screen memory to uniform color
for ( i=0; i < ((S1D_DISPLAY_WIDTH*S1D_DISPLAY_HEIGHT)); i++)
{
((VMEM_VALUE *)s1d13xxx_info.VmemAddr)[i] = (unsigned int) 0x01;
}
#endif
//-------------------------------------------------------------------------
// Initialize USB
//-------------------------------------------------------------------------
#ifdef CONFIG_FBCON_EPSON_USB
s1d13xxxfb_USBInit();
#endif
// Set flags for controller supported features
s1d13xxx_fb.flags = FBINFO_FLAG_DEFAULT;
//-------------------------------------------------------------------------
// Initialize 2D graphics engine
//-------------------------------------------------------------------------
#ifdef CONFIG_FBCON_EPSON_2D
s1d13xxxfb_2DEngineInit(s1d13xxx_info.BltAddr, &s1d13xxx_fb, &s1d13xxxfb_ops);
#endif
// Set the pseudo palette
s1d13xxx_fb.pseudo_palette = s1d13xxx_info.pseudo_palette;
s1d13xxxfb_check_var(&s1d13xxx_fb.var, &s1d13xxx_fb);
s1d13xxx_fb.fbops = &s1d13xxxfb_ops;
s1d13xxx_fb.node = -1;
// Enable display
s1dValue = s1d13xxxfb_read_reg (0x10);
s1dValue &= 0xff7fffff;
s1d13xxxfb_write_reg(0x10, s1dValue);
#if defined(CONFIG_FBCON_EPSON_RAM_BASED_LCD) || defined(CONFIG_FBCON_EPSON_INDIRECT)
// Create a timer to trigger a refresh of the displaye
init_timer(&s1d13xxx_timer);
s1d13xxx_timer.function = s1d13xxx_refresh_display;
#endif
if (register_framebuffer(&s1d13xxx_fb) < 0)
return -EINVAL;
return 0;
}
//-----------------------------------------------------------------------------
// Parse user speficied options (`video=s1d13xxx:')
// Example:
// video=s1d13xxx:noaccel
//-----------------------------------------------------------------------------
int __init s1d13xxxfb_setup(char *options, int *ints)
{
return 0;
}
#ifdef MODULE
//--------------------------------------------------------------------------
//
// FUNCTION: init_module() (FILE: s1d13xxxfb.c)
//
// PURPOSE: Memset modularization
//
// REVISIONS:
//
// BY DATE CHANGE
// --- ---------- ------
// HJK 11/05/2007 Reformatted
//
//---------------------------------------------------------------------------
static int __init fb_init(void)
{
char * dummy;
s1d13xxxfb_init(dummy);
return 0;
}
//--------------------------------------------------------------------------
//
// FUNCTION: cleanup_module() (FILE: s1d13xxxfb.c)
//
// PURPOSE:
//
// REVISIONS:
//
// BY DATE CHANGE
// --- ---------- ------
// HJK 11/05/2007 Reformatted
//
//---------------------------------------------------------------------------
static void __exit fb_cleanup(void)
{
unregister_framebuffer(&s1d13xxx_fb);
}
module_init(fb_init);
module_exit(fb_cleanup);
#endif
MODULE_AUTHOR("Seiko Epson Corp");
MODULE_DESCRIPTION("Epson S1D13A04 driver");
MODULE_LICENSE("GPL");
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04 on Coldfire running 2.6.25)
2008-11-11 1:54 Seg fault on any FB write (Epson S1D13A04 on Coldfire running 2.6.25) James Kimble
2008-11-11 9:57 ` Hinko Kocevar
@ 2008-11-11 18:50 ` Kristoffer Ericson
1 sibling, 0 replies; 18+ messages in thread
From: Kristoffer Ericson @ 2008-11-11 18:50 UTC (permalink / raw)
To: James Kimble; +Cc: linux-fbdev-devel
[-- Attachment #1.1: Type: text/plain, Size: 1846 bytes --]
On Mon, 10 Nov 2008 20:54:11 -0500
James Kimble <jkimble@one.net> wrote:
>
> I've been working on porting the s1d13xxxfb driver from the latest
> kernel from Freescale for Coldfire to work with the S1D13A04 chip. I was
> able to get things working to the point that I do get a little TUX logo
> up on the screen at boot up. Seemed like a good start but none of my
> user space applications will work. I can open the /dev/fb0 device and
> the data in the info structure is correct but if I try to write to any
> register or area in the frame buffer (or write to the device at all) I
> get a seg fault.
Please drop me a mail with patch attached and I'll look at it,
you must have hit something nasty.
>
> I had an earlier driver working with the 2.6.10 kernel with the same
> hardware. The same application space program should work ( I would
> think...) but I get the seg fault on the first write to fb0. I tried a
> different memory location (ox4400 0000 to 0x7400 0000) for the CS
> associated with the video chip, no difference. Permissions for
> /dev/fb0 are "rw". No other process using fb0. This is really weird.
>
> Any help or suggestions MUCH appreciated.
>
> -------------------------------------------------------------------------
> This SF.Net email is sponsored by the Moblin Your Move Developer's challenge
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> _______________________________________________
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> https://lists.sourceforge.net/lists/listinfo/linux-fbdev-devel
--
Kristoffer Ericson <kristoffer.ericson@gmail.com>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04on Coldfire running 2.6.25)
2008-11-11 15:04 ` Hinko Kocevar
2008-11-11 16:10 ` Seg fault on any FB write (Epson S1D13A04onColdfire " jkimble
@ 2008-11-11 18:52 ` Kristoffer Ericson
2008-11-11 18:02 ` Seg fault on any FB write (Epson S1D13A04onColdfire " jkimble
2008-11-12 8:34 ` Seg fault on any FB write (Epson S1D13A04on Coldfire " Hinko Kocevar
1 sibling, 2 replies; 18+ messages in thread
From: Kristoffer Ericson @ 2008-11-11 18:52 UTC (permalink / raw)
To: Hinko Kocevar; +Cc: linux-fbdev-devel
[-- Attachment #1.1: Type: text/plain, Size: 1964 bytes --]
On Tue, 11 Nov 2008 16:04:03 +0100
Hinko Kocevar <hinko.kocevar@cetrtapot.si> wrote:
> jkimble@one.net wrote:
> >> James Kimble wrote:
> >
> > /proc/iomem shows:
> >
> > 74000000-74009000 : s1d13a04fb.0
> > 74000000-74009000 : s1d13xxxfb regs
> > 74040000-74068000 : s1d13a04fb.0
> > 74040000-74068000 : s1d13xxxfb mem
>
> I'm not sure if this is correct - two drivers mapped the same region twice !?
> Maybe the experts will shed some light on this..
>
> > f000070c-f000070c : spi-int-mask
> > f0000740-f000075f : spi-int-level
> > f0000a50-f0000a50 : spi-par
> > f0008a00-f0008ab8 : spi-module
> > f0008f00-f0008f20 : MCF548X-i2c
> > f000a000-f000a7ff : mcf548x-flexcan.0
> > f000a000-f000a7ff : mcf548x-flexcan
> > f000a800-f000afff : mcf548x-flexcan.1
> > f000a800-f000afff : mcf548x-flexcan
> > f0020000-f0033000 : fsl-sec1
> > fc000000-ffffffff : physmap-flash.0
> >
>
> I haven't took a long look at your driver, but here is our driver for S13706FB that
> we use on our embedded platform. Hope it helps.
Any chance of getting a patch against s1d13xxxfb?
>
> Regards,
> Hinko
> --
> Hinko Kočevar, OSS developer
> ČETRTA POT, d.o.o.
> Planina 3, 4000 Kranj, SI EU
> tel ++386 (0) 4 280 66 03
> e-mail hinko.kocevar@cetrtapot.si
> http www.cetrtapot.si
>
>
> -------------------------------------------------------------------------
> This SF.Net email is sponsored by the Moblin Your Move Developer's challenge
> Build the coolest Linux based applications with Moblin SDK & win great prizes
> Grand prize is a trip for two to an Open Source event anywhere in the world
> http://moblin-contest.org/redirect.php?banner_id=100&url=/
> _______________________________________________
> Linux-fbdev-devel mailing list
> Linux-fbdev-devel@lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/linux-fbdev-devel
--
Kristoffer Ericson <kristoffer.ericson@gmail.com>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04onColdfire running 2.6.25)
2008-11-11 18:02 ` Seg fault on any FB write (Epson S1D13A04onColdfire " jkimble
@ 2008-11-11 19:14 ` Kristoffer Ericson
2008-11-11 18:20 ` jkimble
0 siblings, 1 reply; 18+ messages in thread
From: Kristoffer Ericson @ 2008-11-11 19:14 UTC (permalink / raw)
To: jkimble; +Cc: linux-fbdev-devel
[-- Attachment #1.1: Type: text/plain, Size: 2835 bytes --]
On Tue, 11 Nov 2008 13:02:11 -0500 (EST)
jkimble@one.net wrote:
>
> Sorry, I was hacking around just to get something to work. If you look at
> the two side by side you'll see that I've not changed that much. The
> changes are mostly just plugging in my specific info for the panel I'm
> using.
>
> I've not worked with patches much so I'll have to figure out how to do that.
Perhaps you should include the old patch to 2.6.10 since
we know that worked and take it from there? In theory
all you should need are the basic mappings and
perhaps and reg init structure.
>
>
> > On Tue, 11 Nov 2008 16:04:03 +0100
> > Hinko Kocevar <hinko.kocevar@cetrtapot.si> wrote:
> >
> >> jkimble@one.net wrote:
> >> >> James Kimble wrote:
> >> >
> >> > /proc/iomem shows:
> >> >
> >> > 74000000-74009000 : s1d13a04fb.0
> >> > 74000000-74009000 : s1d13xxxfb regs
> >> > 74040000-74068000 : s1d13a04fb.0
> >> > 74040000-74068000 : s1d13xxxfb mem
> >>
> >> I'm not sure if this is correct - two drivers mapped the same region
> >> twice !?
> >> Maybe the experts will shed some light on this..
> >>
> >> > f000070c-f000070c : spi-int-mask
> >> > f0000740-f000075f : spi-int-level
> >> > f0000a50-f0000a50 : spi-par
> >> > f0008a00-f0008ab8 : spi-module
> >> > f0008f00-f0008f20 : MCF548X-i2c
> >> > f000a000-f000a7ff : mcf548x-flexcan.0
> >> > f000a000-f000a7ff : mcf548x-flexcan
> >> > f000a800-f000afff : mcf548x-flexcan.1
> >> > f000a800-f000afff : mcf548x-flexcan
> >> > f0020000-f0033000 : fsl-sec1
> >> > fc000000-ffffffff : physmap-flash.0
> >> >
> >>
> >> I haven't took a long look at your driver, but here is our driver for
> >> S13706FB that
> >> we use on our embedded platform. Hope it helps.
> >
> > Any chance of getting a patch against s1d13xxxfb?
> >
> >>
> >> Regards,
> >> Hinko
> >> --
> >> Hinko KoÄevar, OSS developer
> >> ÄŒETRTA POT, d.o.o.
> >> Planina 3, 4000 Kranj, SI EU
> >> tel ++386 (0) 4 280 66 03
> >> e-mail hinko.kocevar@cetrtapot.si
> >> http www.cetrtapot.si
> >>
> >>
> >> -------------------------------------------------------------------------
> >> This SF.Net email is sponsored by the Moblin Your Move Developer's
> >> challenge
> >> Build the coolest Linux based applications with Moblin SDK & win great
> >> prizes
> >> Grand prize is a trip for two to an Open Source event anywhere in the
> >> world
> >> http://moblin-contest.org/redirect.php?banner_id=100&url=/
> >> _______________________________________________
> >> Linux-fbdev-devel mailing list
> >> Linux-fbdev-devel@lists.sourceforge.net
> >> https://lists.sourceforge.net/lists/listinfo/linux-fbdev-devel
> >
> >
> > --
> > Kristoffer Ericson <kristoffer.ericson@gmail.com>
> >
>
>
--
Kristoffer Ericson <kristoffer.ericson@gmail.com>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04onColdfire running 2.6.25)
2008-11-11 18:20 ` jkimble
@ 2008-11-11 19:29 ` Kristoffer Ericson
0 siblings, 0 replies; 18+ messages in thread
From: Kristoffer Ericson @ 2008-11-11 19:29 UTC (permalink / raw)
To: jkimble; +Cc: linux-fbdev-devel
[-- Attachment #1.1: Type: text/plain, Size: 4186 bytes --]
On Tue, 11 Nov 2008 13:20:22 -0500 (EST)
jkimble@one.net wrote:
> The 2.6.10 driver is considerably different. There's no platform device
> structure. I tried taking the 2.6.10 forward to the 2.6.25 kernel but
> found so many differences I thought getting the 2.6.25 driver working
> would be easier.
I havent seen the 2.6.10 driver so you might be
right. Ive only recently taken over maintainership
so still working out the quirks.
>
> Again, I've never made a patch for it. I've attached the actual driver
> code here.
>
Roger, I'll take a look at it.
> Not to make excuses (but here I go) this is the first foray I've made into
> the kernel in any real way so I'm still figuring out the right way to do
> things (after I get them to work at all).
>
No worries. The best/easiest approach is to clone a copy
of linux-2.6.git (google for it). You then edit the file
in that directory and can generate diffs with 'git diff <filename>'.
> Thanks again.
>
>
> > On Tue, 11 Nov 2008 13:02:11 -0500 (EST)
> > jkimble@one.net wrote:
> >
> >>
> >> Sorry, I was hacking around just to get something to work. If you look
> >> at
> >> the two side by side you'll see that I've not changed that much. The
> >> changes are mostly just plugging in my specific info for the panel I'm
> >> using.
> >>
> >> I've not worked with patches much so I'll have to figure out how to do
> >> that.
> >
> > Perhaps you should include the old patch to 2.6.10 since
> > we know that worked and take it from there? In theory
> > all you should need are the basic mappings and
> > perhaps and reg init structure.
> >
> >>
> >>
> >> > On Tue, 11 Nov 2008 16:04:03 +0100
> >> > Hinko Kocevar <hinko.kocevar@cetrtapot.si> wrote:
> >> >
> >> >> jkimble@one.net wrote:
> >> >> >> James Kimble wrote:
> >> >> >
> >> >> > /proc/iomem shows:
> >> >> >
> >> >> > 74000000-74009000 : s1d13a04fb.0
> >> >> > 74000000-74009000 : s1d13xxxfb regs
> >> >> > 74040000-74068000 : s1d13a04fb.0
> >> >> > 74040000-74068000 : s1d13xxxfb mem
> >> >>
> >> >> I'm not sure if this is correct - two drivers mapped the same region
> >> >> twice !?
> >> >> Maybe the experts will shed some light on this..
> >> >>
> >> >> > f000070c-f000070c : spi-int-mask
> >> >> > f0000740-f000075f : spi-int-level
> >> >> > f0000a50-f0000a50 : spi-par
> >> >> > f0008a00-f0008ab8 : spi-module
> >> >> > f0008f00-f0008f20 : MCF548X-i2c
> >> >> > f000a000-f000a7ff : mcf548x-flexcan.0
> >> >> > f000a000-f000a7ff : mcf548x-flexcan
> >> >> > f000a800-f000afff : mcf548x-flexcan.1
> >> >> > f000a800-f000afff : mcf548x-flexcan
> >> >> > f0020000-f0033000 : fsl-sec1
> >> >> > fc000000-ffffffff : physmap-flash.0
> >> >> >
> >> >>
> >> >> I haven't took a long look at your driver, but here is our driver for
> >> >> S13706FB that
> >> >> we use on our embedded platform. Hope it helps.
> >> >
> >> > Any chance of getting a patch against s1d13xxxfb?
> >> >
> >> >>
> >> >> Regards,
> >> >> Hinko
> >> >> --
> >> >> Hinko KoÄevar, OSS developer
> >> >> ÄŒETRTA POT, d.o.o.
> >> >> Planina 3, 4000 Kranj, SI EU
> >> >> tel ++386 (0) 4 280 66 03
> >> >> e-mail hinko.kocevar@cetrtapot.si
> >> >> http www.cetrtapot.si
> >> >>
> >> >>
> >> >> -------------------------------------------------------------------------
> >> >> This SF.Net email is sponsored by the Moblin Your Move Developer's
> >> >> challenge
> >> >> Build the coolest Linux based applications with Moblin SDK & win
> >> great
> >> >> prizes
> >> >> Grand prize is a trip for two to an Open Source event anywhere in the
> >> >> world
> >> >> http://moblin-contest.org/redirect.php?banner_id=100&url=/
> >> >> _______________________________________________
> >> >> Linux-fbdev-devel mailing list
> >> >> Linux-fbdev-devel@lists.sourceforge.net
> >> >> https://lists.sourceforge.net/lists/listinfo/linux-fbdev-devel
> >> >
> >> >
> >> > --
> >> > Kristoffer Ericson <kristoffer.ericson@gmail.com>
> >> >
> >>
> >>
> >
> >
> > --
> > Kristoffer Ericson <kristoffer.ericson@gmail.com>
> >
>
--
Kristoffer Ericson <kristoffer.ericson@gmail.com>
[-- Attachment #1.2: Type: application/pgp-signature, Size: 197 bytes --]
[-- Attachment #2: Type: text/plain, Size: 363 bytes --]
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_______________________________________________
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Linux-fbdev-devel@lists.sourceforge.net
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04onColdfire running 2.6.25)
2008-11-11 16:10 ` Seg fault on any FB write (Epson S1D13A04onColdfire " jkimble
@ 2008-11-12 8:25 ` Hinko Kocevar
2008-11-12 15:52 ` jkimble
2008-11-13 4:47 ` James Kimble
0 siblings, 2 replies; 18+ messages in thread
From: Hinko Kocevar @ 2008-11-12 8:25 UTC (permalink / raw)
To: jkimble; +Cc: linux-fbdev-devel
[-- Attachment #1: Type: text/plain, Size: 546 bytes --]
jkimble@one.net wrote:
> I thought it looked OK because it looks the same as the flexCAN stuff.
> However I just noticed that flexCAN has a .0 and .1 whereas the s1d13 are
> both .0. Yeah, I hope an expert weighs in on this because I'm not sure
> now.
>
> I didn't get your attachement.
>
Maybe I forgot to attach it :P
Here it is.
HTH,
HK
--
Hinko Kočevar, OSS developer
ČETRTA POT, d.o.o.
Planina 3, 4000 Kranj, SI EU
tel ++386 (0) 4 280 66 03
e-mail hinko.kocevar@cetrtapot.si
http www.cetrtapot.si
[-- Attachment #2: carneol-s1d13706fb.c --]
[-- Type: text/x-csrc, Size: 16195 bytes --]
/*
* drivers/cpot/carneol-s1d13706fb.c
*
* Carneol Epson S1D13706 frame buffer driver.
*
* Copyright (C) 2006, 2007 Simon Posnjak <simon.posnjak@cetrtapot.si>
* Copyright (C) 2008 Hinko Kocevar <hinko.kocevar@cetrtapot.si>
*
* Adapted from:
*
* -linux/drivers/video/skeletonfb.c
* Modified to new api Jan 2001 by James Simmons (jsimmons@infradead.org)
* Created 28 Dec 1997 by Geert Uytterhoeven
*
* -linux/drivers/video/epson1355fb.c
* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> (2.4 driver)
* Copyright (C) Hewlett-Packard Company. All rights reserved. (2.6 driver)
*
* -Epson Linux drivers 2.4
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of the Linux
* distribution for more details.
*
* Changelog:
* 11 Nov 2008 added splash support with automatic rotation of image
* according to detected panel. Bitmap data is stored in
* header file containg only bitmap pixels (top->bottom)
* in uncompreesed, 8bpp (max 240 indexed colors), 320x240
* pixels format
*/
#include <linux/version.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/mman.h>
#include <linux/fb.h>
#include <asm/io.h>
#include <asm/cpot/carneol-platform.h>
#include <asm/cpot/carneol-s1d13706fb.h>
#include <asm/cpot/carneol-splash.h>
/* YYMMDDRR - year, month, day, release */
static unsigned char mod_name[] = "carneol-s1d13706fb";
static unsigned char mod_version[] = "08111114";
static unsigned char panel_type = CARNEOL_LCD_NONE;
static unsigned char platform_ver = CARNEOL_PLATFORM_VER_10;
static inline u8 s1d13706fb_readreg (struct s1d13706fb_par *par, u16 regno)
{
return readb((const volatile void __iomem *)(par->RegAddr + regno));
}
static inline void s1d13706fb_writereg (struct s1d13706fb_par *par,
u16 regno, u8 value)
{
writeb(value, (volatile unsigned char *)(par->RegAddr + regno));
}
/* Sets splash from static bitmap data found in header file.
* Bitmap is expected to be 320x240 px - same as framebuffer/LCD size, 8bpp,
* with indexed colors (max 240 colors).
*/
static void display_splash (struct fb_info *info)
{
struct s1d13706fb_par *par = info->par;
u8 *src;
u8 *dst;
u32 i;
u32 r, g, b;
u32 w, h, dx, dy;
u8 buf[BMP_LOGO_WIDTH];
printk("%s: enter\n", __func__);
/* Clear the palette to avoid sliding effect when drawing on screen. */
for (i = 0; i < BMP_LOGO_COLORS; i++)
S1D_WRITE_PALETTE(par->RegAddr, i + BMP_LOGO_OFFSET, 0, 0, 0);
w = BMP_LOGO_WIDTH;
h = BMP_LOGO_HEIGHT;
dst = (u8 *) info->screen_base;
switch (panel_type)
{
case CARNEOL_LCD_SHARP:
/* Normal. */
printk("%s: fixing bitmap data for LCD: Sharp\n", __func__);
src = (u8 *) bmp_logo_bitmap;
dx = 1;
dy = 1;
break;
case CARNEOL_LCD_AMPIRE:
/* 180 degrees rotate. */
printk("%s: fixing bitmap data for LCD: Ampire\n", __func__);
src = (u8 *) bmp_logo_bitmap + h * w - 1;
dx = -1;
dy = -1;
break;
default:
printk("%s: unknown LCD panel type %d\n", __func__, panel_type);
return;
}
while (h--)
{
for (i = 0; i < w; i++)
{
buf[i] = *src;
src += dx;
}
memcpy(dst, buf, w);
dst += w;
}
/* Get bitmap colors and set the hardware palette. Skip first 16
* colors. */
for (i = 0; i < BMP_LOGO_COLORS; i++)
{
r = (bmp_logo_palette[i] & 0x0f00) >> 4;
g = (bmp_logo_palette[i] & 0x00f0);
b = (bmp_logo_palette[i] & 0x000f) << 4;
S1D_WRITE_PALETTE(par->RegAddr, i + BMP_LOGO_OFFSET, r, g, b);
}
printk("%s: exit\n", __func__);
}
static int control_backlight (struct device *dev, int state)
{
u_int16_t val;
struct fb_info *info = dev_get_drvdata(dev);
struct s1d13706fb_par *par = info->par;
val = 0;
switch (platform_ver)
{
case CARNEOL_PLATFORM_VER_10:
case CARNEOL_PLATFORM_VER_11:
val = (state) ? 0x00 : 0x80;
break;
case CARNEOL_PLATFORM_VER_15:
val = (state) ? 0x80 : 0x00;
break;
default:
return -1;
break;
}
if (state)
printk("Backlight ON %X\n", val);
else
printk("Backlight OFF %x\n", val);
s1d13706fb_writereg(par, 0xAD, val);
return 0;
}
#define show_reg(reg) \
static ssize_t __show_reg_##reg (struct device *dev, \
struct device_attribute *attr, char *buf) \
{ \
unsigned char val; \
struct fb_info *info = dev_get_drvdata(dev); \
struct s1d13706fb_par *par = info->par; \
\
val = s1d13706fb_readreg(par, reg); \
return sprintf(buf, "HEX 0x%02X DEC %d\n", val, val); \
}
show_reg(0x12); // Horizontal Total Register
show_reg(0x14); // Horizontal Display Period Register
show_reg(0x16); // Horizontal Display Period Start Pos Register 0
show_reg(0x17); // Horizontal Display Period Start Pos Register 1
show_reg(0x18); // Vertical Total Register 0
show_reg(0x19); // Vertical Total Register 1
show_reg(0x1C); // Vertical Display Period Register 0
show_reg(0x1D); // Vertical Display Period Register 1
show_reg(0x1E); // Vertical Display Period Start Pos Register 0
show_reg(0x1F); // Vertical Display Period Start Pos Register 1
show_reg(0x20); // Horizontal Sync Pulse Width Register
show_reg(0x22); // Horizontal Sync Pulse Start Pos Register 0
show_reg(0x23); // Horizontal Sync Pulse Start Pos Register 1
show_reg(0x24); // Vertical Sync Pulse Width Register
show_reg(0x26); // Vertical Sync Pulse Start Pos Register 0
show_reg(0x27); // Vertical Sync Pulse Start Pos Register 1
show_reg(0xA8); // GPIO Config Register 0
show_reg(0xA9); // GPIO Config Register 1
show_reg(0xAC); // GPIO Status Control Register 0
show_reg(0xAD); // GPIO Status Control Register 1
#define set_reg(reg) \
static ssize_t __set_reg_##reg (struct device *dev, \
struct device_attribute *attr, const char *buf, size_t count) \
{ \
struct fb_info *info = dev_get_drvdata(dev); \
struct s1d13706fb_par *par = info->par; \
unsigned char val = simple_strtoul(buf, NULL, 16); \
\
if (reg == 0xAD) \
control_backlight (dev, val); \
else \
s1d13706fb_writereg(par, reg, val); \
return count; \
} \
static DEVICE_ATTR(reg_##reg, S_IWUSR | S_IRUGO, \
__show_reg_##reg, __set_reg_##reg);
set_reg(0x12); // Horizontal Total Register
set_reg(0x14); // Horizontal Display Period Register
set_reg(0x16); // Horizontal Display Period Start Pos Register 0
set_reg(0x17); // Horizontal Display Period Start Pos Register 1
set_reg(0x18); // Vertical Total Register 0
set_reg(0x19); // Vertical Total Register 1
set_reg(0x1C); // Vertical Display Period Register 0
set_reg(0x1D); // Vertical Display Period Register 1
set_reg(0x1E); // Vertical Display Period Start Pos Register 0
set_reg(0x1F); // Vertical Display Period Start Pos Register 1
set_reg(0x20); // Horizontal Sync Pulse Width Register
set_reg(0x22); // Horizontal Sync Pulse Start Pos Register 0
set_reg(0x23); // Horizontal Sync Pulse Start Pos Register 1
set_reg(0x24); // Vertical Sync Pulse Width Register
set_reg(0x26); // Vertical Sync Pulse Start Pos Register 0
set_reg(0x27); // Vertical Sync Pulse Start Pos Register 1
set_reg(0xA8); // GPIO Config Register 0
set_reg(0xA9); // GPIO Config Register 1
set_reg(0xAC); // GPIO Status Control Register 0
set_reg(0xAD); // GPIO Status Control Register 1
static int s1d13706fb_setcolreg (unsigned regno, unsigned r, unsigned g,
unsigned b, unsigned transp, struct fb_info *info)
{
struct s1d13706fb_par *par = info->par;
if (regno >= S1D_PALETTE_SIZE)
return 1;
S1D_WRITE_PALETTE(par->RegAddr, regno, r>>8, g>>8, b>>8);
return (0);
}
static int s1d13706fb_blank (int blank_mode, struct fb_info *info)
{
return (0);
}
static int s1d13706fb_pan_display (struct fb_var_screeninfo *var,
struct fb_info *info)
{
return (0);
}
static void s1d13706fb_rotate (struct fb_info *info, int angle)
{
printk("%s: angle %d\n", __func__, angle);
}
static struct fb_ops s1d13706fb_fbops =
{
.owner = THIS_MODULE,
.fb_setcolreg = s1d13706fb_setcolreg,
.fb_pan_display = s1d13706fb_pan_display,
.fb_blank = s1d13706fb_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_rotate = s1d13706fb_rotate,
};
static int s1d13706fb_remove (struct platform_device *dev)
{
struct fb_info *info = dev_get_drvdata(&dev->dev);
struct s1d13706fb_par *par = info->par;
if (par)
{
if (par && par->RegAddr)
iounmap((void *) par->RegAddr);
}
if (info)
{
fb_dealloc_cmap(&info->cmap);
if (info->screen_base)
iounmap(info->screen_base);
framebuffer_release(info);
}
release_mem_region(S1D_PHYSICAL_REG_ADDR, S1D_PHYSICAL_REG_SIZE);
release_mem_region(S1D_PHYSICAL_VMEM_ADDR, S1D_PHYSICAL_VMEM_SIZE);
return 0;
}
static int __init s1d13706fb_probe (struct platform_device *dev)
{
struct s1d13706fb_par *default_par;
struct fb_info *info;
S1D_INDEX s1dReg;
S1D_VALUE s1dValue;
int rc, i;
u8 revision;
int nrregs;
i = tsc2301_gpio_get_level(TSC2301_GPIO_IN3);
if (i)
{
printk("Carneol platform detect: version 1.5\n");
platform_ver = CARNEOL_PLATFORM_VER_15;
}
else
{
printk("Carneol platform detect: version 1.0 or 1.1\n");
platform_ver = CARNEOL_PLATFORM_VER_11;
}
i = tsc2301_gpio_get_level(TSC2301_GPIO_IN4);
if (i)
{
panel_type = CARNEOL_LCD_AMPIRE;
printk("Carneol LCD detect: Ampire\n");
}
else
{
panel_type = CARNEOL_LCD_SHARP;
printk("Carneol LCD detect: Sharp\n");
}
if (!request_mem_region(S1D_PHYSICAL_REG_ADDR, S1D_PHYSICAL_REG_SIZE,
"S1D13706 registers"))
{
printk(KERN_ERR "s1d13706fb: unable to reserve registers at 0x%0lx\n",
S1D_PHYSICAL_REG_ADDR);
rc = -EBUSY;
goto bail;
}
if (!request_mem_region(S1D_PHYSICAL_VMEM_ADDR, S1D_PHYSICAL_VMEM_SIZE,
"S1D13706 framebuffer"))
{
printk(KERN_ERR "s1d13706fb: unable to reserve framebuffer at 0x%0lx\n",
S1D_PHYSICAL_VMEM_ADDR);
rc = -EBUSY;
goto bail;
}
info = framebuffer_alloc(sizeof(struct s1d13706fb_par) + sizeof(u32) * 256,
&dev->dev);
if (!info)
{
rc = -ENOMEM;
goto bail;
}
default_par = info->par;
default_par->RegAddr = (u8 *) ioremap(S1D_PHYSICAL_REG_ADDR,
S1D_PHYSICAL_REG_SIZE);
if (!default_par->RegAddr)
{
printk(KERN_ERR "s1d13706fb: unable to map registers\n");
rc = -ENOMEM;
goto bail;
}
info->pseudo_palette = (void *)(default_par + 1);
info->screen_base = ioremap(S1D_PHYSICAL_VMEM_ADDR,
S1D_PHYSICAL_VMEM_SIZE);
if (!info->screen_base)
{
printk(KERN_ERR "s1d13706fb: unable to map framebuffer\n");
rc = -ENOMEM;
goto bail;
}
info->fix.mmio_start = S1D_PHYSICAL_REG_ADDR;
info->fix.mmio_len = S1D_PHYSICAL_REG_SIZE;
info->fix.smem_start = S1D_PHYSICAL_VMEM_ADDR;
info->fix.smem_len = S1D_PHYSICAL_VMEM_SIZE;
nrregs = sizeof(sharp_S1DRegs);
for (i = 0; i < nrregs/sizeof(S1D_REGS); i++)
{
switch (panel_type)
{
case CARNEOL_LCD_SHARP:
s1dReg = sharp_S1DRegs[i].Index;
s1dValue = sharp_S1DRegs[i].Value;
break;
case CARNEOL_LCD_AMPIRE:
s1dReg = ampire_S1DRegs[i].Index;
s1dValue = ampire_S1DRegs[i].Value;
break;
default:
rc = -EINVAL;
goto bail;
break;
}
if (s1dReg == S1D_REGDELAYOFF || s1dReg == S1D_REGDELAYON)
mdelay((int)s1dValue);
else
((S1D_VALUE*)default_par->RegAddr)[s1dReg/sizeof(S1D_VALUE)] =
s1dValue;
}
strcpy(info->fix.id, "S1D13706");
info->par = default_par;
info->fbops = &s1d13706fb_fbops;
info->flags = FBINFO_DEFAULT;
revision = s1d13706fb_readreg (default_par, 0);
if (register_framebuffer(info) < 0)
{
rc = -EINVAL;
goto bail;
}
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->var.bits_per_pixel = 8;
info->var.red.offset = info->var.green.offset = info->var.blue.offset = 0;
info->var.red.length = info->var.green.length = info->var.blue.length = 8;
fb_alloc_cmap(&info->cmap, 256, 0);
/* Make sure first color is black - 0,0,0 */
s1d13706fb_setcolreg(0, 0, 0, 0, 0, info);
info->var.xres = S1D_DISPLAY_WIDTH;
info->var.yres = S1D_DISPLAY_HEIGHT;
info->var.xres_virtual = info->var.xres;
info->var.yres_virtual = info->var.yres;
info->var.xoffset = info->var.yoffset = 0;
info->fix.line_length = 320;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->var.grayscale = 0;
info->var.pixclock = S1D_DISPLAY_PCLK;
info->var.sync = 0;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->var.activate = FB_ACTIVATE_NOW;
dev_set_drvdata(&dev->dev, info);
/*
* Set Backlight power ON according to carneol board type detected.
* Board r1.1 has backlight permanently on, while on board r1.5 we
* have to turn it on with GP0 pin on S1D13706.
* Newer 1.5 boards dont't have a backlight converter at all - boards
* with Ampire LCD panels.
*/
control_backlight(&dev->dev, 1);
/* Show nice logo from bitmap pixel array. */
display_splash(info);
return 0;
bail:
s1d13706fb_remove(dev);
return rc;
}
static struct platform_driver s1d13706fb_driver =
{
.probe = s1d13706fb_probe,
.remove = s1d13706fb_remove,
.driver = {
.owner = THIS_MODULE,
.name = mod_name,
}
};
static void s1d13706fb_release (struct device *device)
{
return;
}
static struct platform_device s1d13706fb_device =
{
.name = mod_name,
.id = -1,
.dev = {
.release = s1d13706fb_release,
}
};
static int __init s1d13706fb_init (void)
{
int ret;
printk("Carneol %s module %s, (C) 2005 - 2008 Simon Posnjak\n", mod_name, mod_version);
if (fb_get_options("s1d13706fb", NULL))
return -ENODEV;
ret = platform_driver_register(&s1d13706fb_driver);
if (ret == 0)
{
ret = platform_device_register(&s1d13706fb_device);
if (ret)
{
printk(KERN_ERR "Failed to register device for Carneol %s\n", mod_name);
goto error;
}
}
else
{
printk(KERN_ERR "Failed to register driver for Carneol %s\n", mod_name);
goto error;
}
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x12);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x14);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x16);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x17);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x18);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x19);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x1C);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x1D);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x1E);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x1F);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x20);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x22);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x23);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x24);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x26);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x27);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0xA8);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0xA9);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0xAC);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0xAD);
return 0;
error:
platform_driver_unregister(&s1d13706fb_driver);
return ret;
}
static void __exit s1d13706fb_exit (void)
{
/* Turn backlight off */
control_backlight(&s1d13706fb_device.dev, 0);
platform_device_unregister(&s1d13706fb_device);
platform_driver_unregister(&s1d13706fb_driver);
printk("Carneol %s module version %s removed\n", mod_name, mod_version);
}
module_init(s1d13706fb_init);
module_exit(s1d13706fb_exit);
MODULE_AUTHOR("Simon Posnjak <simon.posnjak@cetrtapot.si>, Hinko Kocevar <hinko.kocevar@cetrtapot.si>");
MODULE_DESCRIPTION("CPOT Carneol framebuffer module for Epson S1D13706");
MODULE_LICENSE("GPL");
[-- Attachment #3: carneol-s1d13706fb.h --]
[-- Type: text/x-chdr, Size: 7395 bytes --]
#ifndef _CARNEOL_S1D13706FB_H_
#define _CARNEOL_S1D13706FB_H_
/*
* Generated with Epson configuration generator
*
* BIG NOTE
*
* Must use un-cached area when accessing framebuffer memory,
* otherwise cached lines corrupt screen image - screen ripping.
* Add 0x80000000 to addresses to use uncached access!
*/
#define S1D_PHYSICAL_VMEM_ADDR 0x88020000L
#define S1D_PHYSICAL_VMEM_SIZE 0x14000L
#define S1D_PHYSICAL_REG_ADDR 0x88000000L
#define S1D_PHYSICAL_REG_SIZE 0x100
#define S1D_DISPLAY_WIDTH 320
#define S1D_DISPLAY_HEIGHT 240
/* SHARP panels works fine with 12.5 MHz PCLK, Ampire panels *only* work fine
* with 12.5 MHz!
*/
#define S1D_DISPLAY_PCLK 12500000
#define S1DREG_LCD_MEM_OFF0 0x80
#define S1DREG_LCD_MEM_OFF1 0x81
#define S1DREG_DISP_MODE 0x70
#define S1D_PALETTE_SIZE 256
#define S1D_REGDELAYOFF 0xFFFE
#define S1D_REGDELAYON 0xFFFF
#define S1D_WRITE_PALETTE(p,i,r,g,b) \
{ \
((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)(r); \
((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)(g); \
((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)(b); \
((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
}
struct s1d13706fb_par
{
u_int8_t * RegAddr;
};
typedef unsigned short S1D_INDEX;
typedef unsigned char S1D_VALUE;
typedef struct
{
S1D_INDEX Index;
S1D_VALUE Value;
} S1D_REGS;
/* Each panel has its own special settings that make scren look ideal. Specify
* settings below..
*/
static S1D_REGS sharp_S1DRegs[] =
{
{0x04,0x00}, /* BUSCLK MEMCLK Config Register */
{0x05,0x33}, /* PCLK Config Register */
{0x10,0x61}, /* PANEL Type Register */
{0x11,0x00}, /* MOD Rate Register */
{0x12,0x2F}, /* Horizontal Total Register */
{0x14,0x27}, /* Horizontal Display Period Register */
{0x16,0x38}, /* Horizontal Display Period Start Pos Register 0 */
{0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
{0x18,0x05}, /* Vertical Total Register 0 */
{0x19,0x01}, /* Vertical Total Register 1 */
{0x1C,0xEF}, /* Vertical Display Period Register 0 */
{0x1D,0x00}, /* Vertical Display Period Register 1 */
{0x1E,0x07}, /* Vertical Display Period Start Pos Register 0 */
{0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
{0x20,0x07}, /* Horizontal Sync Pulse Width Register */
{0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
{0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
{0x24,0x03}, /* Vertical Sync Pulse Width Register */
{0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */
{0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
{0x70,0x03}, /* Display Mode Register */
{0x71,0x00}, /* Special Effects Register */
{0x74,0x00}, /* Main Window Display Start Address Register 0 */
{0x75,0x00}, /* Main Window Display Start Address Register 1 */
{0x76,0x00}, /* Main Window Display Start Address Register 2 */
{0x78,0x50}, /* Main Window Address Offset Register 0 */
{0x79,0x00}, /* Main Window Address Offset Register 1 */
{0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
{0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
{0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
{0x80,0x50}, /* Sub Window Address Offset Register 0 */
{0x81,0x00}, /* Sub Window Address Offset Register 1 */
{0x84,0x00}, /* Sub Window X Start Pos Register 0 */
{0x85,0x00}, /* Sub Window X Start Pos Register 1 */
{0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
{0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
{0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
{0x8D,0x00}, /* Sub Window X End Pos Register 1 */
{0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
{0x91,0x00}, /* Sub Window Y End Pos Register 1 */
{0xA0,0x00}, /* Power Save Config Register */
{0xA1,0x00}, /* CPU Access Control Register */
{0xA2,0x00}, /* Software Reset Register */
{0xA3,0x00}, /* BIG Endian Support Register */
{0xA4,0x00}, /* Scratch Pad Register 0 */
{0xA5,0x00}, /* Scratch Pad Register 1 */
{0xA8,0x06}, /* GPIO Config Register 0 */
{0xA9,0x80}, /* GPIO Config Register 1 */
{0xAC,0x04}, /* GPIO Status Control Register 0 */
{0xAD,0x00}, /* GPIO Status Control Register 1 */
{0xB0,0x00}, /* PWM CV Clock Control Register */
{0xB1,0x00}, /* PWM CV Clock Config Register */
{0xB2,0x00}, /* CV Clock Burst Length Register */
{0xB3,0x00}, /* PWM Clock Duty Cycle Register */
};
static S1D_REGS ampire_S1DRegs[] =
{
{0x04,0x00}, /* BUSCLK MEMCLK Config Register */
{0x05,0x33}, /* PCLK Config Register */
{0x10,0x61}, /* PANEL Type Register */
{0x11,0x00}, /* MOD Rate Register */
{0x12,0x32}, /* Horizontal Total Register */
{0x14,0x27}, /* Horizontal Display Period Register */
{0x16,0x40}, /* Horizontal Display Period Start Pos Register 0 */
{0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
{0x18,0x13}, /* Vertical Total Register 0 */
{0x19,0x01}, /* Vertical Total Register 1 */
{0x1C,0xEF}, /* Vertical Display Period Register 0 */
{0x1D,0x00}, /* Vertical Display Period Register 1 */
{0x1E,0x21}, /* Vertical Display Period Start Pos Register 0 */
{0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
{0x20,0x13}, /* Horizontal Sync Pulse Width Register */
{0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
{0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
{0x24,0x02}, /* Vertical Sync Pulse Width Register */
{0x26,0x0F}, /* Vertical Sync Pulse Start Pos Register 0 */
{0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
{0x70,0x03}, /* Display Mode Register */
{0x71,0x00}, /* Special Effects Register */
{0x74,0x00}, /* Main Window Display Start Address Register 0 */
{0x75,0x00}, /* Main Window Display Start Address Register 1 */
{0x76,0x00}, /* Main Window Display Start Address Register 2 */
{0x78,0x50}, /* Main Window Address Offset Register 0 */
{0x79,0x00}, /* Main Window Address Offset Register 1 */
{0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
{0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
{0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
{0x80,0x50}, /* Sub Window Address Offset Register 0 */
{0x81,0x00}, /* Sub Window Address Offset Register 1 */
{0x84,0x00}, /* Sub Window X Start Pos Register 0 */
{0x85,0x00}, /* Sub Window X Start Pos Register 1 */
{0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
{0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
{0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
{0x8D,0x00}, /* Sub Window X End Pos Register 1 */
{0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
{0x91,0x00}, /* Sub Window Y End Pos Register 1 */
{0xA0,0x00}, /* Power Save Config Register */
{0xA1,0x00}, /* CPU Access Control Register */
{0xA2,0x00}, /* Software Reset Register */
{0xA3,0x00}, /* BIG Endian Support Register */
{0xA4,0x00}, /* Scratch Pad Register 0 */
{0xA5,0x00}, /* Scratch Pad Register 1 */
{0xA8,0x06}, /* GPIO Config Register 0 */
{0xA9,0x80}, /* GPIO Config Register 1 */
{0xAC,0x04}, /* GPIO Status Control Register 0 */
{0xAD,0x00}, /* GPIO Status Control Register 1 */
{0xB0,0x00}, /* PWM CV Clock Control Register */
{0xB1,0x00}, /* PWM CV Clock Config Register */
{0xB2,0x00}, /* CV Clock Burst Length Register */
{0xB3,0x00}, /* PWM Clock Duty Cycle Register */
};
#endif /* _CARNEOL_S1D13706FB_H_ */
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04on Coldfire running 2.6.25)
2008-11-11 18:52 ` Seg fault on any FB write (Epson S1D13A04on Coldfire " Kristoffer Ericson
2008-11-11 18:02 ` Seg fault on any FB write (Epson S1D13A04onColdfire " jkimble
@ 2008-11-12 8:34 ` Hinko Kocevar
1 sibling, 0 replies; 18+ messages in thread
From: Hinko Kocevar @ 2008-11-12 8:34 UTC (permalink / raw)
To: Kristoffer Ericson; +Cc: linux-fbdev-devel
Kristoffer Ericson wrote:
> On Tue, 11 Nov 2008 16:04:03 +0100
> Hinko Kocevar <hinko.kocevar@cetrtapot.si> wrote:
>
>> jkimble@one.net wrote:
>>>> James Kimble wrote:
>>> /proc/iomem shows:
>>>
>>> 74000000-74009000 : s1d13a04fb.0
>>> 74000000-74009000 : s1d13xxxfb regs
>>> 74040000-74068000 : s1d13a04fb.0
>>> 74040000-74068000 : s1d13xxxfb mem
>> I'm not sure if this is correct - two drivers mapped the same region twice !?
>> Maybe the experts will shed some light on this..
>>
>>> f000070c-f000070c : spi-int-mask
>>> f0000740-f000075f : spi-int-level
>>> f0000a50-f0000a50 : spi-par
>>> f0008a00-f0008ab8 : spi-module
>>> f0008f00-f0008f20 : MCF548X-i2c
>>> f000a000-f000a7ff : mcf548x-flexcan.0
>>> f000a000-f000a7ff : mcf548x-flexcan
>>> f000a800-f000afff : mcf548x-flexcan.1
>>> f000a800-f000afff : mcf548x-flexcan
>>> f0020000-f0033000 : fsl-sec1
>>> fc000000-ffffffff : physmap-flash.0
>>>
>> I haven't took a long look at your driver, but here is our driver for S13706FB that
>> we use on our embedded platform. Hope it helps.
>
> Any chance of getting a patch against s1d13xxxfb?
Maybe, in the days that follow, in the meantime please take a look at the
driver (resend) in the previous email.
It is tested with 320x240 LCD panel from Sharp, 8bpp, and hardware palette. The xx706 chip
only has 80kB of framebuffer memory so there is not much you can do with it.
Regards,
Hinko
--
Hinko Koèevar, OSS developer
ÈETRTA POT, d.o.o.
Planina 3, 4000 Kranj, SI EU
tel ++386 (0) 4 280 66 03
e-mail hinko.kocevar@cetrtapot.si
http www.cetrtapot.si
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04onColdfire running 2.6.25)
2008-11-12 8:25 ` Hinko Kocevar
@ 2008-11-12 15:52 ` jkimble
2008-11-13 4:47 ` James Kimble
1 sibling, 0 replies; 18+ messages in thread
From: jkimble @ 2008-11-12 15:52 UTC (permalink / raw)
To: Hinko Kocevar; +Cc: linux-fbdev-devel
Thanks! This should help a lot.
This seg fault thing is very weird though. I think my FB driver is ok. I
think it's something basic in how user space accesses this memory that I'm
missing.
Thanks for your help though.
> jkimble@one.net wrote:
>> I thought it looked OK because it looks the same as the flexCAN stuff.
>> However I just noticed that flexCAN has a .0 and .1 whereas the s1d13
>> are
>> both .0. Yeah, I hope an expert weighs in on this because I'm not sure
>> now.
>>
>> I didn't get your attachement.
>>
>
> Maybe I forgot to attach it :P
> Here it is.
>
>
> HTH,
> HK
>
>
> --
> Hinko Kočevar, OSS developer
> ČETRTA POT, d.o.o.
> Planina 3, 4000 Kranj, SI EU
> tel ++386 (0) 4 280 66 03
> e-mail hinko.kocevar@cetrtapot.si
> http www.cetrtapot.si
>
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04onColdfire running 2.6.25)
2008-11-12 8:25 ` Hinko Kocevar
2008-11-12 15:52 ` jkimble
@ 2008-11-13 4:47 ` James Kimble
2008-11-13 8:50 ` Hinko Kocevar
1 sibling, 1 reply; 18+ messages in thread
From: James Kimble @ 2008-11-13 4:47 UTC (permalink / raw)
To: Hinko Kocevar; +Cc: linux-fbdev-devel
In looking at your driver (which I think is a lot better organized than
the general one that came with the kernel by the way) I see that you're
doing a whole string of:
~~~~~~~~~~
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x12);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x14);
device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x16);
~~~~~~~~~~
In s1d13706fb_init(). I didn't do any of this my driver. Is this needed
for any purpose other than to allow easy access to change the values in
these registers in user space?
I was able to port your driver to the values and registers used by my
device and the behavior is virtually the same as with my driver. Screen
is initialized, I can see the color palette get set and the panel
enable. Everything boots up fine but none of my user space applications
work. The first time I try to write to a register or video memory I get
a seg fault.
This has got to be some kind of memory configuration issue. I've moved
the CS configuration for this device to different memory locations but
it doesn't change the behavior. I'm setting things up in U-Boot in
exactly the same way I had been setting them up in Colilo for the 2.6.10
kernel (where everything worked).
I'm really stuck. If anyone has any ideas or suggestions I'd really
appreciate your thoughts.
Thanks for your attention...
Hinko Kocevar wrote:
> jkimble@one.net wrote:
>
>> I thought it looked OK because it looks the same as the flexCAN stuff.
>> However I just noticed that flexCAN has a .0 and .1 whereas the s1d13 are
>> both .0. Yeah, I hope an expert weighs in on this because I'm not sure
>> now.
>>
>> I didn't get your attachement.
>>
>>
>
> Maybe I forgot to attach it :P
> Here it is.
>
>
> HTH,
> HK
>
>
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04onColdfire running 2.6.25)
2008-11-13 4:47 ` James Kimble
@ 2008-11-13 8:50 ` Hinko Kocevar
2008-11-13 11:55 ` Kristoffer Ericson
0 siblings, 1 reply; 18+ messages in thread
From: Hinko Kocevar @ 2008-11-13 8:50 UTC (permalink / raw)
To: James Kimble; +Cc: linux-fbdev-devel
James Kimble wrote:
>
> In looking at your driver (which I think is a lot better organized than
> the general one that came with the kernel by the way) I see that you're
> doing a whole string of:
>
> ~~~~~~~~~~
> device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x12);
> device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x14);
> device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x16);
> ~~~~~~~~~~
> In s1d13706fb_init(). I didn't do any of this my driver. Is this needed
> for any purpose other than to allow easy access to change the values in
> these registers in user space?
>
It is there purely for debugging purposes. It also allows quick setup of
eg. different LCD panels that require some tweaking in order to center the
image or fix refresh rate.
> I was able to port your driver to the values and registers used by my
> device and the behavior is virtually the same as with my driver. Screen
> is initialized, I can see the color palette get set and the panel
And if you draw a pixel from the driver - does it work? Another quick test
is to set color palette and then memset() complete framebuffer memory to
a singles value stored in palette, or change the palette index value to
achieve image color change on the screen.
> enable. Everything boots up fine but none of my user space applications
> work. The first time I try to write to a register or video memory I get
> a seg fault.
>
Does the oops appear in the dmesg, too?
> This has got to be some kind of memory configuration issue. I've moved
> the CS configuration for this device to different memory locations but
> it doesn't change the behavior. I'm setting things up in U-Boot in
> exactly the same way I had been setting them up in Colilo for the 2.6.10
> kernel (where everything worked).
>
What about other memory mapped devices you might have on the system? Do
they function properly? If not this might be indicator where look for
the problem.
Regards,
Hinko
--
Hinko Kočevar, OSS developer
ČETRTA POT, d.o.o.
Planina 3, 4000 Kranj, SI EU
tel ++386 (0) 4 280 66 03
e-mail hinko.kocevar@cetrtapot.si
http www.cetrtapot.si
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: Seg fault on any FB write (Epson S1D13A04onColdfire running 2.6.25)
2008-11-13 8:50 ` Hinko Kocevar
@ 2008-11-13 11:55 ` Kristoffer Ericson
0 siblings, 0 replies; 18+ messages in thread
From: Kristoffer Ericson @ 2008-11-13 11:55 UTC (permalink / raw)
To: Hinko Kocevar; +Cc: linux-fbdev-devel
[-- Attachment #1.1: Type: text/plain, Size: 3377 bytes --]
On Thu, 13 Nov 2008 09:50:50 +0100
Hinko Kocevar <hinko.kocevar@cetrtapot.si> wrote:
> James Kimble wrote:
> >
> > In looking at your driver (which I think is a lot better organized than
> > the general one that came with the kernel by the way) I see that you're
> > doing a whole string of:
> >
> > ~~~~~~~~~~
> > device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x12);
> > device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x14);
> > device_create_file(&s1d13706fb_device.dev, &dev_attr_reg_0x16);
> > ~~~~~~~~~~
> > In s1d13706fb_init(). I didn't do any of this my driver. Is this needed
> > for any purpose other than to allow easy access to change the values in
> > these registers in user space?
> >
>
> It is there purely for debugging purposes. It also allows quick setup of
> eg. different LCD panels that require some tweaking in order to center the
> image or fix refresh rate.
>
> > I was able to port your driver to the values and registers used by my
> > device and the behavior is virtually the same as with my driver. Screen
> > is initialized, I can see the color palette get set and the panel
>
> And if you draw a pixel from the driver - does it work? Another quick test
> is to set color palette and then memset() complete framebuffer memory to
> a singles value stored in palette, or change the palette index value to
> achieve image color change on the screen.
>
> > enable. Everything boots up fine but none of my user space applications
> > work. The first time I try to write to a register or video memory I get
> > a seg fault.
> >
>
> Does the oops appear in the dmesg, too?
>
> > This has got to be some kind of memory configuration issue. I've moved
> > the CS configuration for this device to different memory locations but
> > it doesn't change the behavior. I'm setting things up in U-Boot in
> > exactly the same way I had been setting them up in Colilo for the 2.6.10
> > kernel (where everything worked).
> >
I agree, it sounds alot more like a deeper bug
than restricted to your video driver. I can't see
anything that would cause that (atleast yet). Would
be worth it to get some input from linux-m68k (coldfire m68k right?).
>
> What about other memory mapped devices you might have on the system? Do
> they function properly? If not this might be indicator where look for
> the problem.
>
> Regards,
> Hinko
>
> --
> Hinko Kočevar, OSS developer
> ČETRTA POT, d.o.o.
> Planina 3, 4000 Kranj, SI EU
> tel ++386 (0) 4 280 66 03
> e-mail hinko.kocevar@cetrtapot.si
> http www.cetrtapot.si
>
>
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> _______________________________________________
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--
Kristoffer Ericson <kristoffer.ericson@gmail.com>
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^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2008-11-13 10:54 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-11-11 1:54 Seg fault on any FB write (Epson S1D13A04 on Coldfire running 2.6.25) James Kimble
2008-11-11 9:57 ` Hinko Kocevar
2008-11-11 14:50 ` Seg fault on any FB write (Epson S1D13A04on " jkimble
2008-11-11 15:04 ` Hinko Kocevar
2008-11-11 16:10 ` Seg fault on any FB write (Epson S1D13A04onColdfire " jkimble
2008-11-12 8:25 ` Hinko Kocevar
2008-11-12 15:52 ` jkimble
2008-11-13 4:47 ` James Kimble
2008-11-13 8:50 ` Hinko Kocevar
2008-11-13 11:55 ` Kristoffer Ericson
2008-11-11 18:52 ` Seg fault on any FB write (Epson S1D13A04on Coldfire " Kristoffer Ericson
2008-11-11 18:02 ` Seg fault on any FB write (Epson S1D13A04onColdfire " jkimble
2008-11-11 19:14 ` Kristoffer Ericson
2008-11-11 18:20 ` jkimble
2008-11-11 19:29 ` Kristoffer Ericson
2008-11-12 8:34 ` Seg fault on any FB write (Epson S1D13A04on Coldfire " Hinko Kocevar
2008-11-11 15:06 ` jkimble
2008-11-11 18:50 ` Seg fault on any FB write (Epson S1D13A04 on " Kristoffer Ericson
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