From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53355C433F5 for ; Mon, 30 May 2022 08:21:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233613AbiE3IVQ (ORCPT ); Mon, 30 May 2022 04:21:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232803AbiE3IVL (ORCPT ); Mon, 30 May 2022 04:21:11 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 304446CF72; Mon, 30 May 2022 01:21:10 -0700 (PDT) X-UUID: 982407c30d5946e9ab684d23f77821d1-20220530 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:168ee1fe-803a-40b0-b12e-f89bb2b057ae,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:c66ac1b8-3c45-407b-8f66-25095432a27a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: 982407c30d5946e9ab684d23f77821d1-20220530 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 610165319; Mon, 30 May 2022 16:21:04 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 30 May 2022 16:21:02 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 30 May 2022 16:21:02 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 30 May 2022 16:21:02 +0800 Message-ID: <5253064d45064cc89d7c3c75d217b8fcb059766e.camel@mediatek.com> Subject: Re: [PATCH v10 10/21] drm/mediatek: dpi: move hvsize_mask to SoC config From: CK Hu To: Guillaume Ranquet , Chun-Kuang Hu , Philipp Zabel , "David Airlie" , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , "Kishon Vijay Abraham I" , Vinod Koul , "Helge Deller" , Jitao shi CC: AngeloGioacchino Del Regno , Rex-BC Chen , , , , , , , Date: Mon, 30 May 2022 16:21:02 +0800 In-Reply-To: <20220523104758.29531-11-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-11-granquet@baylibre.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Hi, Guillaume: On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > Add flexibility by moving the hvsize mask to SoC specific config Reviewed-by: CK Hu > > Signed-off-by: Guillaume Ranquet > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Reviewed-by: Rex-BC Chen > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index bf098f36a466..6eeda222a973 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -129,6 +129,8 @@ struct mtk_dpi_conf { > bool swap_input_support; > /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH > (no shift) */ > u32 dimension_mask; > + /* HSIZE and VSIZE mask (no shift) */ > + u32 hvsize_mask; > const struct mtk_dpi_yc_limit *limit; > }; > > @@ -243,8 +245,10 @@ static void mtk_dpi_config_interface(struct > mtk_dpi *dpi, bool inter) > > static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, > u32 height) > { > - mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); > - mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); > + mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, > + dpi->conf->hvsize_mask << HSIZE); > + mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, > + dpi->conf->hvsize_mask << VSIZE); > } > > static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) > @@ -816,6 +820,7 @@ static const struct mtk_dpi_conf mt8173_conf = { > .is_ck_de_pol = true, > .swap_input_support = true, > .dimension_mask = HPW_MASK, > + .hvsize_mask = HSIZE_MASK, > .limit = &mtk_dpi_limit, > }; > > @@ -829,6 +834,7 @@ static const struct mtk_dpi_conf mt2701_conf = { > .is_ck_de_pol = true, > .swap_input_support = true, > .dimension_mask = HPW_MASK, > + .hvsize_mask = HSIZE_MASK, > .limit = &mtk_dpi_limit, > }; > > @@ -841,6 +847,7 @@ static const struct mtk_dpi_conf mt8183_conf = { > .is_ck_de_pol = true, > .swap_input_support = true, > .dimension_mask = HPW_MASK, > + .hvsize_mask = HSIZE_MASK, > .limit = &mtk_dpi_limit, > }; > > @@ -853,6 +860,7 @@ static const struct mtk_dpi_conf mt8192_conf = { > .is_ck_de_pol = true, > .swap_input_support = true, > .dimension_mask = HPW_MASK, > + .hvsize_mask = HSIZE_MASK, > .limit = &mtk_dpi_limit, > }; >