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charset=UTF-8 Date: Mon, 02 Mar 2026 21:02:07 +0900 Message-Id: Cc: , "Miguel Ojeda" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , "Danilo Krummrich" , "Dave Airlie" , "Daniel Almeida" , "Koen Koning" , , , , "Nikola Djukic" , "Maarten Lankhorst" , "Maxime Ripard" , "Simona Vetter" , "Jonathan Corbet" , "Alex Deucher" , =?utf-8?q?Christian_K=C3=B6nig?= , "Jani Nikula" , "Joonas Lahtinen" , "Rodrigo Vivi" , "Tvrtko Ursulin" , "Huang Rui" , "Matthew Auld" , "Matthew Brost" , "Lucas De Marchi" , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , "Helge Deller" , "Alex Gaynor" , "Boqun Feng" , "Alistair Popple" , "Andrea Righi" , "Zhi Wang" , "Philipp Stanner" , "Elle Rhumsaa" , , "Eliot Courtney" , , , , , , Subject: Re: [PATCH v8 07/25] docs: gpu: nova-core: Document the PRAMIN aperture mechanism From: "Alexandre Courbot" To: "Joel Fernandes" References: <20260224225323.3312204-1-joelagnelf@nvidia.com> <20260224225323.3312204-8-joelagnelf@nvidia.com> In-Reply-To: <20260224225323.3312204-8-joelagnelf@nvidia.com> X-ClientProxiedBy: TYCP286CA0078.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b3::15) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|LV5PR12MB9827:EE_ X-MS-Office365-Filtering-Correlation-Id: aefbff18-1d92-4fd7-671e-08de785388d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|10070799003|1800799024|366016; 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The SYS_MEM target value= s > are documented for completeness but not used by the driver. > > Cc: Nikola Djukic > Signed-off-by: Joel Fernandes > --- > Documentation/gpu/nova/core/pramin.rst | 125 +++++++++++++++++++++++++ > Documentation/gpu/nova/index.rst | 1 + > 2 files changed, 126 insertions(+) > create mode 100644 Documentation/gpu/nova/core/pramin.rst > > diff --git a/Documentation/gpu/nova/core/pramin.rst b/Documentation/gpu/n= ova/core/pramin.rst > new file mode 100644 > index 000000000000..55ec9d920629 > --- /dev/null > +++ b/Documentation/gpu/nova/core/pramin.rst > @@ -0,0 +1,125 @@ > +.. SPDX-License-Identifier: GPL-2.0 > + > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D > +PRAMIN aperture mechanism > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D > + > +.. note:: > + The following description is approximate and current as of the Ampere= family. > + It may change for future generations and is intended to assist in und= erstanding > + the driver code. > + > +Introduction > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > +PRAMIN is a hardware aperture mechanism that provides CPU access to GPU = Video RAM (VRAM) before > +the GPU's Memory Management Unit (MMU) and page tables are initialized. = This 1MB sliding window, > +located at a fixed offset within BAR0, is essential for setting up page = tables and other critical > +GPU data structures without relying on the GPU's MMU. > + > +Architecture Overview > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > +The PRAMIN aperture mechanism is logically implemented by the GPU's PBUS= (PCIe Bus Controller Unit) > +and provides a CPU-accessible window into VRAM through the PCIe interfac= e:: > + > + +-----------------+ PCIe +------------------------------+ > + | CPU |<----------->| GPU | > + +-----------------+ | | > + | +----------------------+ | > + | | PBUS | | > + | | (Bus Controller) | | > + | | | | > + | | +--------------+<------------ = (window starts at > + | | | PRAMIN | | | = BAR0 + 0x700000) > + | | | Window | | | > + | | | (1MB) | | | > + | | +--------------+ | | > + | | | | | > + | +---------|------------+ | > + | | | > + | v | > + | +----------------------+<--------= ---- (Program PRAMIN to any > + | | VRAM | | = 64KB-aligned VRAM boundary) > + | | (Several GBs) | | > + | | | | > + | | FB[0x000000000000] | | > + | | ... | | > + | | FB[0x7FFFFFFFFFF] | | > + | +----------------------+ | > + +------------------------------+ > + > +PBUS (PCIe Bus Controller) is responsible for, among other things, handl= ing MMIO > +accesses to the BAR registers. > + > +PRAMIN Window Operation > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > +The PRAMIN window provides a 1MB sliding aperture that can be reposition= ed over > +the entire VRAM address space using the ``NV_PBUS_BAR0_WINDOW`` register= . > + > +Window Control Mechanism > +------------------------- > + > +The window position is controlled via the PBUS ``BAR0_WINDOW`` register:= : This repeats the sentence of `PRAMIN Window Operation`. Let's remove that sentence. > + > + NV_PBUS_BAR0_WINDOW Register (0x1700): > + +-------+--------+--------------------------------------+ > + | 31:26 | 25:24 | 23:0 | > + | RSVD | TARGET | BASE_ADDR | > + | | | (bits 39:16 of VRAM address) | > + +-------+--------+--------------------------------------+ > + > + BASE_ADDR field (bits 23:0): > + - Contains bits [39:16] of the target VRAM address > + - Provides 40-bit (1TB) address space coverage > + - Must be programmed with 64KB-aligned addresses This reads a bit like filler - let's turn this into a single sentence, of just keep the first point - the other two are deducible from it.