From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 197E1C433EF for ; Mon, 30 May 2022 08:47:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232665AbiE3Ird (ORCPT ); Mon, 30 May 2022 04:47:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230287AbiE3Ir2 (ORCPT ); Mon, 30 May 2022 04:47:28 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 332B029827; Mon, 30 May 2022 01:47:27 -0700 (PDT) X-UUID: 8411f63de33c4a2e8149dc7f93c31407-20220530 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:19cfd18b-16d3-4fbd-baba-fdc4bfa74526,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:9802ff47-4fb1-496b-8f1d-39e733fed1ea,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: 8411f63de33c4a2e8149dc7f93c31407-20220530 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1985271771; Mon, 30 May 2022 16:47:23 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 30 May 2022 16:47:21 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 30 May 2022 16:47:21 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 30 May 2022 16:47:21 +0800 Message-ID: Subject: Re: [PATCH v10 12/21] drm/mediatek: dpi: move the yuv422_en_bit to SoC config From: CK Hu To: Guillaume Ranquet , Chun-Kuang Hu , Philipp Zabel , "David Airlie" , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , "Kishon Vijay Abraham I" , Vinod Koul , "Helge Deller" , Jitao shi CC: AngeloGioacchino Del Regno , Rex-BC Chen , , , , , , , Date: Mon, 30 May 2022 16:47:21 +0800 In-Reply-To: <20220523104758.29531-13-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-13-granquet@baylibre.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Hi, Guillaume: On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > Add flexibility by moving the yuv422 en bit to SoC specific config Reviewed-by: CK Hu > > Signed-off-by: Guillaume Ranquet > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Reviewed-by: Rex-BC Chen > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 6d4d8c6ec47d..40254cd9d168 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -132,6 +132,7 @@ struct mtk_dpi_conf { > /* HSIZE and VSIZE mask (no shift) */ > u32 hvsize_mask; > u32 channel_swap_shift; > + u32 yuv422_en_bit; > const struct mtk_dpi_yc_limit *limit; > }; > > @@ -356,7 +357,8 @@ static void mtk_dpi_config_channel_swap(struct > mtk_dpi *dpi, > > static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool > enable) > { > - mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); > + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : > 0, > + dpi->conf->yuv422_en_bit); > } > > static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool > enable) > @@ -824,6 +826,7 @@ static const struct mtk_dpi_conf mt8173_conf = { > .dimension_mask = HPW_MASK, > .hvsize_mask = HSIZE_MASK, > .channel_swap_shift = CH_SWAP, > + .yuv422_en_bit = YUV422_EN, > .limit = &mtk_dpi_limit, > }; > > @@ -839,6 +842,7 @@ static const struct mtk_dpi_conf mt2701_conf = { > .dimension_mask = HPW_MASK, > .hvsize_mask = HSIZE_MASK, > .channel_swap_shift = CH_SWAP, > + .yuv422_en_bit = YUV422_EN, > .limit = &mtk_dpi_limit, > }; > > @@ -853,6 +857,7 @@ static const struct mtk_dpi_conf mt8183_conf = { > .dimension_mask = HPW_MASK, > .hvsize_mask = HSIZE_MASK, > .channel_swap_shift = CH_SWAP, > + .yuv422_en_bit = YUV422_EN, > .limit = &mtk_dpi_limit, > }; > > @@ -867,6 +872,7 @@ static const struct mtk_dpi_conf mt8192_conf = { > .dimension_mask = HPW_MASK, > .hvsize_mask = HSIZE_MASK, > .channel_swap_shift = CH_SWAP, > + .yuv422_en_bit = YUV422_EN, > .limit = &mtk_dpi_limit, > }; >