From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 930D4C43334 for ; Tue, 21 Jun 2022 08:05:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346525AbiFUIFj (ORCPT ); Tue, 21 Jun 2022 04:05:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348059AbiFUIFT (ORCPT ); Tue, 21 Jun 2022 04:05:19 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4DEF9598; Tue, 21 Jun 2022 01:05:17 -0700 (PDT) X-UUID: e0277822d01a440bb699fe1d22a5f8a0-20220621 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:c17b9320-9d59-46d2-9efc-5410dfa22f82,OB:10,L OB:30,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,A CTION:release,TS:45 X-CID-INFO: VERSION:1.1.6,REQID:c17b9320-9d59-46d2-9efc-5410dfa22f82,OB:10,LOB :30,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:45 X-CID-META: VersionHash:b14ad71,CLOUDID:0889a02d-1756-4fa3-be7f-474a6e4be921,C OID:8d11524cbd9e,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: e0277822d01a440bb699fe1d22a5f8a0-20220621 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 940616836; Tue, 21 Jun 2022 16:05:10 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 21 Jun 2022 16:05:09 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 21 Jun 2022 16:05:09 +0800 Message-ID: Subject: Re: [PATCH v11 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver From: CK Hu To: Bo-Chen Chen , , , , , , , , , , CC: , , , , , , , , , , , Date: Tue, 21 Jun 2022 16:05:08 +0800 In-Reply-To: <20220610105522.13449-6-rex-bc.chen@mediatek.com> References: <20220610105522.13449-1-rex-bc.chen@mediatek.com> <20220610105522.13449-6-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen > --- [snip] > + > +static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp) > +{ > + u8 val; > + struct mtk_dp_train_info *train_info = &mtk_dp->train_info; > + > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, > DP_SET_POWER_D0); > + usleep_range(2000, 5000); > + > + drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap); > + > + mtk_dp->rx_cap[DP_TRAINING_AUX_RD_INTERVAL] &= > DP_TRAINING_AUX_RD_MASK; You never use mtk_dp->rx_cap[DP_TRAINING_AUX_RD_INTERVAL], why do you modify it? > + > + train_info->link_rate = min_t(int, mtk_dp->max_linkrate, > + mtk_dp->rx_cap[mtk_dp- > >max_linkrate]); > + train_info->lane_count = min_t(int, mtk_dp->max_lanes, > + drm_dp_max_lane_count(mtk_dp- > >rx_cap)); > + > + train_info->tps3 = drm_dp_tps3_supported(mtk_dp->rx_cap); > + train_info->tps4 = drm_dp_tps4_supported(mtk_dp->rx_cap); > + > + train_info->sink_ssc = !!(mtk_dp->rx_cap[DP_MAX_DOWNSPREAD] & > + DP_MAX_DOWNSPREAD_0_5); > + train_info->sink_ssc = drm_dp_max_downspread(mtk_dp->rx_cap); Regards, CK > + train_info->sink_ssc = false; > + > + drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val); > + if (val & DP_MST_CAP) { > + /* Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 */ > + drm_dp_dpcd_readb(&mtk_dp->aux, > + DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0, > &val); > + if (val) > + drm_dp_dpcd_writeb(&mtk_dp->aux, > + DP_DEVICE_SERVICE_IRQ_VECTOR > _ESI0, > + val); > + } > + > + return 0; > +}