From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 079E2C43334 for ; Tue, 21 Jun 2022 12:21:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349239AbiFUMVj (ORCPT ); Tue, 21 Jun 2022 08:21:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350135AbiFUMV3 (ORCPT ); Tue, 21 Jun 2022 08:21:29 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDF5E22B3C; Tue, 21 Jun 2022 05:21:27 -0700 (PDT) X-UUID: e94fb377026848c1af657358276e1a8d-20220621 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:63699e81-a3ed-478e-b6ec-5d68422d7f2f,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:45 X-CID-INFO: VERSION:1.1.6,REQID:63699e81-a3ed-478e-b6ec-5d68422d7f2f,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTIO N:release,TS:45 X-CID-META: VersionHash:b14ad71,CLOUDID:58661338-5e4b-44d7-80b2-bb618cb09d29,C OID:b4703f8f6c85,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: e94fb377026848c1af657358276e1a8d-20220621 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 388077197; Tue, 21 Jun 2022 20:21:24 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 21 Jun 2022 20:21:23 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 21 Jun 2022 20:21:22 +0800 Message-ID: Subject: Re: [PATCH v11 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver From: Rex-BC Chen To: CK Hu , "chunkuang.hu@kernel.org" , "p.zabel@pengutronix.de" , "daniel@ffwll.ch" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "mripard@kernel.org" , "tzimmermann@suse.de" , "matthias.bgg@gmail.com" , "deller@gmx.de" , "airlied@linux.ie" CC: "msp@baylibre.com" , "granquet@baylibre.com" , Jitao Shi =?UTF-8?Q?=28=E7=9F=B3=E8=AE=B0=E6=B6=9B=29?= , "wenst@chromium.org" , "angelogioacchino.delregno@collabora.com" , "dri-devel@lists.freedesktop.org" , "linux-mediatek@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-fbdev@vger.kernel.org" , Project_Global_Chrome_Upstream_Group Date: Tue, 21 Jun 2022 20:21:22 +0800 In-Reply-To: <017bb546af028e881ccd914fad5ac00030199199.camel@mediatek.com> References: <20220610105522.13449-1-rex-bc.chen@mediatek.com> <20220610105522.13449-6-rex-bc.chen@mediatek.com> <7a0630c68f2754343521daf7b638a20b44e55624.camel@mediatek.com> <017bb546af028e881ccd914fad5ac00030199199.camel@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org On Mon, 2022-06-20 at 11:19 +0800, CK Hu wrote: > On Mon, 2022-06-20 at 11:12 +0800, CK Hu wrote: > > On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > > > From: Markus Schneider-Pargmann > > > > > > This patch adds a embedded displayport driver for the MediaTek > > > mt8195 > > > SoC. > > > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > > DisplayPort 1.4 with up to 4 lanes. > > > > > > The driver creates a child device for the phy. The child device > > > will > > > never exist without the parent being active. As they are sharing > > > a > > > register range, the parent passes a regmap pointer to the child > > > so > > > that > > > both can work with the same register range. The phy driver sets > > > device > > > data that is read by the parent to get the phy device that can be > > > used > > > to control the phy properties. > > > > > > This driver is based on an initial version by > > > Jitao shi > > > > > > Signed-off-by: Markus Schneider-Pargmann > > > Signed-off-by: Guillaume Ranquet > > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > > Signed-off-by: Bo-Chen Chen > > > --- > > > > [snip] > > > > > + > > > +static void mtk_dp_calculate_pixrate(struct mtk_dp *mtk_dp) > > > +{ > > > + u8 target_frame_rate = 60; > > > + u32 target_pixel_clk; > > > + struct drm_display_mode mode; > > > + struct mtk_dp_timings *timings = &mtk_dp->info.timings; > > > + > > > + drm_display_mode_from_videomode(&timings->vm, &mode); > > > + > > > + if (mtk_dp->info.timings.frame_rate > 0) { > > > + target_frame_rate = mtk_dp->info.timings.frame_rate; > > > + target_pixel_clk = mode.htotal * mode.vtotal * > > > + target_frame_rate; > > > + } else if (mtk_dp->info.timings.pix_rate_khz > 0) { > > > + target_pixel_clk = mtk_dp->info.timings.pix_rate_khz * > > > 1000; > > > + } else { > > > + target_pixel_clk = mode.htotal * mode.vtotal * > > > + target_frame_rate; > > > + } > > > + > > > + mtk_dp->info.timings.pix_rate_khz = target_pixel_clk / 1000; > > > > It seems that pix_rate_khz is used only here and does not used in > > another place, so pix_rate_khz is useless, remove it. > > It seems that frame_rate is also redundant, so remove it. > > Regards, > CK > I think we do use this variable in mtk_dp_parse_drm_mode_timings() We use this variable to get target framerate. BRs, Bo-Chen > > > > Regards, > > CK > > > > > +} > > > + > >