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[188.155.201.27]) by smtp.googlemail.com with ESMTPSA id g4-20020a170906520400b006e0b798a0b8sm490009ejm.94.2022.03.25.10.36.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Mar 2022 10:36:37 -0700 (PDT) Message-ID: Date: Fri, 25 Mar 2022 18:36:35 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 03/22] dt-bindings: mediatek,dp_phy: Add Display Port PHY binding Content-Language: en-US To: Guillaume Ranquet , chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com References: <20220325171511.23493-1-granquet@baylibre.com> <20220325171511.23493-4-granquet@baylibre.com> From: Krzysztof Kozlowski In-Reply-To: <20220325171511.23493-4-granquet@baylibre.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org On 25/03/2022 18:14, Guillaume Ranquet wrote: > This phy controller is embedded in the Display Port Controller on mt8195 SoCs. > > Signed-off-by: Guillaume Ranquet > --- > .../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml > new file mode 100644 > index 000000000000..4180d40f4fa7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml > @@ -0,0 +1,43 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2022 MediaTek > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Display Port PHY binding Skip "binding" > + > +maintainers: > + - CK Hu > + - Jitao shi > + > +description: | > + Device tree bindings for the Mediatek (embedded) Display Port PHY > + present on some Mediatek SoCs. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8195-dp-phy > + > + regmap: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: Phandle to the Display Port node. Need a vendor prefix and descriptive suffix (e.g. mediatek,dp-syscon). > + > + "#phy-cells": > + const: 0 > + > +required: > + - compatible > + - regmap > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + dp_phy: dp_phy { Generic node name: just phy. Also underscores shoulk not be in node name. > + compatible = "mediatek,mt8195-dp-phy"; > + regmap = <&dp_tx>; > + #phy-cells = <0>; > + }; Best regards, Krzysztof