* Re: [PATCH] fb: split out framebuffer initialization from allocation
From: Florian Tobias Schandinat @ 2011-11-19 12:08 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <1321308088-6327-1-git-send-email-timur@freescale.com>
Hi Bruno,
On 11/19/2011 11:47 AM, Bruno Prémont wrote:
> Hi Florian, Timur,
>
> On Sat, 19 November 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de> wrote:
>> On 11/17/2011 08:19 PM, Timur Tabi wrote:
>>> Timur Tabi wrote:
>>>> Introduce functions framebuffer_init() and framebuffer_cleanup() to allow
>>>> the initialization of a user-allocated fb_info object.
>>>>
>>>> framebuffer_alloc() allows for appending a private data structure when it
>>>> allocates the fb_info object. However, a driver that registers multiple
>>>> framebuffers for one device may also need another private data structure
>>>> for the device itself. framebuffer_init() allows such drivers to store
>>>> the fb_info objects in the device-specific private data structure,
>>>> thereby simplifying memory allocation.
>>>>
>>>> Signed-off-by: Timur Tabi <timur@freescale.com>
>>>
>>> Florian,
>>>
>>> Any comments on this patch? If you're okay with the change, I want to take
>>> advantage of it in my framebuffer driver.
>>
>> Of course you want, otherwise I'd be wondering why you are sending this patch
>> at all.
>>
>> But I don't see any advantages of your approach. Instead of pointers to fb_info
>> with this patch you could embed fb_info directly in your data structure but that
>> is barely a difference for a programmer I'd think. You'd still have to call your
>> new functions on init/exit so the amount of function calls needed is the same
>> with or without the patch (I could see an advantage if alloc and release were
>> pure memory allocations). Or is this all about handling the case when fb_alloc
>> fails?
>> Historically some drivers don't even call alloc but have their own fb_info and
>> call only register. I do not want to add yet another way of doing framebuffer
>> initialization unless you can clearly show its benefits.
>
> Wouldn't it even make sense to move some more of the initialization of fb_info
> out of fb registration into this new init funtion? (I'm thinking about initializing
> mutexes and the like)
This would require someone going through all framebuffers and change them to use
the new fb_init function if they don't use fb_alloc. I'd accept this patch as an
improvement iff someone would do this. Than the number of variation of doing
framebuffer initialization would remain the same. Of course the same should be
done for fb_cleanup.
Best regards,
Florian Tobias Schandinat
> This way fb_info could be used before being registered. Registration would then
> be reduced to makeing the framebuffer visible to userspace and listed in
> registered_fb[].
>
> This way framebuffer_alloc() would be no more that kzalloc(), framebuffer_init()
> would setup all "non-zero" fields of fb_info (including setup of all mutexes, one
> of which is currently being done by framebuffer_alloc() and the rest by
> do_register_framebuffer()!).
>
> Bruno
>
>> Best regards,
>>
>> Florian Tobias Schandinat
>
^ permalink raw reply
* Re: [PATCH] fb: split out framebuffer initialization from
From: Bruno Prémont @ 2011-11-19 11:47 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <1321308088-6327-1-git-send-email-timur@freescale.com>
Hi Florian, Timur,
On Sat, 19 November 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de> wrote:
> On 11/17/2011 08:19 PM, Timur Tabi wrote:
> > Timur Tabi wrote:
> >> Introduce functions framebuffer_init() and framebuffer_cleanup() to allow
> >> the initialization of a user-allocated fb_info object.
> >>
> >> framebuffer_alloc() allows for appending a private data structure when it
> >> allocates the fb_info object. However, a driver that registers multiple
> >> framebuffers for one device may also need another private data structure
> >> for the device itself. framebuffer_init() allows such drivers to store
> >> the fb_info objects in the device-specific private data structure,
> >> thereby simplifying memory allocation.
> >>
> >> Signed-off-by: Timur Tabi <timur@freescale.com>
> >
> > Florian,
> >
> > Any comments on this patch? If you're okay with the change, I want to take
> > advantage of it in my framebuffer driver.
>
> Of course you want, otherwise I'd be wondering why you are sending this patch
> at all.
>
> But I don't see any advantages of your approach. Instead of pointers to fb_info
> with this patch you could embed fb_info directly in your data structure but that
> is barely a difference for a programmer I'd think. You'd still have to call your
> new functions on init/exit so the amount of function calls needed is the same
> with or without the patch (I could see an advantage if alloc and release were
> pure memory allocations). Or is this all about handling the case when fb_alloc
> fails?
> Historically some drivers don't even call alloc but have their own fb_info and
> call only register. I do not want to add yet another way of doing framebuffer
> initialization unless you can clearly show its benefits.
Wouldn't it even make sense to move some more of the initialization of fb_info
out of fb registration into this new init funtion? (I'm thinking about initializing
mutexes and the like)
This way fb_info could be used before being registered. Registration would then
be reduced to makeing the framebuffer visible to userspace and listed in
registered_fb[].
This way framebuffer_alloc() would be no more that kzalloc(), framebuffer_init()
would setup all "non-zero" fields of fb_info (including setup of all mutexes, one
of which is currently being done by framebuffer_alloc() and the rest by
do_register_framebuffer()!).
Bruno
> Best regards,
>
> Florian Tobias Schandinat
^ permalink raw reply
* Re: [PATCH v3.1] [resend] Resurrect Intel740 driver: i740fb
From: Ondrej Zary @ 2011-11-19 11:11 UTC (permalink / raw)
To: Tabi Timur-B04825
Cc: linux-fbdev@vger.kernel.org, Florian Tobias Schandinat,
Paul Mundt, Kernel development list
In-Reply-To: <CAOZdJXVx88nEAQkL13n1QXVw=kOe03QsD=pffHoZ8gecL7u8dA@mail.gmail.com>
On Saturday 19 November 2011 00:53:27 Tabi Timur-B04825 wrote:
> On Fri, Nov 18, 2011 at 2:54 PM, Ondrej Zary <linux@rainbow-software.org>
wrote:
> > Hello,
> > this is an v3 attempt to resurrect an old (like 2.4.19) out-of-tree
> > driver for Intel740 graphics cards and modify it for recent kernels. The
> > old driver is located at:
> > http://sourceforge.net/projects/i740fbdev/files/
>
> Would you please run checkpatch.pl on the patch and fix the complaints
> it has? I get this:
>
> total: 45 errors, 67 warnings, 1619 lines checked
>
> This patch has tons of style problems.
The 45 errors are in i740_calc_fifo(), which now looks good and is readable.
Reformatting according to checkpatch makes it look bad and unredable. This
was already discussed before.
The warnings are lines over 80 characters, which are common in most fb
drivers. Splitting them makes code hard to read.
--
Ondrej Zary
^ permalink raw reply
* Re: [PATCH] fb: split out framebuffer initialization from allocation
From: Florian Tobias Schandinat @ 2011-11-19 5:06 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <1321308088-6327-1-git-send-email-timur@freescale.com>
Hi Timur,
On 11/17/2011 08:19 PM, Timur Tabi wrote:
> Timur Tabi wrote:
>> Introduce functions framebuffer_init() and framebuffer_cleanup() to allow
>> the initialization of a user-allocated fb_info object.
>>
>> framebuffer_alloc() allows for appending a private data structure when it
>> allocates the fb_info object. However, a driver that registers multiple
>> framebuffers for one device may also need another private data structure
>> for the device itself. framebuffer_init() allows such drivers to store
>> the fb_info objects in the device-specific private data structure,
>> thereby simplifying memory allocation.
>>
>> Signed-off-by: Timur Tabi <timur@freescale.com>
>
> Florian,
>
> Any comments on this patch? If you're okay with the change, I want to take
> advantage of it in my framebuffer driver.
Of course you want, otherwise I'd be wondering why you are sending this patch
at all.
But I don't see any advantages of your approach. Instead of pointers to fb_info
with this patch you could embed fb_info directly in your data structure but that
is barely a difference for a programmer I'd think. You'd still have to call your
new functions on init/exit so the amount of function calls needed is the same
with or without the patch (I could see an advantage if alloc and release were
pure memory allocations). Or is this all about handling the case when fb_alloc
fails?
Historically some drivers don't even call alloc but have their own fb_info and
call only register. I do not want to add yet another way of doing framebuffer
initialization unless you can clearly show its benefits.
Best regards,
Florian Tobias Schandinat
^ permalink raw reply
* Re: [PATCH v3.1] [resend] Resurrect Intel740 driver: i740fb
From: Tabi Timur-B04825 @ 2011-11-18 23:53 UTC (permalink / raw)
To: Ondrej Zary
Cc: linux-fbdev@vger.kernel.org, Florian Tobias Schandinat,
Paul Mundt, Kernel development list
In-Reply-To: <201111182154.45139.linux@rainbow-software.org>
On Fri, Nov 18, 2011 at 2:54 PM, Ondrej Zary <linux@rainbow-software.org> wrote:
> Hello,
> this is an v3 attempt to resurrect an old (like 2.4.19) out-of-tree driver for
> Intel740 graphics cards and modify it for recent kernels. The old driver is
> located at: http://sourceforge.net/projects/i740fbdev/files/
Would you please run checkpatch.pl on the patch and fix the complaints
it has? I get this:
total: 45 errors, 67 warnings, 1619 lines checked
This patch has tons of style problems.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* [PATCH v3.1] [resend] Resurrect Intel740 driver: i740fb
From: Ondrej Zary @ 2011-11-18 20:54 UTC (permalink / raw)
To: linux-fbdev
Cc: Florian Tobias Schandinat, Paul Mundt, Kernel development list
Hello,
this is an v3 attempt to resurrect an old (like 2.4.19) out-of-tree driver for
Intel740 graphics cards and modify it for recent kernels. The old driver is
located at: http://sourceforge.net/projects/i740fbdev/files/
It was easier to create a new driver based on skeletonfb, using most of the
low level HW code from the old driver. The DDC code is completely new.
The driver was tested on two 8MB cards: Protac AG240D and Diamond Stealth II
G460.
Changes in v3:
- added suspend/resume support
- fixed x panning
Signed-off-by: Ondrej Zary <linux@rainbow-software.org>
--- linux-2.6.39-rc2-orig/drivers/video/Makefile 2011-04-06 03:30:43.000000000 +0200
+++ linux-2.6.39-rc2/drivers/video/Makefile 2011-07-30 11:34:10.000000000 +0200
@@ -36,6 +36,7 @@ obj-$(CONFIG_FB_CYBER2000) += cyb
obj-$(CONFIG_FB_PM2) += pm2fb.o
obj-$(CONFIG_FB_PM3) += pm3fb.o
+obj-$(CONFIG_FB_I740) += i740fb.o
obj-$(CONFIG_FB_MATROX) += matrox/
obj-$(CONFIG_FB_RIVA) += riva/
obj-$(CONFIG_FB_NVIDIA) += nvidia/
--- linux-2.6.39-rc2-orig/drivers/video/Kconfig 2011-04-06 03:30:43.000000000 +0200
+++ linux-2.6.39-rc2/drivers/video/Kconfig 2011-10-24 23:29:42.000000000 +0200
@@ -1117,6 +1117,17 @@ config FB_RIVA_BACKLIGHT
help
Say Y here if you want to control the backlight of your display.
+config FB_I740
+ tristate "Intel740 support (EXPERIMENTAL)"
+ depends on EXPERIMENTAL && FB && PCI
+ select FB_MODE_HELPERS
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ select VGASTATE
+ help
+ This driver supports graphics cards based on Intel740 chip.
+
config FB_I810
tristate "Intel 810/815 support (EXPERIMENTAL)"
depends on EXPERIMENTAL && FB && PCI && X86_32 && AGP_INTEL
--- /dev/null 2011-10-28 20:05:27.615214131 +0200
+++ linux-2.6.39-rc2/drivers/video/i740fb.c 2011-10-28 20:03:34.000000000 +0200
@@ -0,0 +1,1286 @@
+/*
+ * i740fb - framebuffer driver for Intel740
+ * Copyright (c) 2011 Ondrej Zary
+ *
+ * Based on old i740fb driver (c) 2001-2002 Andrey Ulanov <drey@rt.mipt.ru> which was partially based on:
+ * VGA 16-color framebuffer driver (c) 1999 Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
+ * i740 driver from XFree86 (c) 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
+ * i740fb by Patrick LERDA, v0.9
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <linux/console.h>
+#include <video/vga.h>
+
+#ifdef CONFIG_MTRR
+#include <asm/mtrr.h>
+#endif
+
+#include "i740_reg.h"
+
+static char *mode_option __devinitdata;
+
+#ifdef CONFIG_MTRR
+static int mtrr __devinitdata = 1;
+#endif
+
+struct i740fb_par {
+ unsigned char __iomem *regs;
+ bool has_sgram;
+#ifdef CONFIG_MTRR
+ int mtrr_reg;
+#endif
+ bool ddc_registered;
+ struct i2c_adapter ddc_adapter;
+ struct i2c_algo_bit_data ddc_algo;
+ u32 pseudo_palette[16];
+ struct mutex open_lock;
+ unsigned int ref_count;
+
+ u8 crtc[VGA_CRT_C];
+ u8 atc[VGA_ATT_C];
+ u8 gdc[VGA_GFX_C];
+ u8 seq[VGA_SEQ_C];
+ u8 misc;
+ u8 vss;
+
+ /* i740 specific registers */
+ u8 display_cntl;
+ u8 pixelpipe_cfg0;
+ u8 pixelpipe_cfg1;
+ u8 pixelpipe_cfg2;
+ u8 video_clk2_m;
+ u8 video_clk2_n;
+ u8 video_clk2_mn_msbs;
+ u8 video_clk2_div_sel;
+ u8 pll_cntl;
+ u8 address_mapping;
+ u8 io_cntl;
+ u8 bitblt_cntl;
+ u8 ext_vert_total;
+ u8 ext_vert_disp_end;
+ u8 ext_vert_sync_start;
+ u8 ext_vert_blank_start;
+ u8 ext_horiz_total;
+ u8 ext_horiz_blank;
+ u8 ext_offset;
+ u8 interlace_cntl;
+ u32 lmi_fifo_watermark;
+ u8 ext_start_addr;
+ u8 ext_start_addr_hi;
+};
+
+#define DACSPEED8 203
+#define DACSPEED16 163
+#define DACSPEED24_SG 136
+#define DACSPEED24_SD 128
+#define DACSPEED32 86
+
+static struct fb_fix_screeninfo i740fb_fix __devinitdata = {
+ .id = "i740fb",
+ .type = FB_TYPE_PACKED_PIXELS,
+ .visual = FB_VISUAL_TRUECOLOR,
+ .xpanstep = 8,
+ .ypanstep = 1,
+ .accel = FB_ACCEL_NONE,
+};
+
+static inline void i740outb(struct i740fb_par *par, u16 port, u8 val)
+{
+ vga_mm_w(par->regs, port, val);
+}
+static inline u8 i740inb(struct i740fb_par *par, u16 port)
+{
+ return vga_mm_r(par->regs, port);
+}
+static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val)
+{
+ vga_mm_w_fast(par->regs, port, reg, val);
+}
+static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg)
+{
+ vga_mm_w(par->regs, port, reg);
+ return vga_mm_r(par->regs, port+1);
+}
+static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg, u8 val, u8 mask)
+{
+ vga_mm_w_fast(par->regs, port, reg, (val & mask) | (i740inreg(par, port, reg) & ~mask));
+}
+static inline void i740outb_p(struct i740fb_par *par, u16 port, u8 val)
+{
+ vga_mm_w(par->regs, port, val);
+}
+static inline u8 i740inb_p(struct i740fb_par *par, unsigned short port)
+{
+ return vga_mm_r(par->regs, port);
+}
+
+#define REG_DDC_DRIVE 0x62
+#define REG_DDC_STATE 0x63
+#define DDC_SCL (1 << 3)
+#define DDC_SDA (1 << 2)
+
+static void i740fb_ddc_setscl(void *data, int val)
+{
+ struct i740fb_par *par = data;
+ unsigned char reg;
+
+ i740outreg(par, XRX, REG_DDC_DRIVE,
+ i740inreg(par, XRX, REG_DDC_DRIVE) | DDC_SCL);
+
+ reg = i740inreg(par, XRX, REG_DDC_STATE);
+ if (val)
+ reg |= DDC_SCL;
+ else
+ reg &= ~DDC_SCL;
+ i740outreg(par, XRX, REG_DDC_STATE, reg);
+}
+
+static void i740fb_ddc_setsda(void *data, int val)
+{
+ struct i740fb_par *par = data;
+ unsigned char reg;
+
+ i740outreg(par, XRX, REG_DDC_DRIVE,
+ i740inreg(par, XRX, REG_DDC_DRIVE) | DDC_SDA);
+
+ reg = i740inreg(par, XRX, REG_DDC_STATE);
+ if (val)
+ reg |= DDC_SDA;
+ else
+ reg &= ~DDC_SDA;
+ i740outreg(par, XRX, REG_DDC_STATE, reg);
+}
+
+static int i740fb_ddc_getscl(void *data)
+{
+ struct i740fb_par *par = data;
+
+ i740outreg(par, XRX, REG_DDC_DRIVE,
+ i740inreg(par, XRX, REG_DDC_DRIVE) & ~DDC_SCL);
+
+ return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
+}
+
+static int i740fb_ddc_getsda(void *data)
+{
+ struct i740fb_par *par = data;
+
+ i740outreg(par, XRX, REG_DDC_DRIVE,
+ i740inreg(par, XRX, REG_DDC_DRIVE) & ~DDC_SDA);
+
+ return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
+}
+
+static int __devinit i740fb_setup_ddc_bus(struct fb_info *info)
+{
+ struct i740fb_par *par = info->par;
+
+ strlcpy(par->ddc_adapter.name, info->fix.id,
+ sizeof(par->ddc_adapter.name));
+ par->ddc_adapter.owner = THIS_MODULE;
+ par->ddc_adapter.class = I2C_CLASS_DDC;
+ par->ddc_adapter.algo_data = &par->ddc_algo;
+ par->ddc_adapter.dev.parent = info->device;
+ par->ddc_algo.setsda = i740fb_ddc_setsda;
+ par->ddc_algo.setscl = i740fb_ddc_setscl;
+ par->ddc_algo.getsda = i740fb_ddc_getsda;
+ par->ddc_algo.getscl = i740fb_ddc_getscl;
+ par->ddc_algo.udelay = 10;
+ par->ddc_algo.timeout = 20;
+ par->ddc_algo.data = par;
+
+ i2c_set_adapdata(&par->ddc_adapter, par);
+
+ return i2c_bit_add_bus(&par->ddc_adapter);
+}
+
+static int i740fb_open(struct fb_info *info, int user)
+{
+ struct i740fb_par *par = info->par;
+
+ mutex_lock(&(par->open_lock));
+ par->ref_count++;
+ mutex_unlock(&(par->open_lock));
+
+ return 0;
+}
+
+static int i740fb_release(struct fb_info *info, int user)
+{
+ struct i740fb_par *par = info->par;
+
+ mutex_lock(&(par->open_lock));
+ if (par->ref_count = 0) {
+ mutex_unlock(&(par->open_lock));
+ return -EINVAL;
+ }
+
+ par->ref_count--;
+ mutex_unlock(&(par->open_lock));
+
+ return 0;
+}
+
+static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp)
+{
+ /*
+ * Would like to calculate these values automatically, but a generic
+ * algorithm does not seem possible. Note: These FIFO water mark
+ * values were tested on several cards and seem to eliminate the
+ * all of the snow and vertical banding, but fine adjustments will
+ * probably be required for other cards.
+ */
+
+ u32 wm = 0x18120000;
+
+ switch (bpp) {
+ case 8:
+ if (freq > 200) wm = 0x18120000;
+ else if (freq > 175) wm = 0x16110000;
+ else if (freq > 135) wm = 0x120E0000;
+ else wm = 0x100D0000;
+ break;
+ case 15:
+ case 16:
+ if (par->has_sgram) {
+ if (freq > 140) wm = 0x2C1D0000;
+ else if (freq > 120) wm = 0x2C180000;
+ else if (freq > 100) wm = 0x24160000;
+ else if (freq > 90) wm = 0x18120000;
+ else if (freq > 50) wm = 0x16110000;
+ else if (freq > 32) wm = 0x13100000;
+ else wm = 0x120E0000;
+ } else {
+ if (freq > 160) wm = 0x28200000;
+ else if (freq > 140) wm = 0x2A1E0000;
+ else if (freq > 130) wm = 0x2B1A0000;
+ else if (freq > 120) wm = 0x2C180000;
+ else if (freq > 100) wm = 0x24180000;
+ else if (freq > 90) wm = 0x18120000;
+ else if (freq > 50) wm = 0x16110000;
+ else if (freq > 32) wm = 0x13100000;
+ else wm = 0x120E0000;
+ }
+ break;
+ case 24:
+ if (par->has_sgram) {
+ if (freq > 130) wm = 0x31200000;
+ else if (freq > 120) wm = 0x2E200000;
+ else if (freq > 100) wm = 0x2C1D0000;
+ else if (freq > 80) wm = 0x25180000;
+ else if (freq > 64) wm = 0x24160000;
+ else if (freq > 49) wm = 0x18120000;
+ else if (freq > 32) wm = 0x16110000;
+ else wm = 0x13100000;
+ } else {
+ if (freq > 120) wm = 0x311F0000;
+ else if (freq > 100) wm = 0x2C1D0000;
+ else if (freq > 80) wm = 0x25180000;
+ else if (freq > 64) wm = 0x24160000;
+ else if (freq > 49) wm = 0x18120000;
+ else if (freq > 32) wm = 0x16110000;
+ else wm = 0x13100000;
+ }
+ break;
+ case 32:
+ if (par->has_sgram) {
+ if (freq > 80) wm = 0x2A200000;
+ else if (freq > 60) wm = 0x281A0000;
+ else if (freq > 49) wm = 0x25180000;
+ else if (freq > 32) wm = 0x18120000;
+ else wm = 0x16110000;
+ } else {
+ if (freq > 80) wm = 0x29200000;
+ else if (freq > 60) wm = 0x281A0000;
+ else if (freq > 49) wm = 0x25180000;
+ else if (freq > 32) wm = 0x18120000;
+ else wm = 0x16110000;
+ }
+ break;
+ }
+
+ return wm;
+}
+
+/* clock calculation from i740fb by Patrick LERDA */
+
+#define I740_RFREQ (1e6)
+#define TARGET_MAX_N 30
+
+#define I740_FFIX 8
+#define I740_REF_FREQ (u32) (66.66666666667 * (1 << I740_FFIX) + 0.5)
+#define I740_MAX_VCO_FREQ (u32)(450.00000000000 * (1 << I740_FFIX) + 0.5)
+
+#define I740_CALC_VCLKfix(m, n, p, d) ((((((m) * I740_REF_FREQ * (4 << ((d) << 1)))) / (n)) + ((1 << (p)) / 2)) / (1 << (p)))
+
+static void i740_calc_vclk(u32 freq_hz, struct i740fb_par *par)
+{
+ u32 freq = freq_hz / (u32)(1e6 / I740_RFREQ);
+ const u32 err_max = freq / (u32)(I740_RFREQ / 0.005 / (1 << I740_FFIX) + 0.5);
+ const u32 err_target = freq / (u32)(I740_RFREQ / 0.001 / (1 << I740_FFIX) + 0.5);
+ u32 err_best = (u32)(512.0 * (1 << I740_FFIX));
+ u32 f_err, f_vco;
+ int m_best = 0, n_best = 0, p_best = 0, d_best = 0;
+ int m, n, i;
+
+ /* find log2(MAX_VCO_FREQ/f_target) */
+ for (i = 0; i < 16; i++)
+ if ((I740_MAX_VCO_FREQ) / (1 << i) < freq / (u32)(I740_RFREQ / (1 << I740_FFIX)))
+ break;
+ i--;
+ p_best = i;
+
+ d_best = 0;
+ f_vco = (freq * (1 << p_best)) / (u32)(I740_RFREQ / (1 << I740_FFIX));
+ freq = freq / (u32)(I740_RFREQ / (1 << I740_FFIX));
+
+ n = 2;
+ do {
+ n++;
+ m = ((f_vco * n) / I740_REF_FREQ + 2) / 4;
+
+ if (m < 3)
+ m = 3;
+
+ {
+ u32 f_out = I740_CALC_VCLKfix(m, n, p_best, d_best);
+
+ f_err = (freq - f_out);
+
+ if (abs(f_err) < err_max) {
+ m_best = m;
+ n_best = n;
+ err_best = f_err;
+ }
+ }
+ } while ((abs(f_err) >= err_target) &&
+ ((n <= TARGET_MAX_N) || (abs(err_best) > err_max)));
+
+ if (abs(f_err) < err_target) {
+ m_best = m;
+ n_best = n;
+ }
+
+ par->video_clk2_m = (m_best-2) & 0xFF;
+ par->video_clk2_n = (n_best-2) & 0xFF;
+ par->video_clk2_mn_msbs = ((((n_best-2) >> 4) & VCO_N_MSBS) |
+ (((m_best-2) >> 8) & VCO_M_MSBS));
+ par->video_clk2_div_sel = ((p_best << 4) | (d_best ? 4 : 0) | REF_DIV_1);
+}
+
+static int i740fb_decode_var(const struct fb_var_screeninfo *var, struct i740fb_par *par, struct fb_info *info)
+{
+ /*
+ * Get the video params out of 'var'. If a value doesn't fit, round it up,
+ * if it's too big, return -EINVAL.
+ */
+
+ u32 xres, right, hslen, left, xtotal;
+ u32 yres, lower, vslen, upper, ytotal;
+ u32 vxres, xoffset, vyres, yoffset;
+ u32 bpp, base, dacspeed24;
+ u8 r7;
+ int i;
+
+ dev_dbg(info->device, "decode_var: xres: %i, yres: %i, xres_v: %i, xres_v: %i\n",
+ var->xres, var->yres, var->xres_virtual, var->xres_virtual);
+ dev_dbg(info->device, " xoff: %i, yoff: %i, bpp: %i, graysc: %i\n",
+ var->xoffset, var->yoffset, var->bits_per_pixel, var->grayscale);
+ dev_dbg(info->device, " activate: %i, nonstd: %i, vmode: %i\n",
+ var->activate, var->nonstd, var->vmode);
+ dev_dbg(info->device, " pixclock: %i, hsynclen:%i, vsynclen:%i\n",
+ var->pixclock, var->hsync_len, var->vsync_len);
+ dev_dbg(info->device, " left: %i, right: %i, up:%i, lower:%i\n",
+ var->left_margin, var->right_margin, var->upper_margin, var->lower_margin);
+
+
+ bpp = var->bits_per_pixel;
+ switch (bpp) {
+ case 1 ... 8:
+ bpp = 8;
+ if ((((u32)1e6) / var->pixclock) > DACSPEED8) {
+ dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 8bpp)\n", 1000000 / var->pixclock, DACSPEED8);
+ return -EINVAL;
+ }
+ break;
+ case 9 ... 15:
+ bpp = 15;
+ case 16:
+ if ((((u32)1e6) / var->pixclock) > DACSPEED16) {
+ dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 15/16bpp)\n", 1000000 / var->pixclock, DACSPEED16);
+ return -EINVAL;
+ }
+ break;
+ case 17 ... 24:
+ bpp = 24;
+ dacspeed24 = par->has_sgram ? DACSPEED24_SG : DACSPEED24_SD;
+ if ((((u32)1e6) / var->pixclock) > dacspeed24) {
+ dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 24bpp)\n", 1000000 / var->pixclock, dacspeed24);
+ return -EINVAL;
+ }
+ break;
+ case 25 ... 32:
+ bpp = 32;
+ if ((((u32)1e6) / var->pixclock) > DACSPEED32) {
+ dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 32bpp)\n", 1000000 / var->pixclock, DACSPEED32);
+ return -EINVAL;
+ }
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ xres = (var->xres + 7) & ~7;
+ vxres = (var->xres_virtual + 0xF) & ~0xF;
+ if (vxres < xres)
+ vxres = xres;
+
+ xoffset = (var->xoffset + 7) & ~7;
+ xoffset = var->xoffset;
+ if (xres + xoffset > vxres)
+ xoffset = vxres - xres;
+
+ left = (var->left_margin + 7) & ~7;
+ right = (var->right_margin + 7) & ~7;
+ hslen = (var->hsync_len + 7) & ~7;
+
+ yres = var->yres;
+ vyres = var->yres_virtual;
+ if (yres > vyres)
+ vyres = yres;
+
+ yoffset = var->yoffset;
+ if (yres + yoffset > vyres)
+ yoffset = vyres - yres;
+
+ lower = var->lower_margin;
+ vslen = var->vsync_len;
+ upper = var->upper_margin;
+
+ if (vxres * vyres * ((bpp + 1) / 8) > info->screen_size || vyres = yres) {
+ vyres = info->screen_size / vxres / ((bpp + 1) / 8);
+ if (vyres < yres)
+ return -ENOMEM;
+ }
+
+ if (yoffset + yres > vyres)
+ yoffset = vyres - yres;
+
+ xtotal = xres + right + hslen + left;
+ ytotal = yres + lower + vslen + upper;
+
+ par->crtc[VGA_CRTC_H_TOTAL] = (xtotal >> 3) - 5;
+ par->crtc[VGA_CRTC_H_DISP] = (xres >> 3) - 1;
+ par->crtc[VGA_CRTC_H_BLANK_START] = ((xres + right) >> 3) - 1;
+ par->crtc[VGA_CRTC_H_SYNC_START] = (xres + right) >> 3;
+ par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F)
+ | ((((xres + right + hslen) >> 3) & 0x20) << 2);
+ par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F) | 0x80;
+
+ par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
+
+ r7 = 0x10; /* disable linecompare */
+ if (ytotal & 0x100)
+ r7 |= 0x01;
+ if (ytotal & 0x200)
+ r7 |= 0x20;
+
+ par->crtc[VGA_CRTC_PRESET_ROW] = 0;
+ par->crtc[VGA_CRTC_MAX_SCAN] = 0x40; /* 1 scanline, no linecmp */
+ if (var->vmode & FB_VMODE_DOUBLE)
+ par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
+ par->crtc[VGA_CRTC_CURSOR_START] = 0x00;
+ par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
+ par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
+ par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
+ par->crtc[VGA_CRTC_V_DISP_END] = yres-1;
+ if ((yres-1) & 0x100)
+ r7 |= 0x02;
+ if ((yres-1) & 0x200)
+ r7 |= 0x40;
+
+ par->crtc[VGA_CRTC_V_BLANK_START] = yres + lower - 1;
+ par->crtc[VGA_CRTC_V_SYNC_START] = yres + lower - 1;
+ if ((yres + lower - 1) & 0x100)
+ r7 |= 0x0C;
+ if ((yres + lower - 1) & 0x200) {
+ par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20;
+ r7 |= 0x80;
+ }
+
+ par->crtc[VGA_CRTC_V_SYNC_END] = ((yres + lower - 1 + vslen) & 0x0F) & ~0x10; /* disabled IRQ */
+ par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF; /* 0x7F for original VGA, but some SVGA chips requires all 8 bits to set */
+
+ par->crtc[VGA_CRTC_UNDERLINE] = 0x00;
+ par->crtc[VGA_CRTC_MODE] = 0xC3 ;
+ par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
+ par->crtc[VGA_CRTC_OVERFLOW] = r7;
+
+ par->vss = 0x00; /* 3DA */
+
+ for (i = 0x00; i < 0x10; i++)
+ par->atc[i] = i;
+ par->atc[VGA_ATC_MODE] = 0x81;
+ par->atc[VGA_ATC_OVERSCAN] = 0x00; /* 0 for EGA, 0xFF for VGA */
+ par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
+ /*par->atc[VGA_ATC_PEL] = xoffset & 7;*/
+ par->atc[VGA_ATC_COLOR_PAGE] = 0x00;
+
+ par->misc = 0xC3;
+ if (var->sync & FB_SYNC_HOR_HIGH_ACT)
+ par->misc &= ~0x40;
+ if (var->sync & FB_SYNC_VERT_HIGH_ACT)
+ par->misc &= ~0x80;
+
+ par->seq[VGA_SEQ_CLOCK_MODE] = 0x01;
+ par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
+ par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
+ par->seq[VGA_SEQ_MEMORY_MODE] = 0x06;
+
+ par->gdc[VGA_GFX_SR_VALUE] = 0x00;
+ par->gdc[VGA_GFX_SR_ENABLE] = 0x00;
+ par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
+ par->gdc[VGA_GFX_DATA_ROTATE] = 0x00;
+ par->gdc[VGA_GFX_PLANE_READ] = 0;
+ par->gdc[VGA_GFX_MODE] = 0x02;
+ par->gdc[VGA_GFX_MISC] = 0x05;
+ par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
+ par->gdc[VGA_GFX_BIT_MASK] = 0xFF;
+
+ base = (yoffset * vxres + (xoffset & ~7)) >> 2;
+ switch (bpp) {
+ case 8:
+ par->crtc[VGA_CRTC_OFFSET] = vxres >> 3;
+ par->ext_offset = vxres >> 11;
+ par->pixelpipe_cfg1 = DISPLAY_8BPP_MODE;
+ par->bitblt_cntl = COLEXP_8BPP;
+ break;
+ case 15: /* 0rrrrrgg gggbbbbb */
+ case 16: /* rrrrrggg gggbbbbb */
+ par->pixelpipe_cfg1 = (var->green.length = 6) ? DISPLAY_16BPP_MODE : DISPLAY_15BPP_MODE;
+ par->crtc[VGA_CRTC_OFFSET] = vxres >> 2;
+ par->ext_offset = vxres >> 10;
+ par->bitblt_cntl = COLEXP_16BPP;
+ base *= 2;
+ break;
+ case 24:
+ par->crtc[VGA_CRTC_OFFSET] = (vxres * 3) >> 3;
+ par->ext_offset = (vxres * 3) >> 11;
+ par->pixelpipe_cfg1 = DISPLAY_24BPP_MODE;
+ par->bitblt_cntl = COLEXP_24BPP;
+ base &= 0xFFFFFFFE; /* ...ignore the last bit. */
+ base *= 3;
+ break;
+ case 32:
+ par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
+ par->ext_offset = vxres >> 9;
+ par->pixelpipe_cfg1 = DISPLAY_32BPP_MODE;
+ par->bitblt_cntl = COLEXP_RESERVED; /* Not implemented on i740 */
+ base *= 4;
+ break;
+ }
+
+ par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
+ par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8;
+ par->ext_start_addr = ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
+ par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
+
+ par->pixelpipe_cfg0 = DAC_8_BIT;
+
+ par->pixelpipe_cfg2 = DISPLAY_GAMMA_ENABLE | OVERLAY_GAMMA_ENABLE;
+ par->io_cntl = EXTENDED_CRTC_CNTL;
+ par->address_mapping = LINEAR_MODE_ENABLE | PAGE_MAPPING_ENABLE;
+ par->display_cntl = HIRES_MODE;
+
+ /* Set the MCLK freq */
+ par->pll_cntl = PLL_MEMCLK_100000KHZ; /* 100 MHz -- use as default */
+
+ /* Calculate the extended CRTC regs */
+ par->ext_vert_total = (ytotal - 2) >> 8;
+ par->ext_vert_disp_end = (yres - 1) >> 8;
+ par->ext_vert_sync_start = (yres + lower) >> 8;
+ par->ext_vert_blank_start = (yres + lower) >> 8;
+ par->ext_horiz_total = ((xtotal >> 3) - 5) >> 8;
+ par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6;
+
+ par->interlace_cntl = INTERLACE_DISABLE;
+
+ /* Set the overscan color to 0. (NOTE: This only affects >8bpp mode.) */
+ par->atc[VGA_ATC_OVERSCAN] = 0;
+
+ /* Calculate VCLK that most closely matches the requested dot clock */
+ i740_calc_vclk((((u32)1e9) / var->pixclock) * (u32)(1e3), par);
+
+ /* Since we program the clocks ourselves, always use VCLK2. */
+ par->misc |= 0x0C;
+
+ /* Calculate the FIFO Watermark and Burst Length. */
+ par->lmi_fifo_watermark = i740_calc_fifo(par, ((int)1e6) / var->pixclock, bpp);
+
+ /*if (!fbmon_valid_timings(var->pixclock, ytotal, xtotal, info))
+ return -EINVAL;*/
+
+ return 0;
+}
+
+static int i740fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ switch (var->bits_per_pixel) {
+ case 8:
+ var->red.offset = var->green.offset = var->blue.offset = 0;
+ var->red.length = var->green.length = var->blue.length = 8;
+ break;
+ case 16:
+ switch (var->green.length) {
+ default:
+ case 5:
+ var->red.offset = 10;
+ var->green.offset = 5;
+ var->blue.offset = 0;
+ var->red.length = var->green.length = var->blue.length = 5;
+ break;
+ case 6:
+ var->red.offset = 11;
+ var->green.offset = 5;
+ var->blue.offset = 0;
+ var->green.length = 6;
+ var->red.length = var->blue.length = 5;
+ break;
+ }
+ break;
+ case 24:
+ var->red.offset = 16;
+ var->green.offset = 8;
+ var->blue.offset = 0;
+ var->red.length = var->green.length = var->blue.length = 8;
+ break;
+ case 32:
+ var->transp.offset = 24;
+ var->red.offset = 16;
+ var->green.offset = 8;
+ var->blue.offset = 0;
+ var->transp.length = var->red.length = var->green.length = var->blue.length = 8;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (var->xres > var->xres_virtual)
+ var->xres_virtual = var->xres;
+
+ if (var->yres > var->yres_virtual)
+ var->yres_virtual = var->yres;
+
+ if (info->monspecs.hfmax && info->monspecs.vfmax &&
+ info->monspecs.dclkmax && fb_validate_mode(var, info) < 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void vga_protect(struct i740fb_par *par)
+{
+ i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, i740inreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE) | 0x20); /* disable the display */
+
+ i740inb(par, 0x3DA);
+ i740outb(par, VGA_ATT_W, 0x00); /* enable pallete access */
+}
+
+static void vga_unprotect(struct i740fb_par *par)
+{
+ i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, i740inreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE) & 0xDF); /* reenable display */
+
+ i740inb(par, 0x3DA);
+ i740outb(par, VGA_ATT_W, 0x20); /* disable pallete access */
+}
+
+static int i740fb_set_par(struct fb_info *info)
+{
+ struct i740fb_par *par = info->par;
+ u32 itemp;
+ int i;
+
+ i = i740fb_decode_var(&info->var, par, info);
+ if (i)
+ return i;
+
+ memset(info->screen_base, 0, info->screen_size);
+
+ vga_protect(par);
+
+ i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
+
+ mdelay(1);
+
+ i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
+ i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
+ i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
+ i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
+
+ i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0 & DAC_8_BIT, 0x80);
+
+ i740inb(par, 0x3DA);
+ i740outb(par, 0x3C0, 0x00);
+
+ /* update misc output register */
+ i740outb(par, VGA_MIS_W, par->misc | 0x01);
+
+ /* synchronous reset on */
+ i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01);
+ /* write sequencer registers */
+ i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, par->seq[VGA_SEQ_CLOCK_MODE] | 0x20);
+ for (i = 2; i < VGA_SEQ_C; i++)
+ i740outreg(par, VGA_SEQ_I, i, par->seq[i]);
+
+ /* synchronous reset off */
+ i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03);
+
+ /* deprotect CRT registers 0-7 */
+ i740outreg(par, VGA_CRT_IC, VGA_CRTC_V_SYNC_END, par->crtc[VGA_CRTC_V_SYNC_END]);
+
+ /* write CRT registers */
+ for (i = 0; i < VGA_CRT_C; i++)
+ i740outreg(par, VGA_CRT_IC, i, par->crtc[i]);
+
+ /* write graphics controller registers */
+ for (i = 0; i < VGA_GFX_C; i++)
+ i740outreg(par, VGA_GFX_I, i, par->gdc[i]);
+
+ /* write attribute controller registers */
+ for (i = 0; i < VGA_ATT_C; i++) {
+ i740inb_p(par, VGA_IS1_RC); /* reset flip-flop */
+ i740outb_p(par, VGA_ATT_IW, i);
+ i740outb_p(par, VGA_ATT_IW, par->atc[i]);
+ }
+
+ i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, par->seq[VGA_SEQ_CLOCK_MODE]);
+
+ i740inb(par, VGA_IS1_RC);
+ i740outb(par, VGA_ATT_IW, 0x20);
+
+ i740outreg(par, VGA_CRT_IC, EXT_VERT_TOTAL, par->ext_vert_total);
+ i740outreg(par, VGA_CRT_IC, EXT_VERT_DISPLAY, par->ext_vert_disp_end);
+ i740outreg(par, VGA_CRT_IC, EXT_VERT_SYNC_START, par->ext_vert_sync_start);
+ i740outreg(par, VGA_CRT_IC, EXT_VERT_BLANK_START, par->ext_vert_blank_start);
+ i740outreg(par, VGA_CRT_IC, EXT_HORIZ_TOTAL, par->ext_horiz_total);
+ i740outreg(par, VGA_CRT_IC, EXT_HORIZ_BLANK, par->ext_horiz_blank);
+ i740outreg(par, VGA_CRT_IC, EXT_OFFSET, par->ext_offset);
+ i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, par->ext_start_addr_hi);
+ i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, par->ext_start_addr);
+
+ i740outreg_mask(par, VGA_CRT_IC, INTERLACE_CNTL, par->interlace_cntl, INTERLACE_ENABLE);
+ i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
+ i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
+ i740outreg_mask(par, XRX, DISPLAY_CNTL, par->display_cntl, VGA_WRAP_MODE | GUI_MODE);
+ i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
+ i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
+
+ i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
+
+ i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1, par->pixelpipe_cfg1, DISPLAY_COLOR_MODE);
+
+ itemp = readl(par->regs + FWATER_BLC);
+ itemp &= ~(LMI_BURST_LENGTH | LMI_FIFO_WATERMARK);
+ itemp |= par->lmi_fifo_watermark;
+ writel(itemp, par->regs + FWATER_BLC);
+
+ i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
+
+ i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY);
+ i740outreg_mask(par, XRX, IO_CTNL, par->io_cntl, EXTENDED_ATTR_CNTL | EXTENDED_CRTC_CNTL);
+
+ if (par->pixelpipe_cfg1 != DISPLAY_8BPP_MODE) {
+ i740outb(par, VGA_PEL_MSK, 0xFF);
+ i740outb(par, VGA_PEL_IW, 0x00);
+ for (i = 0; i < 256; i++) {
+ i740outb_p(par, VGA_PEL_D, (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2);
+ i740outb_p(par, VGA_PEL_D, (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2);
+ i740outb_p(par, VGA_PEL_D, (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2);
+ }
+ }
+
+ /* Wait for screen to stabilize. */
+ mdelay(50);
+ vga_unprotect(par);
+
+ info->fix.line_length = info->var.xres_virtual * info->var.bits_per_pixel / 8;
+ if (info->var.bits_per_pixel = 8)
+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+ else
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+
+ return 0;
+}
+
+static int i740fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info)
+{
+ dev_dbg(info->device, "setcolreg: regno: %i, red=%d, green=%d, blue=%d, transp=%d, bpp=%d\n", regno, red, green, blue, transp, info->var.bits_per_pixel);
+
+ switch (info->var.bits_per_pixel) {
+ case 8:
+ if (regno >= 256)
+ return 1;
+ i740outb(info->par, VGA_PEL_IW, regno);
+ i740outb(info->par, VGA_PEL_D, red >> 8);
+ i740outb(info->par, VGA_PEL_D, green >> 8);
+ i740outb(info->par, VGA_PEL_D, blue >> 8);
+ break;
+ case 15:
+ case 16:
+ if (regno >= 16)
+ return 0;
+ if (info->var.green.length = 5)
+ ((u32 *)info->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
+ else if (info->var.green.length = 6)
+ ((u32 *)info->pseudo_palette)[regno] = (red & 0xF800) | ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
+ else
+ return -EINVAL;
+ break;
+ case 24:
+ case 32:
+ if (regno >= 16)
+ return 0;
+ ((u32 *)info->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | (green & 0xFF00) | ((blue & 0xFF00) >> 8);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int i740fb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct i740fb_par *par = info->par;
+ u32 base = (var->yoffset * var->xres_virtual + (var->xoffset & ~7)) >> 2;
+
+ dev_dbg(info->device, "pan_display: xoffset: %i, yoffset: %i base: %i\n", var->xoffset, var->yoffset, base);
+
+ switch (var->bits_per_pixel) {
+ case 8:
+ break;
+ case 15:
+ case 16:
+ base *= 2;
+ break;
+ case 24:
+ /*
+ * The last bit does not seem to have any effect on the start
+ * address register in 24bpp mode, so...
+ */
+ base &= 0xFFFFFFFE; /* ...ignore the last bit. */
+ base *= 3;
+ break;
+ case 32:
+ base *= 4;
+ break;
+ }
+
+ par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
+ par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8;
+ par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
+ par->ext_start_addr = ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
+ /*par->atc[VGA_ATC_PEL] = var->xoffset & 7;*/
+
+ i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO, base & 0x000000FF);
+ i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_HI, (base & 0x0000FF00) >> 8);
+ i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, (base & 0x3FC00000) >> 22);
+ i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE);
+ /*i740outreg(par, VGA_ATT_W, VGA_ATC_PEL, var->xoffset & 7);*/
+
+ return 0;
+}
+
+static int i740fb_blank(int blank_mode, struct fb_info *info)
+{
+ struct i740fb_par *par = info->par;
+
+ unsigned char SEQ01;
+ int DPMSSyncSelect;
+
+ switch (blank_mode) {
+ case FB_BLANK_UNBLANK:
+ case FB_BLANK_NORMAL:
+ SEQ01 = 0x00;
+ DPMSSyncSelect = HSYNC_ON | VSYNC_ON;
+ break;
+ case FB_BLANK_VSYNC_SUSPEND:
+ SEQ01 = 0x20;
+ DPMSSyncSelect = HSYNC_ON | VSYNC_OFF;
+ break;
+ case FB_BLANK_HSYNC_SUSPEND:
+ SEQ01 = 0x20;
+ DPMSSyncSelect = HSYNC_OFF | VSYNC_ON;
+ break;
+ case FB_BLANK_POWERDOWN:
+ SEQ01 = 0x20;
+ DPMSSyncSelect = HSYNC_OFF | VSYNC_OFF;
+ break;
+ default:
+ return -EINVAL;
+ }
+ /* Turn the screen on/off */
+ i740outb(par, SRX, 0x01);
+ SEQ01 |= i740inb(par, SRX + 1) & ~0x20;
+ i740outb(par, SRX, 0x01);
+ i740outb(par, SRX + 1, SEQ01);
+
+ /* Set the DPMS mode */
+ i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);
+
+ /* Let fbcon do a soft blank for us */
+ return (blank_mode = FB_BLANK_NORMAL) ? 1 : 0;
+}
+
+static struct fb_ops i740fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_open = i740fb_open,
+ .fb_release = i740fb_release,
+ .fb_check_var = i740fb_check_var,
+ .fb_set_par = i740fb_set_par,
+ .fb_setcolreg = i740fb_setcolreg,
+ .fb_blank = i740fb_blank,
+ .fb_pan_display = i740fb_pan_display,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+};
+
+/* ------------------------------------------------------------------------- */
+
+static int __devinit i740fb_probe(struct pci_dev *dev,
+ const struct pci_device_id *ent)
+{
+ struct fb_info *info;
+ struct i740fb_par *par;
+ int ret;
+ bool found = false;
+ u8 *edid;
+
+ info = framebuffer_alloc(sizeof(struct i740fb_par), &(dev->dev));
+ if (!info) {
+ dev_err(&(dev->dev), "cannot allocate framebuffer\n");
+ return -ENOMEM;
+ }
+
+ par = info->par;
+ mutex_init(&par->open_lock);
+
+ info->var.activate = FB_ACTIVATE_NOW;
+ info->var.bits_per_pixel = 8;
+ info->fbops = &i740fb_ops;
+ info->pseudo_palette = par->pseudo_palette;
+
+ ret = pci_enable_device(dev);
+ if (ret) {
+ dev_err(info->device, "cannot enable PCI device\n");
+ goto err_enable_device;
+ }
+
+ ret = pci_request_regions(dev, info->fix.id);
+ if (ret) {
+ dev_err(info->device, "error requesting regions\n");
+ goto err_request_regions;
+ }
+
+ info->screen_base = pci_ioremap_bar(dev, 0);
+ if (!info->screen_base) {
+ dev_err(info->device, "error remapping base\n");
+ ret = -ENOMEM;
+ goto err_ioremap_1;
+ }
+
+ par->regs = pci_ioremap_bar(dev, 1);
+ if (!par->regs) {
+ dev_err(info->device, "error remapping MMIO\n");
+ ret = -ENOMEM;
+ goto err_ioremap_2;
+ }
+
+ /* detect memory size */
+ if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1) = DRAM_ROW_1_SDRAM)
+ i740outb(par, XRX, DRAM_ROW_BNDRY_1);
+ else
+ i740outb(par, XRX, DRAM_ROW_BNDRY_0);
+ info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
+ /* detect memory type */
+ par->has_sgram = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);
+ par->has_sgram = !((par->has_sgram & DRAM_RAS_TIMING) ||
+ (par->has_sgram & DRAM_RAS_PRECHARGE));
+
+ printk(KERN_INFO "fb%d: Intel740 on %s, %ld KB %s\n", info->node,
+ pci_name(dev), info->screen_size >> 10,
+ par->has_sgram ? "SGRAM" : "SDRAM");
+
+ info->fix = i740fb_fix;
+ info->fix.mmio_start = pci_resource_start(dev, 1);
+ info->fix.mmio_len = pci_resource_len(dev, 1);
+ info->fix.smem_start = pci_resource_start(dev, 0);
+ info->fix.smem_len = info->screen_size;
+ info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
+
+ if (i740fb_setup_ddc_bus(info) = 0) {
+ par->ddc_registered = true;
+ edid = fb_ddc_read(&par->ddc_adapter);
+ if (edid) {
+ fb_edid_to_monspecs(edid, &info->monspecs);
+ kfree(edid);
+ if (!info->monspecs.modedb)
+ dev_err(info->device, "error getting mode database\n");
+ else {
+ const struct fb_videomode *m;
+
+ fb_videomode_to_modelist(info->monspecs.modedb,
+ info->monspecs.modedb_len,
+ &info->modelist);
+ m = fb_find_best_display(&info->monspecs, &info->modelist);
+ if (m) {
+ fb_videomode_to_var(&info->var, m);
+ /* fill all other info->var's fields */
+ if (i740fb_check_var(&info->var, info) = 0)
+ found = true;
+ }
+ }
+ }
+ }
+
+ if (!mode_option && !found)
+ mode_option = "640x480-8@60";
+
+ if (mode_option) {
+ ret = fb_find_mode(&info->var, info, mode_option,
+ info->monspecs.modedb, info->monspecs.modedb_len,
+ NULL, info->var.bits_per_pixel);
+ if (!ret || ret = 4) {
+ dev_err(info->device, "mode %s not found\n", mode_option);
+ ret = -EINVAL;
+ }
+ }
+
+ fb_destroy_modedb(info->monspecs.modedb);
+ info->monspecs.modedb = NULL;
+
+ /* maximize virtual vertical size for fast scrolling */
+ info->var.yres_virtual = info->fix.smem_len * 8 /
+ (info->var.bits_per_pixel * info->var.xres_virtual);
+
+ if (ret = -EINVAL)
+ goto err_find_mode;
+
+ ret = fb_alloc_cmap(&info->cmap, 256, 0);
+ if (ret) {
+ dev_err(info->device, "cannot allocate colormap\n");
+ goto err_alloc_cmap;
+ }
+
+ ret = register_framebuffer(info);
+ if (ret) {
+ dev_err(info->device, "error registering framebuffer\n");
+ goto err_reg_framebuffer;
+ }
+
+ printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
+ pci_set_drvdata(dev, info);
+#ifdef CONFIG_MTRR
+ if (mtrr) {
+ par->mtrr_reg = -1;
+ par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
+ }
+#endif
+ return 0;
+
+err_reg_framebuffer:
+ fb_dealloc_cmap(&info->cmap);
+err_alloc_cmap:
+err_find_mode:
+ if (par->ddc_registered)
+ i2c_del_adapter(&par->ddc_adapter);
+ pci_iounmap(dev, par->regs);
+err_ioremap_2:
+ pci_iounmap(dev, info->screen_base);
+err_ioremap_1:
+ pci_release_regions(dev);
+err_request_regions:
+/* pci_disable_device(dev); */
+err_enable_device:
+ framebuffer_release(info);
+ return ret;
+}
+
+static void __devexit i740fb_remove(struct pci_dev *dev)
+{
+ struct fb_info *info = pci_get_drvdata(dev);
+
+ if (info) {
+#ifdef CONFIG_MTRR
+ struct i740fb_par *par = info->par;
+
+ if (par->mtrr_reg >= 0) {
+ mtrr_del(par->mtrr_reg, 0, 0);
+ par->mtrr_reg = -1;
+ }
+#endif
+ unregister_framebuffer(info);
+ fb_dealloc_cmap(&info->cmap);
+ if (par->ddc_registered)
+ i2c_del_adapter(&par->ddc_adapter);
+ pci_iounmap(dev, par->regs);
+ pci_iounmap(dev, info->screen_base);
+ pci_release_regions(dev);
+/* pci_disable_device(dev); */
+ pci_set_drvdata(dev, NULL);
+ framebuffer_release(info);
+ }
+}
+
+#ifdef CONFIG_PM
+static int i740fb_suspend(struct pci_dev *dev, pm_message_t state)
+{
+ struct fb_info *info = pci_get_drvdata(dev);
+ struct i740fb_par *par = info->par;
+
+ /* don't disable console during hibernation and wakeup from it */
+ if (state.event = PM_EVENT_FREEZE || state.event = PM_EVENT_PRETHAW)
+ return 0;
+
+ console_lock();
+ mutex_lock(&(par->open_lock));
+
+ /* do nothing if framebuffer is not active */
+ if (par->ref_count = 0) {
+ mutex_unlock(&(par->open_lock));
+ console_unlock();
+ return 0;
+ }
+
+ fb_set_suspend(info, 1);
+
+ pci_save_state(dev);
+ pci_disable_device(dev);
+ pci_set_power_state(dev, pci_choose_state(dev, state));
+
+ mutex_unlock(&(par->open_lock));
+ console_unlock();
+
+ return 0;
+}
+
+static int i740fb_resume(struct pci_dev *dev)
+{
+ struct fb_info *info = pci_get_drvdata(dev);
+ struct i740fb_par *par = info->par;
+
+ console_lock();
+ mutex_lock(&(par->open_lock));
+
+ if (par->ref_count = 0)
+ goto fail;
+
+ pci_set_power_state(dev, PCI_D0);
+ pci_restore_state(dev);
+ if (pci_enable_device(dev))
+ goto fail;
+
+ i740fb_set_par(info);
+ fb_set_suspend(info, 0);
+
+fail:
+ mutex_unlock(&(par->open_lock));
+ console_unlock();
+ return 0;
+}
+#else
+#define i740fb_suspend NULL
+#define i740fb_resume NULL
+#endif /* CONFIG_PM */
+
+#define I740_ID_PCI 0x00d1
+#define I740_ID_AGP 0x7800
+
+static DEFINE_PCI_DEVICE_TABLE(i740fb_id_table) = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_PCI) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_AGP) },
+ { 0 }
+};
+MODULE_DEVICE_TABLE(pci, i740fb_id_table);
+
+static struct pci_driver i740fb_driver = {
+ .name = "i740fb",
+ .id_table = i740fb_id_table,
+ .probe = i740fb_probe,
+ .remove = __devexit_p(i740fb_remove),
+ .suspend = i740fb_suspend,
+ .resume = i740fb_resume,
+};
+
+#ifndef MODULE
+static int __init i740fb_setup(char *options)
+{
+ char *opt;
+
+ if (!options || !*options)
+ return 0;
+
+ while ((opt = strsep(&options, ",")) != NULL) {
+ if (!*opt)
+ continue;
+#ifdef CONFIG_MTRR
+ else if (!strncmp(opt, "mtrr:", 5))
+ mtrr = simple_strtoul(opt + 5, NULL, 0);
+#endif
+ else
+ mode_option = opt;
+ }
+
+ return 0;
+}
+#endif
+
+int __init i740fb_init(void)
+{
+#ifndef MODULE
+ char *option = NULL;
+
+ if (fb_get_options("i740fb", &option))
+ return -ENODEV;
+ i740fb_setup(option);
+#endif
+
+ return pci_register_driver(&i740fb_driver);
+}
+
+static void __exit i740fb_exit(void)
+{
+ pci_unregister_driver(&i740fb_driver);
+}
+
+module_init(i740fb_init);
+module_exit(i740fb_exit);
+
+MODULE_AUTHOR("(c) 2011 Ondrej Zary <linux@rainbow-software.org>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("fbdev driver for Intel740");
+
+module_param(mode_option, charp, 0444);
+MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
+
+#ifdef CONFIG_MTRR
+module_param(mtrr, int, 0444);
+MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
+#endif
--- /dev/null 2011-10-28 20:05:27.615214131 +0200
+++ linux-2.6.39-rc2/drivers/video/i740_reg.h 2011-08-14 23:47:48.000000000 +0200
@@ -0,0 +1,309 @@
+/**************************************************************************
+
+Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
+All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sub license, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+**************************************************************************/
+
+/*
+ * Authors:
+ * Kevin E. Martin <kevin@precisioninsight.com>
+ */
+
+/* I/O register offsets */
+#define SRX VGA_SEQ_I
+#define GRX VGA_GFX_I
+#define ARX VGA_ATT_IW
+#define XRX 0x3D6
+#define MRX 0x3D2
+
+/* VGA Color Palette Registers */
+#define DACMASK 0x3C6
+#define DACSTATE 0x3C7
+#define DACRX 0x3C7
+#define DACWX 0x3C8
+#define DACDATA 0x3C9
+
+/* CRT Controller Registers (CRX) */
+#define START_ADDR_HI 0x0C
+#define START_ADDR_LO 0x0D
+#define VERT_SYNC_END 0x11
+#define EXT_VERT_TOTAL 0x30
+#define EXT_VERT_DISPLAY 0x31
+#define EXT_VERT_SYNC_START 0x32
+#define EXT_VERT_BLANK_START 0x33
+#define EXT_HORIZ_TOTAL 0x35
+#define EXT_HORIZ_BLANK 0x39
+#define EXT_START_ADDR 0x40
+#define EXT_START_ADDR_ENABLE 0x80
+#define EXT_OFFSET 0x41
+#define EXT_START_ADDR_HI 0x42
+#define INTERLACE_CNTL 0x70
+#define INTERLACE_ENABLE 0x80
+#define INTERLACE_DISABLE 0x00
+
+/* Miscellaneous Output Register */
+#define MSR_R 0x3CC
+#define MSR_W 0x3C2
+#define IO_ADDR_SELECT 0x01
+
+#define MDA_BASE 0x3B0
+#define CGA_BASE 0x3D0
+
+/* System Configuration Extension Registers (XRX) */
+#define IO_CTNL 0x09
+#define EXTENDED_ATTR_CNTL 0x02
+#define EXTENDED_CRTC_CNTL 0x01
+
+#define ADDRESS_MAPPING 0x0A
+#define PACKED_MODE_ENABLE 0x04
+#define LINEAR_MODE_ENABLE 0x02
+#define PAGE_MAPPING_ENABLE 0x01
+
+#define BITBLT_CNTL 0x20
+#define COLEXP_MODE 0x30
+#define COLEXP_8BPP 0x00
+#define COLEXP_16BPP 0x10
+#define COLEXP_24BPP 0x20
+#define COLEXP_RESERVED 0x30
+#define CHIP_RESET 0x02
+#define BITBLT_STATUS 0x01
+
+#define DISPLAY_CNTL 0x40
+#define VGA_WRAP_MODE 0x02
+#define VGA_WRAP_AT_256KB 0x00
+#define VGA_NO_WRAP 0x02
+#define GUI_MODE 0x01
+#define STANDARD_VGA_MODE 0x00
+#define HIRES_MODE 0x01
+
+#define DRAM_ROW_TYPE 0x50
+#define DRAM_ROW_0 0x07
+#define DRAM_ROW_0_SDRAM 0x00
+#define DRAM_ROW_0_EMPTY 0x07
+#define DRAM_ROW_1 0x38
+#define DRAM_ROW_1_SDRAM 0x00
+#define DRAM_ROW_1_EMPTY 0x38
+#define DRAM_ROW_CNTL_LO 0x51
+#define DRAM_CAS_LATENCY 0x10
+#define DRAM_RAS_TIMING 0x08
+#define DRAM_RAS_PRECHARGE 0x04
+#define DRAM_ROW_CNTL_HI 0x52
+#define DRAM_EXT_CNTL 0x53
+#define DRAM_REFRESH_RATE 0x03
+#define DRAM_REFRESH_DISABLE 0x00
+#define DRAM_REFRESH_60HZ 0x01
+#define DRAM_REFRESH_FAST_TEST 0x02
+#define DRAM_REFRESH_RESERVED 0x03
+#define DRAM_TIMING 0x54
+#define DRAM_ROW_BNDRY_0 0x55
+#define DRAM_ROW_BNDRY_1 0x56
+
+#define DPMS_SYNC_SELECT 0x61
+#define VSYNC_CNTL 0x08
+#define VSYNC_ON 0x00
+#define VSYNC_OFF 0x08
+#define HSYNC_CNTL 0x02
+#define HSYNC_ON 0x00
+#define HSYNC_OFF 0x02
+
+#define PIXPIPE_CONFIG_0 0x80
+#define DAC_8_BIT 0x80
+#define DAC_6_BIT 0x00
+#define HW_CURSOR_ENABLE 0x10
+#define EXTENDED_PALETTE 0x01
+
+#define PIXPIPE_CONFIG_1 0x81
+#define DISPLAY_COLOR_MODE 0x0F
+#define DISPLAY_VGA_MODE 0x00
+#define DISPLAY_8BPP_MODE 0x02
+#define DISPLAY_15BPP_MODE 0x04
+#define DISPLAY_16BPP_MODE 0x05
+#define DISPLAY_24BPP_MODE 0x06
+#define DISPLAY_32BPP_MODE 0x07
+
+#define PIXPIPE_CONFIG_2 0x82
+#define DISPLAY_GAMMA_ENABLE 0x08
+#define DISPLAY_GAMMA_DISABLE 0x00
+#define OVERLAY_GAMMA_ENABLE 0x04
+#define OVERLAY_GAMMA_DISABLE 0x00
+
+#define CURSOR_CONTROL 0xA0
+#define CURSOR_ORIGIN_SCREEN 0x00
+#define CURSOR_ORIGIN_DISPLAY 0x10
+#define CURSOR_MODE 0x07
+#define CURSOR_MODE_DISABLE 0x00
+#define CURSOR_MODE_32_4C_AX 0x01
+#define CURSOR_MODE_128_2C 0x02
+#define CURSOR_MODE_128_1C 0x03
+#define CURSOR_MODE_64_3C 0x04
+#define CURSOR_MODE_64_4C_AX 0x05
+#define CURSOR_MODE_64_4C 0x06
+#define CURSOR_MODE_RESERVED 0x07
+#define CURSOR_BASEADDR_LO 0xA2
+#define CURSOR_BASEADDR_HI 0xA3
+#define CURSOR_X_LO 0xA4
+#define CURSOR_X_HI 0xA5
+#define CURSOR_X_POS 0x00
+#define CURSOR_X_NEG 0x80
+#define CURSOR_Y_LO 0xA6
+#define CURSOR_Y_HI 0xA7
+#define CURSOR_Y_POS 0x00
+#define CURSOR_Y_NEG 0x80
+
+#define VCLK2_VCO_M 0xC8
+#define VCLK2_VCO_N 0xC9
+#define VCLK2_VCO_MN_MSBS 0xCA
+#define VCO_N_MSBS 0x30
+#define VCO_M_MSBS 0x03
+#define VCLK2_VCO_DIV_SEL 0xCB
+#define POST_DIV_SELECT 0x70
+#define POST_DIV_1 0x00
+#define POST_DIV_2 0x10
+#define POST_DIV_4 0x20
+#define POST_DIV_8 0x30
+#define POST_DIV_16 0x40
+#define POST_DIV_32 0x50
+#define VCO_LOOP_DIV_BY_4M 0x00
+#define VCO_LOOP_DIV_BY_16M 0x04
+#define REF_CLK_DIV_BY_5 0x02
+#define REF_DIV_4 0x00
+#define REF_DIV_1 0x01
+
+#define PLL_CNTL 0xCE
+#define PLL_MEMCLK_SEL 0x03
+#define PLL_MEMCLK__66667KHZ 0x00
+#define PLL_MEMCLK__75000KHZ 0x01
+#define PLL_MEMCLK__88889KHZ 0x02
+#define PLL_MEMCLK_100000KHZ 0x03
+
+/* Multimedia Extension Registers (MRX) */
+#define ACQ_CNTL_1 0x02
+#define ACQ_CNTL_2 0x03
+#define FRAME_CAP_MODE 0x01
+#define CONT_CAP_MODE 0x00
+#define SINGLE_CAP_MODE 0x01
+#define ACQ_CNTL_3 0x04
+#define COL_KEY_CNTL_1 0x3C
+#define BLANK_DISP_OVERLAY 0x20
+
+/* FIFOs */
+#define LP_FIFO 0x1000
+#define HP_FIFO 0x2000
+#define INSTPNT 0x3040
+#define LP_FIFO_COUNT 0x3040
+#define HP_FIFO_COUNT 0x3041
+
+/* FIFO Commands */
+#define CLIENT 0xE0000000
+#define CLIENT_2D 0x60000000
+
+/* Command Parser Mode Register */
+#define COMPARS 0x3038
+#define TWO_D_INST_DISABLE 0x08
+#define THREE_D_INST_DISABLE 0x04
+#define STATE_VAR_UPDATE_DISABLE 0x02
+#define PAL_STIP_DISABLE 0x01
+
+/* Interrupt Control Registers */
+#define IER 0x3030
+#define IIR 0x3032
+#define IMR 0x3034
+#define ISR 0x3036
+#define VMIINTB_EVENT 0x2000
+#define GPIO4_INT 0x1000
+#define DISP_FLIP_EVENT 0x0800
+#define DVD_PORT_DMA 0x0400
+#define DISP_VBLANK 0x0200
+#define FIFO_EMPTY_DMA_DONE 0x0100
+#define INST_PARSER_ERROR 0x0080
+#define USER_DEFINED 0x0040
+#define BREAKPOINT 0x0020
+#define DISP_HORIZ_COUNT 0x0010
+#define DISP_VSYNC 0x0008
+#define CAPTURE_HORIZ_COUNT 0x0004
+#define CAPTURE_VSYNC 0x0002
+#define THREE_D_PIPE_FLUSHED 0x0001
+
+/* FIFO Watermark and Burst Length Control Register */
+#define FWATER_BLC 0x00006000
+#define LMI_BURST_LENGTH 0x7F000000
+#define LMI_FIFO_WATERMARK 0x003F0000
+#define AGP_BURST_LENGTH 0x00007F00
+#define AGP_FIFO_WATERMARK 0x0000003F
+
+/* BitBLT Registers */
+#define SRC_DST_PITCH 0x00040000
+#define DST_PITCH 0x1FFF0000
+#define SRC_PITCH 0x00001FFF
+#define COLEXP_BG_COLOR 0x00040004
+#define COLEXP_FG_COLOR 0x00040008
+#define MONO_SRC_CNTL 0x0004000C
+#define MONO_USE_COLEXP 0x00000000
+#define MONO_USE_SRCEXP 0x08000000
+#define MONO_DATA_ALIGN 0x07000000
+#define MONO_BIT_ALIGN 0x01000000
+#define MONO_BYTE_ALIGN 0x02000000
+#define MONO_WORD_ALIGN 0x03000000
+#define MONO_DWORD_ALIGN 0x04000000
+#define MONO_QWORD_ALIGN 0x05000000
+#define MONO_SRC_INIT_DSCRD 0x003F0000
+#define MONO_SRC_RIGHT_CLIP 0x00003F00
+#define MONO_SRC_LEFT_CLIP 0x0000003F
+#define BITBLT_CONTROL 0x00040010
+#define BLTR_STATUS 0x80000000
+#define DYN_DEPTH 0x03000000
+#define DYN_DEPTH_8BPP 0x00000000
+#define DYN_DEPTH_16BPP 0x01000000
+#define DYN_DEPTH_24BPP 0x02000000
+#define DYN_DEPTH_32BPP 0x03000000 /* Not implemented on the i740 */
+#define DYN_DEPTH_ENABLE 0x00800000
+#define PAT_VERT_ALIGN 0x00700000
+#define SOLID_PAT_SELECT 0x00080000
+#define PAT_IS_IN_COLOR 0x00000000
+#define PAT_IS_MONO 0x00040000
+#define MONO_PAT_TRANSP 0x00020000
+#define COLOR_TRANSP_ROP 0x00000000
+#define COLOR_TRANSP_DST 0x00008000
+#define COLOR_TRANSP_EQ 0x00000000
+#define COLOR_TRANSP_NOT_EQ 0x00010000
+#define COLOR_TRANSP_ENABLE 0x00004000
+#define MONO_SRC_TRANSP 0x00002000
+#define SRC_IS_IN_COLOR 0x00000000
+#define SRC_IS_MONO 0x00001000
+#define SRC_USE_SRC_ADDR 0x00000000
+#define SRC_USE_BLTDATA 0x00000400
+#define BLT_TOP_TO_BOT 0x00000000
+#define BLT_BOT_TO_TOP 0x00000200
+#define BLT_LEFT_TO_RIGHT 0x00000000
+#define BLT_RIGHT_TO_LEFT 0x00000100
+#define BLT_ROP 0x000000FF
+#define BLT_PAT_ADDR 0x00040014
+#define BLT_SRC_ADDR 0x00040018
+#define BLT_DST_ADDR 0x0004001C
+#define BLT_DST_H_W 0x00040020
+#define BLT_DST_HEIGHT 0x1FFF0000
+#define BLT_DST_WIDTH 0x00001FFF
+#define SRCEXP_BG_COLOR 0x00040024
+#define SRCEXP_FG_COLOR 0x00040028
+#define BLTDATA 0x00050000
--
Ondrej Zary
^ permalink raw reply
* Re: Recent viafb changes break OLPC DCON freeze
From: Daniel Drake @ 2011-11-18 16:09 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <CAMLZHHQHZL9zZMsQgvXBi6MoG9_TXWqPN5D19sqeKSjsoV3unA@mail.gmail.com>
On Thu, Nov 17, 2011 at 8:14 PM, Florian Tobias Schandinat
<FlorianSchandinat@gmx.de> wrote:
> As you mentioned it, I had a look at this driver. It looks like viafb does it
> (polarity) just the other way around than geode. So it might be wort a try to
> change in
>
> drivers/video/via/share.h:
> /* 1200x900@60 Sync Polarity (DCON) */
> #define M1200X900_R60_HSP NEGATIVE
> #define M1200X900_R60_VSP NEGATIVE
>
> to
>
> /* 1200x900@60 Sync Polarity (DCON) */
> #define M1200X900_R60_HSP POSITIVE
> #define M1200X900_R60_VSP POSITIVE
That fixes the problem - thanks! Let me know if you'd like me to make
a patch with that change (I can do so on Monday).
It may still be worth you looking at the diagnosis - in particular I
think I may have found something that may clean up some of the
uncertainty in commit 32fab7bc
Thanks
Daniel
^ permalink raw reply
* QVGA on a hardware which supports only >= VGA
From: Christian Gmeiner @ 2011-11-18 12:01 UTC (permalink / raw)
To: linux-fbdev
Hi all,
I am currently in the process to get some local patches into mainline
and/or fix my
problems the right way. At the moment I am stuck with this problem:
I am on a device (x86), which is Geode lx800 based and there is a
panel connected to
it. The problem is that two different screen resolutions are used. QVGA and VGA.
Should not sound like a problem, but the lx800 can only do VGA. So get
it working,
I need to pass the correct resolution via kernel cmd to the lxfb
driver and I am using
this patch (based on 2.6.36.4 kernel):
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
@@ -1050,6 +1050,7 @@ static long do_fb_ioctl(struct fb_info *info,
unsigned int cmd,
ret = copy_to_user(argp, &var, sizeof(var)) ? -EFAULT : 0;
break;
case FBIOPUT_VSCREENINFO:
+#if 0
if (copy_from_user(&var, argp, sizeof(var)))
return -EFAULT;
if (!lock_fb_info(info))
@@ -1062,6 +1063,8 @@ static long do_fb_ioctl(struct fb_info *info,
unsigned int cmd,
unlock_fb_info(info);
if (!ret && copy_to_user(argp, &var, sizeof(var)))
ret = -EFAULT;
+#endif
+ ret = 0;
break;
case FBIOGET_FSCREENINFO:
if (!lock_fb_info(info))
@@ -1086,6 +1089,7 @@ static long do_fb_ioctl(struct fb_info *info,
unsigned int cmd,
ret = fb_cmap_to_user(&cmap_from, &cmap);
break;
case FBIOPAN_DISPLAY:
+#if 0
if (copy_from_user(&var, argp, sizeof(var)))
return -EFAULT;
if (!lock_fb_info(info))
@@ -1096,6 +1100,8 @@ static long do_fb_ioctl(struct fb_info *info,
unsigned int cmd,
unlock_fb_info(info);
if (ret = 0 && copy_to_user(argp, &var, sizeof(var)))
return -EFAULT;
+#endif
+ ret = 0;
break;
case FBIO_CURSOR:
ret = -EINVAL;
I need to mention that I am using a custom BIOS and Linux based
bootloader (kexec) in the
boot process. At the moment I am looking into coreboot, but I wanted
to know how to
solve this "problem" the correct way.
To sum it up: I want to use a QVGA panel with a hardware that only
supports >= VGA.
Thanks
--
Christian Gmeiner, MSc
^ permalink raw reply
* [GIT PULL] OMAP DSS fixes for 3.2-rc
From: Tomi Valkeinen @ 2011-11-18 8:16 UTC (permalink / raw)
To: florianschandinat; +Cc: linux-fbdev, linux-omap mailing list
[-- Attachment #1: Type: text/plain, Size: 829 bytes --]
Hi Florian,
Here are a few OMAP display subsystem fixes for 3.2-rc.
One for the old omapfb, which was missing include module.h, and two for
the omapdss fixing issues related to HDMI.
Tomi
The following changes since commit cfcfc9eca2bcbd26a8e206baeb005b055dbf8e37:
Linux 3.2-rc2 (2011-11-15 15:02:59 -0200)
are available in the git repository at:
git://gitorious.org/linux-omap-dss2/linux.git for-3.2-rc
Tomi Valkeinen (3):
OMAPDSS: HDMI: fix returned HDMI pixel clock
OMAPFB: fix compilation warnings due to missing include
OMAPDSS: DISPC: skip scaling calculations when not scaling
drivers/video/omap/dispc.c | 1 +
drivers/video/omap2/dss/dispc.c | 11 +++++------
drivers/video/omap2/dss/hdmi.c | 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* [PATCH 6/6] Drivers: video: riva: riva_hw: fixed a brace coding style issue
From: Zac Storer @ 2011-11-18 4:50 UTC (permalink / raw)
To: adaplas; +Cc: linux-fbdev, linux-kernel, Zac Storer
Fixed a brace coding style issue.
Signed-off-by: Zac Storer <zac.3.14159@gmail.com>
---
drivers/video/riva/riva_hw.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c
index c4b8a6f..5cd1d71 100644
--- a/drivers/video/riva/riva_hw.c
+++ b/drivers/video/riva/riva_hw.c
@@ -1038,7 +1038,7 @@ static void nv10CalcArbitration
min_mclk_extra--;
}
} else {
- if (clwm > 1023){ /* Have some margin */
+ if (clwm > 1023) { /* Have some margin */
fifo->valid = 0;
found = 0;
if(min_mclk_extra = 0)
--
1.7.7.3
^ permalink raw reply related
* [PATCH 5/5] Drivers: video: riva: riva_hw: fixed a brace coding style issue
From: Zac Storer @ 2011-11-18 4:45 UTC (permalink / raw)
To: FlorianSchandinat; +Cc: linux-fbdev, linux-kernel, Zac Storer
Fixed a brace coding style issue.
Signed-off-by: Zac Storer <zac.3.14159@gmail.com>
---
drivers/video/riva/riva_hw.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c
index 78fdbf5..c4b8a6f 100644
--- a/drivers/video/riva/riva_hw.c
+++ b/drivers/video/riva/riva_hw.c
@@ -994,7 +994,7 @@ static void nv10CalcArbitration
clwm = clwm_mt;
*/
/* Finally, a heuristic check when width = 64 bits */
- if(width = 1){
+ if(width = 1) {
nvclk_fill = nvclk_freq * 8;
if(crtc_drain_rate * 100 >= nvclk_fill * 102)
clwm = 0xfff; /*Large number to fail */
--
1.7.7.3
^ permalink raw reply related
* [PATCH 4/4] Drivers: video: sbuslib: fixed a brace coding style issue
From: Zac Storer @ 2011-11-18 4:38 UTC (permalink / raw)
To: FlorianSchandinat; +Cc: linux-fbdev, linux-kernel, Zac Storer
Fixed a brace coding style issue.
Signed-off-by: Zac Storer <zac.3.14159@gmail.com>
---
drivers/video/sbuslib.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/video/sbuslib.c b/drivers/video/sbuslib.c
index 37d764a..3c1de98 100644
--- a/drivers/video/sbuslib.c
+++ b/drivers/video/sbuslib.c
@@ -76,7 +76,7 @@ int sbusfb_mmap_helper(struct sbus_mmap_map *map,
map_offset = (physbase + map[i].poff) & POFF_MASK;
break;
}
- if (!map_size){
+ if (!map_size) {
page += PAGE_SIZE;
continue;
}
--
1.7.7.3
^ permalink raw reply related
* [PATCH 3/3] Drivers: video: controlfb: fixed a brace coding style issue
From: Zac Storer @ 2011-11-18 4:34 UTC (permalink / raw)
To: FlorianSchandinat; +Cc: linux-fbdev, linux-kernel, Zac Storer
Fixed a brace coding style issue.
Signed-off-by: Zac Storer <zac.3.14159@gmail.com>
---
drivers/video/controlfb.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/video/controlfb.c b/drivers/video/controlfb.c
index 7b2c40a..0c189b3 100644
--- a/drivers/video/controlfb.c
+++ b/drivers/video/controlfb.c
@@ -420,7 +420,7 @@ static int __init init_control(struct fb_info_control *p)
/* Try to pick a video mode out of NVRAM if we have one. */
#ifdef CONFIG_NVRAM
- if (default_cmode = CMODE_NVRAM){
+ if (default_cmode = CMODE_NVRAM) {
cmode = nvram_read_byte(NV_CMODE);
if(cmode < CMODE_8 || cmode > CMODE_32)
cmode = CMODE_8;
--
1.7.7.3
^ permalink raw reply related
* Re: Recent viafb changes break OLPC DCON freeze
From: Florian Tobias Schandinat @ 2011-11-18 2:14 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <CAMLZHHQHZL9zZMsQgvXBi6MoG9_TXWqPN5D19sqeKSjsoV3unA@mail.gmail.com>
Hi Daniel,
thanks a lot for your debugging. I'm busy at the moment so I'll keep it short.
On 11/17/2011 04:24 PM, Daniel Drake wrote:
> A further data point on this issue: we once hit exactly the same thing
> on XO-1 (geode lxfb). A non-OLPC commit caused the v/h sync output
> polarity to change. The display still worked correctly, but the DCON
> freeze functionality caused garbage in exactly the same way as this
> viafb issue. This suggests that the display itself isn't too fussy
> about video signal parameters, but the DCON controller is picky and
> expects certain parameters. (see commit ad913da61aeb for the lxfb
> fix).
As you mentioned it, I had a look at this driver. It looks like viafb does it
(polarity) just the other way around than geode. So it might be wort a try to
change in
drivers/video/via/share.h:
/* 1200x900@60 Sync Polarity (DCON) */
#define M1200X900_R60_HSP NEGATIVE
#define M1200X900_R60_VSP NEGATIVE
to
/* 1200x900@60 Sync Polarity (DCON) */
#define M1200X900_R60_HSP POSITIVE
#define M1200X900_R60_VSP POSITIVE
> Any thoughts?
If the above works it's just that the thing was initially entered wrong and now
we hit it as we start setting the polarity for the correct devices, similar to
the issue with the refresh rate.
If it does not work I'll have a deeper look at it as soon as possible.
Best regards,
Florian Tobias Schandinat
^ permalink raw reply
* Re: [PATCH] fb: split out framebuffer initialization from allocation
From: Timur Tabi @ 2011-11-17 20:19 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <1321308088-6327-1-git-send-email-timur@freescale.com>
Timur Tabi wrote:
> Introduce functions framebuffer_init() and framebuffer_cleanup() to allow
> the initialization of a user-allocated fb_info object.
>
> framebuffer_alloc() allows for appending a private data structure when it
> allocates the fb_info object. However, a driver that registers multiple
> framebuffers for one device may also need another private data structure
> for the device itself. framebuffer_init() allows such drivers to store
> the fb_info objects in the device-specific private data structure,
> thereby simplifying memory allocation.
>
> Signed-off-by: Timur Tabi <timur@freescale.com>
Florian,
Any comments on this patch? If you're okay with the change, I want to take advantage of it in my framebuffer driver.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* [PATCH] ARM: pxafb: fix overwriting of pixel clock and output enable polarity
From: Marc Kleine-Budde @ 2011-11-17 16:47 UTC (permalink / raw)
To: linux-fbdev
When loading the pxafb driver as a module it's possible to overwrite the
platform data via module parameters. When overwriting the pixel clock or
output enable polarity the parse_opt() function modifies the lccr3 member
of the platform data struct. Later on in pxafb_decode_mach_info() lccr3
is only evaluated if lcd_conn lcd type is not used.
This patch fixes the problem by setting pixel clock and output enable
polarity in inf->lcd_conn, too (which is handled the correct way in
pxafb_decode_mach_info()).
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
drivers/video/pxafb.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 0f4e8c9..119c0a1 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -1979,17 +1979,21 @@ static int __devinit parse_opt(struct device *dev, char *this_opt)
if (simple_strtoul(this_opt+9, NULL, 0) = 0) {
sprintf(s, "output enable: active low\n");
inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
+ inf->lcd_conn |= LCD_BIAS_ACTIVE_LOW;
} else {
sprintf(s, "output enable: active high\n");
inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
+ inf->lcd_conn &= ~LCD_BIAS_ACTIVE_LOW;
}
} else if (!strncmp(this_opt, "pixclockpol:", 12)) {
if (simple_strtoul(this_opt+12, NULL, 0) = 0) {
sprintf(s, "pixel clock polarity: falling edge\n");
inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
+ inf->lcd_conn |= LCD_PCLK_EDGE_FALL;
} else {
sprintf(s, "pixel clock polarity: rising edge\n");
inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
+ inf->lcd_conn &= ~LCD_PCLK_EDGE_FALL;
}
} else if (!strncmp(this_opt, "color", 5)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
--
1.7.4.1
^ permalink raw reply related
* Recent viafb changes break OLPC DCON freeze
From: Daniel Drake @ 2011-11-17 16:24 UTC (permalink / raw)
To: linux-fbdev
Hi,
The OLPC XO-1.5 has a display controller (dcon) which is able to drive
the display while the video device is powered off (e.g. while the
system is in suspend). It works on demand, (approximately) by grabbing
the latest displayed picture (at the hardware level), storing it in
dedicated DCON RAM, and continually reproducing it on the screen. This
is known as "DCON freeze" and can also be triggered while the video
device is still running by executing:
echo 1 > /sys/devices/platform/dcon/freeze
(enabled by CONFIG_FB_OLPC_DCON_1_5)
Unfortunately this has broken in recent kernels due to viafb changes:
when going into "DCON freeze", the DCON fails to capture the display
contents and instead displays garbage. I am testing this on viafb
outside of X.
There are some complications in debugging this and pinpointing a
single responsible commit.
Kernels v2.6.38 and previous work fine. However, in such kernels, OLPC
included an out-of-tree DCON driver. 2.6.38 includes a DCON driver (in
staging) but it was not usable at this point.
v2.6.39 has a functional DCON driver, but viafb in this kernel is
unusable on XO-1.5 due to an unrelated bug which only got fixed for
3.0:
http://www.spinics.net/lists/linux-fbdev/msg03132.html
v3.0 and onwards reproduces the failure.
To debug this, I took the approach of starting with 2.6.38, fixing the
DCON driver in that old kernel, then going through the viafb changes
until the point of breakage was found. This can be done as follows:
git reset --hard v2.6.38
First, fix the DCON driver:
git cherry-pick a90dcd4f7dfc3e664e7d08790a8b39d052e21a2e
git cherry-pick e107e6ebdda9b56be21951a7c58c2fa90d6e685b
git cherry-pick fe2d5b43807ebb38e0e8c7b269ff08fcd4011726
git cherry-pick 8d2d3dd1b4589299ec17b15130fbadfc69996df4
git cherry-pick bb4103544e455e11d9a4379326406a60429b9888
git cherry-pick bada46e5ab10b09b0f86e8b8ede009e759a16adf
git cherry-pick 56463de05a56b80b43d21a442cf2a6e0037762e8
git cherry-pick 9ed62423033d167765a2c6385064acbeeadb2b14
git cherry-pick feaa98b2a5e452d95624d3f217cf1aab9cd25db0
git cherry-pick 45bfe97276856b866dd73fdadb65fb928c0c9bc1
git cherry-pick 31a3da4146c120e87b8d42d033760fe49704a233
git cherry-pick 8f2fb16a9cd015072b3da9038084930287e11985
git cherry-pick 097cd83a4c312e1ae0d9c14526f846666cab4f3a
git cherry-pick bbe963f1b98c90980e33086d726f0963e286d1b4
git cherry-pick 309ef2a25e8d3d5962bb0824c58ea39c12c166ef
git cherry-pick c59eef17f1cc21a984cf077ad45a8355781881b6
git cherry-pick b07b846c333708ce2b95b5cd2a86f51a74331d02
git cherry-pick 6a3a81e7ca9b1ddaaf8d644b4102aff0fe2a7c40
git cherry-pick bed4ab7781e8600a7ebf4378a1b3f26d31517f57
The dcon functionality can now be tested (it works).
Then we can apply all of the viafb changes between 2.6.38 and 2.6.39,
one by one until the commit prior to the one that completely broke
XO-1.5 video:
git cherry-pick a625e305edd8e3ac08888a9b52981205b68cdb0e
git cherry-pick b65d6040e3a7cd75d9287f7ddfd115e85fde4b44
git cherry-pick 23e5abd5555b86fd56af6383e7a832b0cf2a2d95
git cherry-pick dbf85f2326dbb070256ff153853b00f70c27717a
git cherry-pick c8350be26237e2b850b9611dbe55304ad6ebc6c7
git cherry-pick d90108765b64e39e88e59f51d05ac652f0e53fea
git cherry-pick bf5ea02d9058a97a0bc2da9ca04ae4b34989407a
git cherry-pick f5b1c4b3b6d407ec5a9d93ca12738c4c7911000c
git cherry-pick 97597a39778eefb628eb7734a18f32c7880ad0e0
At this point, the dcon functionality is still working.
Now we apply the commit that broke XO-1.5 video display:
git cherry-pick fd3cc69848b7e1873e5f12bbcdd57
[dcon-test3 c8f0551] viafb: remove duplicated clock storage
Author: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
5 files changed, 133 insertions(+), 212 deletions(-)
2b20277ecf3
As expected, the system now boots without working display. So we jump
ahead and grab the fix for that from v3.0:
git cherry-pick b4ce6a285b65be4fb858728b3bbe9011242b769f
[dcon-test3 158fa27] viafb: fix OLPC DCON refresh rate
Author: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
2 files changed, 7 insertions(+), 3 deletions(-)
Regular viafb operation and DCON freeze both work fine at this point.
However, the commit that follows the "fix OLPC DCON refresh rate" is
titled "fix OLPC XO 1.5 device connection" and the message suggests
that it is essential for operation. This doesn't seem to be completely
true - things are working fine with this tree without that patch. And
if I apply it:
git cherry-pick 32fab7bcc79ee0b97277627f456c94202858d851
[dcon-test3 3d690a2] viafb: fix OLPC XO 1.5 device connection
Author: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
1 files changed, 5 insertions(+), 0 deletions(-)
Now the DCON freeze problem appears. So commit 32fab7bcc seems to be
in some way responsible or related to this issue. (However, I have
applied it 'out of context' from the original history).
If I revert this commit from linus master, the system boots with
bad/unreadable display. So in linus master this patch is needed for
the display to come up properly (as the description suggests).
Taking another debugging approach: I start at 2.6.39 (which has
working DCON driver) and apply the OLPC display fix:
git reset --hard v2.6.39
git cherry-pick b4ce6a285b65be4fb858728b3bbe9011242b769f
[dcon-test3 8f8b430] viafb: fix OLPC DCON refresh rate
Author: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
2 files changed, 7 insertions(+), 3 deletions(-)
Regular operation and DCON freeze both work fine at this point.
Now I take the first post-2.6.39 viafb commit:
git cherry-pick 0f8132b7431e241c29e61ac14f22549a6fca9632
[dcon-test3 b66cc33] viafb: move initialization code
Author: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
1 files changed, 7 insertions(+), 5 deletions(-)
Regular operation and DCON freeze continue to work fine.
git cherry-pick 486d4c08dd2eb29b26b4a27f8056155a7a639861
[dcon-test3 e8cfb95] viafb: no need to write CRTC values twice
Author: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
1 files changed, 0 insertions(+), 3 deletions(-)
Now the system boots with bad/unreadable video, so I take an estimated
guess at how to fix it:
git cherry-pick 32fab7bcc79ee0b97277627f456c94202858d851
[dcon-test3 3d690a2] viafb: fix OLPC XO 1.5 device connection
Author: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
1 files changed, 5 insertions(+), 0 deletions(-)
Now the system boots with a readable display, but the DCON bug now
appears. So 486d4c08d also seems to be responsible or related to the
DCON issue in question.
I next tried to revert (only) 486d4c08d from linus master, but this
patch does not revert cleanly:
drivers/video/via/hw.c: In function 'hw_init':
drivers/video/via/hw.c:1827:25: error: 'crt_timing' undeclared (first
use in this function)
drivers/video/via/hw.c:1827:25: note: each undeclared identifier is
reported only once for each function it appears in
drivers/video/via/hw.c:1827:37: error: 'vmode_tbl' undeclared (first
use in this function)
drivers/video/via/hw.c:1827:48: error: 'video_bpp' undeclared (first
use in this function)
drivers/video/via/hw.c:1827:2: error: too many arguments to function
'viafb_fill_crtc_timing'
drivers/video/via/hw.c:1489:6: note: declared here
So here is where I am a bit stuck.
My suspicion is that 486d4c08d is needed (for some reason), and in its
presence, I suspect that 32fab7bc is not needed, and that DCON freeze
will then work under this configuration.
A further data point on this issue: we once hit exactly the same thing
on XO-1 (geode lxfb). A non-OLPC commit caused the v/h sync output
polarity to change. The display still worked correctly, but the DCON
freeze functionality caused garbage in exactly the same way as this
viafb issue. This suggests that the display itself isn't too fussy
about video signal parameters, but the DCON controller is picky and
expects certain parameters. (see commit ad913da61aeb for the lxfb
fix).
Any thoughts?
Thanks,
Daniel
^ permalink raw reply
* Re: [PATCH 2/4] omap_dss: add FocalTech ETM070003DH6 display support
From: Igor Grinberg @ 2011-11-17 6:52 UTC (permalink / raw)
To: Ilya Yanok
Cc: linux-omap, wd, dzu, sasha_d, Tomi Valkeinen,
linux-fbdev@vger.kernel.org
In-Reply-To: <4EC45535.9060708@emcraft.com>
Hi Ilya,
You should have CC'd Tomi and linux-fbdev - done now.
On 11/17/11 02:28, Ilya Yanok wrote:
> Hi guys,
>
> what about this patch? Can it be applied? It's pretty independent from
> other ones.
>
> Regards, Ilya.
>
> On 09.11.2011 04:12, Ilya Yanok wrote:
>> Add data for the FocalTech ETM070003DH6 display to the generic_dpi_panel
>> display driver.
>>
>> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
>> ---
>> drivers/video/omap2/displays/panel-generic-dpi.c | 24 ++++++++++++++++++++++
>> 1 files changed, 24 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/video/omap2/displays/panel-generic-dpi.c b/drivers/video/omap2/displays/panel-generic-dpi.c
>> index 519c47d..42bfe47 100644
>> --- a/drivers/video/omap2/displays/panel-generic-dpi.c
>> +++ b/drivers/video/omap2/displays/panel-generic-dpi.c
>> @@ -297,6 +297,30 @@ static struct panel_config generic_dpi_panels[] = {
>>
>> .name = "apollon",
>> },
>> + /* FocalTech ETM070003DH6 */
>> + {
>> + {
>> + .x_res = 800,
>> + .y_res = 480,
>> +
>> + .pixel_clock = 28000,
>> +
>> + .hsw = 48,
>> + .hfp = 40,
>> + .hbp = 40,
>> +
>> + .vsw = 3,
>> + .vfp = 13,
>> + .vbp = 29,
>> + },
>> + .acbi = 0x0,
>> + .acb = 0x28,
>> + .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
>> + OMAP_DSS_LCD_IHS,
>> + .power_on_delay = 50,
>> + .power_off_delay = 100,
>> + .name = "focaltech_etm070003dh6",
>> + },
>> };
>>
>> struct panel_drv_data {
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Regards,
Igor.
^ permalink raw reply
* [PATCH v2] video: support MIPI-DSI controller driver
From: Kyungmin Park @ 2011-11-16 0:55 UTC (permalink / raw)
To: linux-arm-kernel
From: Donghwa Lee <dh09.lee@samsung.com>
Samsung S5PC210 and EXYNOS SoC platform has MIPI-DSI controller and MIPI-DSI
based LCD Panel could be used with it. This patch supports MIPI-DSI driver
based Samsung SoC chip.
LCD panel driver based MIPI-DSI should be registered to MIPI-DSI driver at
machine code and LCD panel driver specific function registered to mipi_dsim_ddi
structure at lcd panel init function called system init.
In the MIPI-DSI driver, find lcd panel driver by using registered
lcd panel name, and then initialize lcd panel driver.
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Changes since v1:
- /plat/regs-dsim.h moves to /driver/video/s5p_mipi_dsi_regs.h,
- /plat/mipi_dsim.h moves to /linux/mipi_dsim.h
---
drivers/video/Kconfig | 7 +
drivers/video/Makefile | 2 +
drivers/video/s5p_mipi_dsi.c | 601 +++++++++++++++++++++
drivers/video/s5p_mipi_dsi_common.c | 931 +++++++++++++++++++++++++++++++++
drivers/video/s5p_mipi_dsi_common.h | 48 ++
drivers/video/s5p_mipi_dsi_lowlevel.c | 608 +++++++++++++++++++++
drivers/video/s5p_mipi_dsi_lowlevel.h | 108 ++++
drivers/video/s5p_mipi_dsi_regs.h | 153 ++++++
include/linux/mipi_dsim.h | 362 +++++++++++++
9 files changed, 2820 insertions(+), 0 deletions(-)
create mode 100644 drivers/video/s5p_mipi_dsi.c
create mode 100644 drivers/video/s5p_mipi_dsi_common.c
create mode 100644 drivers/video/s5p_mipi_dsi_common.h
create mode 100644 drivers/video/s5p_mipi_dsi_lowlevel.c
create mode 100644 drivers/video/s5p_mipi_dsi_lowlevel.h
create mode 100644 drivers/video/s5p_mipi_dsi_regs.h
create mode 100644 include/linux/mipi_dsim.h
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d83e967..879177b 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2082,6 +2082,13 @@ config FB_S3C2410_DEBUG
Turn on debugging messages. Note that you can set/unset at run time
through sysfs
+config S5P_MIPI_DSI
+ tristate "Samsung SoC MIPI-DSI support."
+ depends on FB_S3C && (ARCH_S5PV210 || ARCH_S5PV310 || ARCH_EXYNOS)
+ default n
+ help
+ This enables support for MIPI-DSI device.
+
config FB_NUC900
bool "NUC900 LCD framebuffer support"
depends on FB && ARCH_W90X900
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9b9d8ff..29eb7c9 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -120,6 +120,8 @@ obj-$(CONFIG_FB_SH7760) += sh7760fb.o
obj-$(CONFIG_FB_IMX) += imxfb.o
obj-$(CONFIG_FB_S3C) += s3c-fb.o
obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
+obj-$(CONFIG_S5P_MIPI_DSI) += s5p_mipi_dsi.o s5p_mipi_dsi_common.o \
+ s5p_mipi_dsi_lowlevel.o
obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o
obj-$(CONFIG_FB_COBALT) += cobalt_lcdfb.o
obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/
diff --git a/drivers/video/s5p_mipi_dsi.c b/drivers/video/s5p_mipi_dsi.c
new file mode 100644
index 0000000..09a4af8
--- /dev/null
+++ b/drivers/video/s5p_mipi_dsi.c
@@ -0,0 +1,601 @@
+/* linux/drivers/video/s5p_mipi_dsi.c
+ *
+ * Samsung SoC MIPI-DSIM driver.
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * InKi Dae, <inki.dae@samsung.com>
+ * Donghwa Lee, <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/wait.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/fb.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/memory.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kthread.h>
+#include <linux/notifier.h>
+#include <linux/mipi_dsim.h>
+
+#include <plat/fb.h>
+#include <linux/mipi_dsim.h>
+
+#include "s5p_mipi_dsi_common.h"
+#include "s5p_mipi_dsi_lowlevel.h"
+
+#define master_to_driver(a) (a->dsim_lcd_drv)
+#define master_to_device(a) (a->dsim_lcd_dev)
+
+struct mipi_dsim_ddi {
+ int bus_id;
+ struct list_head list;
+ struct mipi_dsim_lcd_device *dsim_lcd_dev;
+ struct mipi_dsim_lcd_driver *dsim_lcd_drv;
+};
+
+static LIST_HEAD(dsim_ddi_list);
+
+static DEFINE_MUTEX(mipi_dsim_lock);
+
+static struct s5p_platform_mipi_dsim *to_dsim_plat(struct platform_device *pdev)
+{
+ return (struct s5p_platform_mipi_dsim *)pdev->dev.platform_data;
+}
+
+/* update all register settings to MIPI DSI controller. */
+static void s5p_mipi_update_cfg(struct mipi_dsim_device *dsim)
+{
+ /*
+ * data from Display controller(FIMD) is not transferred in video mode
+ * but in case of command mode, all settings is not updated to
+ * registers.
+ */
+ s5p_mipi_dsi_stand_by(dsim, 0);
+
+ s5p_mipi_dsi_init_dsim(dsim);
+ s5p_mipi_dsi_init_link(dsim);
+
+ s5p_mipi_dsi_set_hs_enable(dsim);
+
+ /* set display timing. */
+ s5p_mipi_dsi_set_display_mode(dsim, dsim->dsim_config);
+
+ /*
+ * data from Display controller(FIMD) is transferred in video mode
+ * but in case of command mode, all settigs is updated to registers.
+ */
+ s5p_mipi_dsi_stand_by(dsim, 1);
+
+}
+
+static int s5p_mipi_dsi_early_blank_mode(struct mipi_dsim_device *dsim,
+ int power)
+{
+ struct platform_device *pdev = to_platform_device(dsim->dev);
+ struct mipi_dsim_lcd_driver *client_drv = master_to_driver(dsim);
+ struct mipi_dsim_lcd_device *client_dev = master_to_device(dsim);
+
+ switch (power) {
+ case FB_BLANK_POWERDOWN:
+ if (client_drv && client_drv->suspend)
+ client_drv->suspend(client_dev);
+
+ clk_disable(dsim->clock);
+
+ if (dsim->pd->mipi_power)
+ dsim->pd->mipi_power(pdev, 0);
+
+ atomic_set(&dsim->power_t, 0);
+
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int s5p_mipi_dsi_blank_mode(struct mipi_dsim_device *dsim, int power)
+{
+ struct platform_device *pdev = to_platform_device(dsim->dev);
+ struct mipi_dsim_lcd_driver *client_drv = master_to_driver(dsim);
+ struct mipi_dsim_lcd_device *client_dev = master_to_device(dsim);
+
+ switch (power) {
+ case FB_BLANK_UNBLANK:
+ /* lcd panel power on. */
+ if (client_drv && client_drv->power_on)
+ client_drv->power_on(client_dev);
+
+ if (dsim->pd->mipi_power)
+ dsim->pd->mipi_power(pdev, 1);
+
+ /* enable MIPI-DSI PHY. */
+ if (dsim->pd->phy_enable)
+ dsim->pd->phy_enable(pdev, true);
+
+ clk_enable(dsim->clock);
+
+ s5p_mipi_update_cfg(dsim);
+
+ /* set lcd panel sequence commands. */
+ if (client_drv && client_drv->set_sequence)
+ client_drv->set_sequence(client_dev);
+
+ atomic_set(&dsim->power_t, 1);
+
+ break;
+ case FB_BLANK_NORMAL:
+ /* TODO. */
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+int s5p_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev)
+{
+ struct mipi_dsim_ddi *dsim_ddi;
+
+ if (!lcd_dev) {
+ printk(KERN_ERR "mipi_dsim_lcd_device is NULL.\n");
+ return -EFAULT;
+ }
+
+ if (!lcd_dev->name) {
+ printk(KERN_ERR "dsim_lcd_device name is NULL.\n");
+ return -EFAULT;
+ }
+
+ dsim_ddi = kzalloc(sizeof(struct mipi_dsim_ddi), GFP_KERNEL);
+ if (!dsim_ddi) {
+ printk(KERN_ERR "failed to allocate dsim_ddi object.\n");
+ return -EFAULT;
+ }
+
+ dsim_ddi->dsim_lcd_dev = lcd_dev;
+
+ mutex_lock(&mipi_dsim_lock);
+ list_add_tail(&dsim_ddi->list, &dsim_ddi_list);
+ mutex_unlock(&mipi_dsim_lock);
+
+ return 0;
+}
+
+struct mipi_dsim_ddi
+ *s5p_mipi_dsi_find_lcd_device(struct mipi_dsim_lcd_driver *lcd_drv)
+{
+ struct mipi_dsim_ddi *dsim_ddi;
+ struct mipi_dsim_lcd_device *lcd_dev;
+
+ mutex_lock(&mipi_dsim_lock);
+
+ list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) {
+ if (!dsim_ddi)
+ goto out;
+
+ lcd_dev = dsim_ddi->dsim_lcd_dev;
+ if (!lcd_dev)
+ continue;
+
+ if (lcd_drv->id >= 0) {
+ if ((strcmp(lcd_drv->name, lcd_dev->name)) = 0 &&
+ lcd_drv->id = lcd_dev->id) {
+ /**
+ * bus_id would be used to identify
+ * connected bus.
+ */
+ dsim_ddi->bus_id = lcd_dev->bus_id;
+ mutex_unlock(&mipi_dsim_lock);
+
+ return dsim_ddi;
+ }
+ } else {
+ if ((strcmp(lcd_drv->name, lcd_dev->name)) = 0) {
+ /**
+ * bus_id would be used to identify
+ * connected bus.
+ */
+ dsim_ddi->bus_id = lcd_dev->bus_id;
+ mutex_unlock(&mipi_dsim_lock);
+
+ return dsim_ddi;
+ }
+ }
+
+ kfree(dsim_ddi);
+ list_del(&dsim_ddi->list);
+ }
+
+out:
+ mutex_unlock(&mipi_dsim_lock);
+
+ return NULL;
+}
+
+int s5p_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver *lcd_drv)
+{
+ struct mipi_dsim_ddi *dsim_ddi;
+
+ if (!lcd_drv) {
+ printk(KERN_ERR "mipi_dsim_lcd_driver is NULL.\n");
+ return -EFAULT;
+ }
+
+ if (!lcd_drv->name) {
+ printk(KERN_ERR "dsim_lcd_driver name is NULL.\n");
+ return -EFAULT;
+ }
+
+ dsim_ddi = s5p_mipi_dsi_find_lcd_device(lcd_drv);
+ if (!dsim_ddi) {
+ printk(KERN_ERR "mipi_dsim_ddi object not found.\n");
+ return -EFAULT;
+ }
+
+ dsim_ddi->dsim_lcd_drv = lcd_drv;
+
+ printk(KERN_INFO "registered panel driver(%s) to mipi-dsi driver.\n",
+ lcd_drv->name);
+
+ return 0;
+
+}
+
+struct mipi_dsim_ddi
+ *s5p_mipi_dsi_bind_lcd_ddi(struct mipi_dsim_device *dsim,
+ const char *name)
+{
+ struct mipi_dsim_ddi *dsim_ddi;
+ struct mipi_dsim_lcd_driver *lcd_drv;
+ struct mipi_dsim_lcd_device *lcd_dev;
+ int ret;
+
+ mutex_lock(&dsim->lock);
+
+ list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) {
+ lcd_drv = dsim_ddi->dsim_lcd_drv;
+ lcd_dev = dsim_ddi->dsim_lcd_dev;
+ if (!lcd_drv || !lcd_dev ||
+ (dsim->id != dsim_ddi->bus_id))
+ continue;
+
+ dev_dbg(dsim->dev, "lcd_drv->id = %d, lcd_dev->id = %d\n",
+ lcd_drv->id, lcd_dev->id);
+ dev_dbg(dsim->dev, "lcd_dev->bus_id = %d, dsim->id = %d\n",
+ lcd_dev->bus_id, dsim->id);
+
+ if ((strcmp(lcd_drv->name, name) = 0)) {
+ lcd_dev->master = dsim;
+
+ lcd_dev->dev.parent = dsim->dev;
+ dev_set_name(&lcd_dev->dev, "%s", lcd_drv->name);
+
+ ret = device_register(&lcd_dev->dev);
+ if (ret < 0) {
+ dev_err(dsim->dev,
+ "can't register %s, status %d\n",
+ dev_name(&lcd_dev->dev), ret);
+ mutex_unlock(&dsim->lock);
+
+ return NULL;
+ }
+
+ dsim->dsim_lcd_dev = lcd_dev;
+ dsim->dsim_lcd_drv = lcd_drv;
+
+ mutex_unlock(&dsim->lock);
+
+ return dsim_ddi;
+ }
+ }
+
+ mutex_unlock(&dsim->lock);
+
+ return NULL;
+}
+
+/* define MIPI-DSI Master operations. */
+static struct mipi_dsim_master_ops master_ops = {
+ .cmd_read = s5p_mipi_dsi_rd_data,
+ .cmd_write = s5p_mipi_dsi_wr_data,
+ .get_dsim_frame_done = s5p_mipi_dsi_get_frame_done_status,
+ .clear_dsim_frame_done = s5p_mipi_dsi_clear_frame_done,
+ .set_early_blank_mode = s5p_mipi_dsi_early_blank_mode,
+ .set_blank_mode = s5p_mipi_dsi_blank_mode,
+};
+
+static int s5p_mipi_dsi_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct mipi_dsim_device *dsim;
+ struct mipi_dsim_config *dsim_config;
+ struct mipi_dsim_platform_data *dsim_pd;
+ struct mipi_dsim_ddi *dsim_ddi;
+ int ret = -EINVAL;
+
+ dsim = kzalloc(sizeof(struct mipi_dsim_device), GFP_KERNEL);
+ if (!dsim) {
+ dev_err(&pdev->dev, "failed to allocate dsim object.\n");
+ return -EFAULT;
+ }
+
+ dsim->pd = to_dsim_plat(pdev);
+ dsim->dev = &pdev->dev;
+ dsim->id = pdev->id;
+
+ /* get mipi_dsim_platform_data. */
+ dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;
+ if (dsim_pd = NULL) {
+ dev_err(&pdev->dev, "failed to get platform data for dsim.\n");
+ return -EFAULT;
+ }
+ /* get mipi_dsim_config. */
+ dsim_config = dsim_pd->dsim_config;
+ if (dsim_config = NULL) {
+ dev_err(&pdev->dev, "failed to get dsim config data.\n");
+ return -EFAULT;
+ }
+
+ dsim->dsim_config = dsim_config;
+ dsim->master_ops = &master_ops;
+
+ dsim->clock = clk_get(&pdev->dev, "dsim0");
+ if (IS_ERR(dsim->clock)) {
+ dev_err(&pdev->dev, "failed to get dsim clock source\n");
+ goto err_clock_get;
+ }
+
+ clk_enable(dsim->clock);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "failed to get io memory region\n");
+ goto err_platform_get;
+ }
+
+ dsim->res = request_mem_region(res->start, resource_size(res),
+ dev_name(&pdev->dev));
+ if (!dsim->res) {
+ dev_err(&pdev->dev, "failed to request io memory region\n");
+ ret = -ENOMEM;
+ goto err_mem_region;
+ }
+
+ dsim->reg_base = ioremap(res->start, resource_size(res));
+ if (!dsim->reg_base) {
+ dev_err(&pdev->dev, "failed to remap io region\n");
+ ret = -EFAULT;
+ goto err_ioremap;
+ }
+
+ mutex_init(&dsim->lock);
+
+ /* bind lcd ddi matched with panel name. */
+ dsim_ddi = s5p_mipi_dsi_bind_lcd_ddi(dsim, dsim_pd->lcd_panel_name);
+ if (!dsim_ddi) {
+ dev_err(&pdev->dev, "mipi_dsim_ddi object not found.\n");
+ goto err_bind;
+ }
+
+ dsim->irq = platform_get_irq(pdev, 0);
+ if (dsim->irq < 0) {
+ dev_err(&pdev->dev, "failed to request dsim irq resource\n");
+ ret = -EINVAL;
+ goto err_platform_get_irq;
+ }
+
+ ret = request_irq(dsim->irq, s5p_mipi_dsi_interrupt_handler,
+ IRQF_SHARED, pdev->name, dsim);
+ if (ret != 0) {
+ dev_err(&pdev->dev, "failed to request dsim irq\n");
+ ret = -EINVAL;
+ goto err_bind;
+ }
+ init_completion(&dsim_rd_comp);
+
+ /* enable interrupt */
+ s5p_mipi_dsi_init_interrupt(dsim);
+
+ /* initialize mipi-dsi client(lcd panel). */
+ if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->probe)
+ dsim_ddi->dsim_lcd_drv->probe(dsim_ddi->dsim_lcd_dev);
+
+ /* in case that mipi got enabled at bootloader. */
+ if (dsim_pd->enabled)
+ goto out;
+
+ /* lcd panel power on. */
+ if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->power_on)
+ dsim_ddi->dsim_lcd_drv->power_on(dsim_ddi->dsim_lcd_dev);
+
+ if (dsim->pd->mipi_power)
+ dsim->pd->mipi_power(pdev, 1);
+
+ /* enable MIPI-DSI PHY. */
+ if (dsim->pd->phy_enable)
+ dsim->pd->phy_enable(pdev, true);
+
+ s5p_mipi_update_cfg(dsim);
+
+ /* set lcd panel sequence commands. */
+ if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->set_sequence)
+ dsim_ddi->dsim_lcd_drv->set_sequence(dsim_ddi->dsim_lcd_dev);
+
+ atomic_set(&dsim->power_t, 1);
+
+out:
+ platform_set_drvdata(pdev, dsim);
+
+ dev_dbg(&pdev->dev, "mipi-dsi driver(%s mode) has been probed.\n",
+ (dsim_config->e_interface = DSIM_COMMAND) ?
+ "CPU" : "RGB");
+
+ return 0;
+
+err_bind:
+ iounmap((void __iomem *) dsim->reg_base);
+
+err_ioremap:
+ release_mem_region(dsim->res->start, resource_size(dsim->res));
+
+err_mem_region:
+ release_resource(dsim->res);
+
+err_platform_get:
+ clk_disable(dsim->clock);
+ clk_put(dsim->clock);
+
+err_clock_get:
+ kfree(dsim);
+
+err_platform_get_irq:
+ return ret;
+}
+
+static int __devexit s5p_mipi_dsi_remove(struct platform_device *pdev)
+{
+ struct mipi_dsim_device *dsim = platform_get_drvdata(pdev);
+ struct mipi_dsim_ddi *dsim_ddi;
+ struct mipi_dsim_lcd_driver *dsim_lcd_drv;
+
+ iounmap(dsim->reg_base);
+
+ clk_disable(dsim->clock);
+ clk_put(dsim->clock);
+
+ release_resource(dsim->res);
+ release_mem_region(dsim->res->start, resource_size(dsim->res));
+
+ list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) {
+ if (dsim_ddi) {
+ if (dsim->id != dsim_ddi->bus_id)
+ continue;
+
+ dsim_lcd_drv = dsim_ddi->dsim_lcd_drv;
+
+ if (dsim_lcd_drv->remove)
+ dsim_lcd_drv->remove(dsim_ddi->dsim_lcd_dev);
+
+ kfree(dsim_ddi);
+ }
+ }
+
+ kfree(dsim);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int s5p_mipi_dsi_suspend(struct platform_device *pdev,
+ pm_message_t state)
+{
+ struct mipi_dsim_device *dsim = platform_get_drvdata(pdev);
+
+ disable_irq(dsim->irq);
+
+ if (!atomic_read(&dsim->power_t))
+ return 0;
+
+ if (master_to_driver(dsim) && (master_to_driver(dsim))->suspend)
+ (master_to_driver(dsim))->suspend(master_to_device(dsim));
+
+ /* enable MIPI-DSI PHY. */
+ if (dsim->pd->phy_enable)
+ dsim->pd->phy_enable(pdev, false);
+
+ clk_disable(dsim->clock);
+
+ if (dsim->pd->mipi_power)
+ dsim->pd->mipi_power(pdev, 0);
+
+ atomic_set(&dsim->power_t, 0);
+
+ return 0;
+}
+
+static int s5p_mipi_dsi_resume(struct platform_device *pdev)
+{
+ struct mipi_dsim_device *dsim = platform_get_drvdata(pdev);
+ struct mipi_dsim_lcd_driver *client_drv = master_to_driver(dsim);
+ struct mipi_dsim_lcd_device *client_dev = master_to_device(dsim);
+
+ enable_irq(dsim->irq);
+
+ if (atomic_read(&dsim->power_t))
+ return 0;
+
+ /* lcd panel power on. */
+ if (client_drv && client_drv->power_on)
+ client_drv->power_on(client_dev);
+
+ if (dsim->pd->mipi_power)
+ dsim->pd->mipi_power(pdev, 1);
+
+ /* enable MIPI-DSI PHY. */
+ if (dsim->pd->phy_enable)
+ dsim->pd->phy_enable(pdev, true);
+
+ clk_enable(dsim->clock);
+
+ s5p_mipi_update_cfg(dsim);
+
+ /* set lcd panel sequence commands. */
+ if (client_drv && client_drv->set_sequence)
+ client_drv->set_sequence(client_dev);
+
+ atomic_set(&dsim->power_t, 1);
+
+ return 0;
+}
+#else
+#define s5p_mipi_dsi_suspend NULL
+#define s5p_mipi_dsi_resume NULL
+#endif
+
+static struct platform_driver s5p_mipi_dsi_driver = {
+ .probe = s5p_mipi_dsi_probe,
+ .remove = __devexit_p(s5p_mipi_dsi_remove),
+ .suspend = s5p_mipi_dsi_suspend,
+ .resume = s5p_mipi_dsi_resume,
+ .driver = {
+ .name = "s5p-mipi-dsim",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int s5p_mipi_dsi_register(void)
+{
+ platform_driver_register(&s5p_mipi_dsi_driver);
+
+ return 0;
+}
+
+static void s5p_mipi_dsi_unregister(void)
+{
+ platform_driver_unregister(&s5p_mipi_dsi_driver);
+}
+
+module_init(s5p_mipi_dsi_register);
+module_exit(s5p_mipi_dsi_unregister);
+
+MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
+MODULE_DESCRIPTION("Samusung SoC MIPI-DSI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/s5p_mipi_dsi_common.c b/drivers/video/s5p_mipi_dsi_common.c
new file mode 100644
index 0000000..f3452b2
--- /dev/null
+++ b/drivers/video/s5p_mipi_dsi_common.c
@@ -0,0 +1,931 @@
+/* linux/drivers/video/s5p_mipi_dsi_common.c
+ *
+ * Samsung SoC MIPI-DSI common driver.
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * InKi Dae, <inki.dae@samsung.com>
+ * Donghwa Lee, <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/wait.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/fb.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/memory.h>
+#include <linux/delay.h>
+#include <linux/kthread.h>
+#include <linux/mipi_dsim.h>
+
+#include <video/mipi_display.h>
+
+#include <mach/map.h>
+#include <plat/mipi_dsim.h>
+
+#include "s5p_mipi_dsi_regs.h"
+#include "s5p_mipi_dsi_lowlevel.h"
+#include "s5p_mipi_dsi_common.h"
+
+#define MIPI_RX_TIMEOUT HZ
+#define MIPI_RX_FIFO_READ_DONE 0x30800002
+#define MIPI_MAX_RX_FIFO 20
+#define MHZ (1000 * 1000)
+#define FIN_HZ (24 * MHZ)
+
+#define DFIN_PLL_MIN_HZ (6 * MHZ)
+#define DFIN_PLL_MAX_HZ (12 * MHZ)
+
+#define DFVCO_MIN_HZ (500 * MHZ)
+#define DFVCO_MAX_HZ (1000 * MHZ)
+
+#define TRY_GET_FIFO_TIMEOUT (5000 * 2)
+
+/* MIPI-DSIM status types. */
+enum {
+ DSIM_STATE_INIT, /* should be initialized. */
+ DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
+ DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
+ DSIM_STATE_ULPS
+};
+
+/* define DSI lane types. */
+enum {
+ DSIM_LANE_CLOCK = (1 << 0),
+ DSIM_LANE_DATA0 = (1 << 1),
+ DSIM_LANE_DATA1 = (1 << 2),
+ DSIM_LANE_DATA2 = (1 << 3),
+ DSIM_LANE_DATA3 = (1 << 4)
+};
+
+static unsigned int dpll_table[15] = {
+ 100, 120, 170, 220, 270,
+ 320, 390, 450, 510, 560,
+ 640, 690, 770, 870, 950
+};
+
+irqreturn_t s5p_mipi_dsi_interrupt_handler(int irq, void *dev_id)
+{
+ int i;
+ unsigned int intsrc = 0;
+ unsigned int intmsk = 0;
+ struct mipi_dsim_device *dsim = NULL;
+
+ dsim = (struct mipi_dsim_device *)dev_id;
+ if (!dsim) {
+ dev_dbg(dsim->dev, "%s:error:wrong parameter\n", __func__);
+ return IRQ_HANDLED;
+ }
+
+ intsrc = s5p_mipi_dsi_read_interrupt(dsim);
+ intmsk = s5p_mipi_dsi_read_interrupt_mask(dsim);
+
+ intmsk = ~(intmsk) & intsrc;
+
+ for (i = 0; i < 32; i++) {
+ switch (intmsk & (0x1 << i)) {
+ case INTMSK_RX_DONE:
+ complete(&dsim_rd_comp);
+ break;
+ case INTMSK_BTA:
+ /* TODO */
+ break;
+ case INTMSK_RX_TIMEOUT:
+ /* TODO */
+ break;
+ case INTMSK_BTA_TIMEOUT:
+ /* TODO */
+ break;
+ case INTMSK_RX_TE:
+ /* TODO */
+ break;
+ case INTMSK_RX_ACK:
+ /* TODO */
+ break;
+ case INTMSK_RX_ECC_ERR:
+ /* TODO */
+ break;
+ case INTMSK_RX_CRC_ERR:
+ /* TODO */
+ break;
+ case INTMSK_FIFO_EMPTY:
+ /* TODO */
+ break;
+ case INTMSK_FRAME_DONE:
+ /* TODO */
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* clear irq */
+ s5p_mipi_dsi_clear_interrupt(dsim);
+
+ return IRQ_HANDLED;
+}
+
+static void s5p_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
+ unsigned int data0, unsigned int data1)
+{
+ unsigned int data_cnt = 0, payload = 0;
+
+ /* in case that data count is more then 4 */
+ for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
+ /*
+ * after sending 4bytes per one time,
+ * send remainder data less then 4.
+ */
+ if ((data1 - data_cnt) < 4) {
+ if ((data1 - data_cnt) = 3) {
+ payload = *(u8 *)(data0 + data_cnt) |
+ (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
+ (*(u8 *)(data0 + (data_cnt + 2))) << 16;
+ dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
+ payload, *(u8 *)(data0 + data_cnt),
+ *(u8 *)(data0 + (data_cnt + 1)),
+ *(u8 *)(data0 + (data_cnt + 2)));
+ } else if ((data1 - data_cnt) = 2) {
+ payload = *(u8 *)(data0 + data_cnt) |
+ (*(u8 *)(data0 + (data_cnt + 1))) << 8;
+ dev_dbg(dsim->dev,
+ "count = 2 payload = %x, %x %x\n", payload,
+ *(u8 *)(data0 + data_cnt),
+ *(u8 *)(data0 + (data_cnt + 1)));
+ } else if ((data1 - data_cnt) = 1) {
+ payload = *(u8 *)(data0 + data_cnt);
+ }
+
+ s5p_mipi_dsi_wr_tx_data(dsim, payload);
+ /* send 4bytes per one time. */
+ } else {
+ payload = *(u8 *)(data0 + data_cnt) |
+ (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
+ (*(u8 *)(data0 + (data_cnt + 2))) << 16 |
+ (*(u8 *)(data0 + (data_cnt + 3))) << 24;
+
+ dev_dbg(dsim->dev,
+ "count = 4 payload = %x, %x %x %x %x\n",
+ payload, *(u8 *)(data0 + data_cnt),
+ *(u8 *)(data0 + (data_cnt + 1)),
+ *(u8 *)(data0 + (data_cnt + 2)),
+ *(u8 *)(data0 + (data_cnt + 3)));
+
+ s5p_mipi_dsi_wr_tx_data(dsim, payload);
+ }
+ }
+}
+
+int s5p_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
+ unsigned int data0, unsigned int data1)
+{
+ unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
+ unsigned long delay_val, udelay;
+ unsigned int check_rx_ack = 0;
+
+ if (dsim->state = DSIM_STATE_ULPS) {
+ dev_err(dsim->dev, "state is ULPS.\n");
+
+ return -EINVAL;
+ }
+
+ delay_val = MHZ / dsim->dsim_config->esc_clk;
+ udelay = 10 * delay_val;
+
+ mdelay(udelay);
+
+ /* only if transfer mode is LPDT, wait SFR becomes empty. */
+ if (dsim->state = DSIM_STATE_STOP) {
+ while (!(s5p_mipi_dsi_get_fifo_state(dsim) &
+ SFR_HEADER_EMPTY)) {
+ if ((timeout--) > 0)
+ mdelay(1);
+ else {
+ dev_err(dsim->dev,
+ "SRF header fifo is not empty.\n");
+ return -EINVAL;
+ }
+ }
+ }
+
+ switch (data_id) {
+ /* short packet types of packet types for command. */
+ case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
+ case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
+ case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
+ case MIPI_DSI_DCS_SHORT_WRITE:
+ case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+ case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
+ s5p_mipi_dsi_wr_pkt_header(dsim, data_id, data0, data1);
+ if (check_rx_ack)
+ /* process response func should be implemented */
+ return 0;
+ else
+ return -EINVAL;
+
+ /* general command */
+ case MIPI_DSI_COLOR_MODE_OFF:
+ case MIPI_DSI_COLOR_MODE_ON:
+ case MIPI_DSI_SHUTDOWN_PERIPHERAL:
+ case MIPI_DSI_TURN_ON_PERIPHERAL:
+ s5p_mipi_dsi_wr_pkt_header(dsim, data_id, data0, data1);
+ if (check_rx_ack)
+ /* process response func should be implemented. */
+ return 0;
+ else
+ return -EINVAL;
+
+ /* packet types for video data */
+ case MIPI_DSI_V_SYNC_START:
+ case MIPI_DSI_V_SYNC_END:
+ case MIPI_DSI_H_SYNC_START:
+ case MIPI_DSI_H_SYNC_END:
+ case MIPI_DSI_END_OF_TRANSMISSION:
+ return 0;
+
+ /* short and response packet types for command */
+ case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
+ case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
+ case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
+ case MIPI_DSI_DCS_READ:
+ s5p_mipi_dsi_clear_all_interrupt(dsim);
+ s5p_mipi_dsi_wr_pkt_header(dsim, data_id, data0, data1);
+ /* process response func should be implemented. */
+ return 0;
+
+ /* long packet type and null packet */
+ case MIPI_DSI_NULL_PACKET:
+ case MIPI_DSI_BLANKING_PACKET:
+ return 0;
+ case MIPI_DSI_GENERIC_LONG_WRITE:
+ case MIPI_DSI_DCS_LONG_WRITE:
+ {
+ unsigned int size, data_cnt = 0, payload = 0;
+
+ size = data1 * 4;
+
+ /* if data count is less then 4, then send 3bytes data. */
+ if (data1 < 4) {
+ payload = *(u8 *)(data0) |
+ *(u8 *)(data0 + 1) << 8 |
+ *(u8 *)(data0 + 2) << 16;
+
+ s5p_mipi_dsi_wr_tx_data(dsim, payload);
+
+ dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
+ data1, payload,
+ *(u8 *)(data0 + data_cnt),
+ *(u8 *)(data0 + (data_cnt + 1)),
+ *(u8 *)(data0 + (data_cnt + 2)));
+ /* in case that data count is more then 4 */
+ } else
+ s5p_mipi_dsi_long_data_wr(dsim, data0, data1);
+
+ /* put data into header fifo */
+ s5p_mipi_dsi_wr_pkt_header(dsim, data_id, data1 & 0xff,
+ (data1 & 0xff00) >> 8);
+
+ }
+ if (check_rx_ack)
+ /* process response func should be implemented. */
+ return 0;
+ else
+ return -EINVAL;
+
+ /* packet typo for video data */
+ case MIPI_DSI_PACKED_PIXEL_STREAM_16:
+ case MIPI_DSI_PACKED_PIXEL_STREAM_18:
+ case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
+ case MIPI_DSI_PACKED_PIXEL_STREAM_24:
+ if (check_rx_ack)
+ /* process response func should be implemented. */
+ return 0;
+ else
+ return -EINVAL;
+ default:
+ dev_warn(dsim->dev,
+ "data id %x is not supported current DSI spec.\n",
+ data_id);
+
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static unsigned int s5p_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,
+ unsigned int req_size, unsigned int rx_data, u8 *rx_buf)
+{
+ unsigned int rcv_pkt, i, j;
+ u16 rxsize;
+
+ /* for long packet */
+ rxsize = (u16)((rx_data & 0x00ffff00) >> 8);
+ dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize);
+ if (rxsize != req_size) {
+ dev_dbg(dsim->dev,
+ "received data size mismatch\n");
+ dev_dbg(dsim->dev,
+ "received: %d, requested: %d\n", rxsize, req_size);
+ goto err;
+ }
+
+ for (i = 0; i < (rxsize >> 2); i++) {
+ rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim);
+ dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
+ for (j = 0; j < 4; j++) {
+ rx_buf[(i * 4) + j] + (u8)(rcv_pkt >> (j * 8)) & 0xff;
+ dev_dbg(dsim->dev, "received value : %02x\n",
+ (rcv_pkt >> (j * 8)) & 0xff);
+ }
+ }
+ if (rxsize % 4) {
+ rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim);
+ dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
+ for (j = 0; j < (rxsize % 4); j++) {
+ rx_buf[(i * 4) + j] + (u8)(rcv_pkt >> (j * 8)) & 0xff;
+ dev_dbg(dsim->dev, "received value : %02x\n",
+ (rcv_pkt >> (j * 8)) & 0xff);
+ }
+ }
+
+ return rxsize;
+
+err:
+ return -EINVAL;
+}
+
+static unsigned int s5p_mipi_dsi_respense_size(unsigned int req_size)
+{
+ u8 response;
+ switch (req_size) {
+ case 1:
+ response = MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE;
+ break;
+ case 2:
+ response = MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE;
+ break;
+ default:
+ response = MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE;
+ break;
+ }
+
+ return response;
+}
+
+int s5p_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
+ unsigned int data0, unsigned int req_size, u8 *rx_buf)
+{
+ unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
+ unsigned long delay_val, udelay;
+ unsigned int rx_data, rcv_pkt, i;
+ u8 response = 0;
+ u16 rxsize;
+
+ if (dsim->state = DSIM_STATE_ULPS) {
+ dev_err(dsim->dev, "state is ULPS.\n");
+
+ return -EINVAL;
+ }
+
+ delay_val = MHZ / dsim->dsim_config->esc_clk;
+ udelay = 10 * delay_val;
+
+ msleep(udelay);
+
+ /* only if transfer mode is LPDT, wait SFR becomes empty. */
+ if (dsim->state = DSIM_STATE_STOP) {
+ while (!(s5p_mipi_dsi_get_fifo_state(dsim) &
+ SFR_HEADER_EMPTY)) {
+ if ((timeout--) > 0)
+ mdelay(1);
+ else {
+ dev_err(dsim->dev,
+ "SRF header fifo is not empty.\n");
+ return -EINVAL;
+ }
+ }
+ }
+
+ mutex_lock(&dsim->lock);
+ INIT_COMPLETION(dsim_rd_comp);
+ s5p_mipi_dsi_rd_pkt_header(dsim,
+ MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, req_size);
+
+ response = s5p_mipi_dsi_respense_size(req_size);
+
+ msleep(udelay);
+
+ switch (data_id) {
+ case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
+ case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
+ case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
+ case MIPI_DSI_DCS_READ:
+ s5p_mipi_dsi_clear_all_interrupt(dsim);
+ s5p_mipi_dsi_rd_pkt_header(dsim,
+ data_id, data0);
+ /* process response func should be implemented. */
+ break;
+ default:
+ dev_warn(dsim->dev,
+ "data id %x is not supported current DSI spec.\n",
+ data_id);
+
+ return -EINVAL;
+ }
+
+ if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp,
+ MIPI_RX_TIMEOUT)) {
+ printk(KERN_ERR "RX done interrupt timeout\n");
+ mutex_unlock(&dsim->lock);
+ return 0;
+ }
+
+ msleep(20);
+
+ rx_data = s5p_mipi_dsi_rd_rx_fifo(dsim);
+
+ if ((u8)(rx_data & 0xff) != response) {
+ printk(KERN_ERR
+ "mipi dsi wrong response rx_data : %x, response:%x\n",
+ rx_data, response);
+ goto clear_rx_fifo;
+ }
+
+ if (req_size <= 2) {
+ /* for short packet */
+ for (i = 0; i < req_size; i++)
+ rx_buf[i] = (rx_data >> (8 + (i * 8))) & 0xff;
+ rxsize = req_size;
+ } else {
+ /* for long packet */
+ rxsize = s5p_mipi_dsi_long_data_rd(dsim, req_size, rx_data,
+ rx_buf);
+ if (rxsize != req_size)
+ goto clear_rx_fifo;
+ }
+
+ rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim);
+
+ msleep(20);
+
+ if (rcv_pkt != MIPI_RX_FIFO_READ_DONE) {
+ dev_info(dsim->dev,
+ "Can't found RX FIFO READ DONE FLAG : %x\n", rcv_pkt);
+ goto clear_rx_fifo;
+ }
+
+ mutex_unlock(&dsim->lock);
+
+ return rxsize;
+
+clear_rx_fifo:
+ i = 0;
+ while (1) {
+ rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim);
+ if ((rcv_pkt = MIPI_RX_FIFO_READ_DONE)
+ || (i > MIPI_MAX_RX_FIFO))
+ break;
+ dev_dbg(dsim->dev,
+ "mipi dsi clear rx fifo : %08x\n", rcv_pkt);
+ i++;
+ }
+ dev_info(dsim->dev,
+ "mipi dsi rx done count : %d, rcv_pkt : %08x\n", i, rcv_pkt);
+
+ mutex_unlock(&dsim->lock);
+
+ return 0;
+}
+
+int s5p_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable)
+{
+ int sw_timeout;
+
+ if (enable) {
+ sw_timeout = 1000;
+
+ s5p_mipi_dsi_clear_interrupt(dsim);
+ s5p_mipi_dsi_enable_pll(dsim, 1);
+ while (1) {
+ sw_timeout--;
+ if (s5p_mipi_dsi_is_pll_stable(dsim))
+ return 0;
+ if (sw_timeout = 0)
+ return -EINVAL;
+ }
+ } else
+ s5p_mipi_dsi_enable_pll(dsim, 0);
+
+ return 0;
+}
+
+unsigned long s5p_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
+ unsigned int pre_divider, unsigned int main_divider,
+ unsigned int scaler)
+{
+ unsigned long dfin_pll, dfvco, dpll_out;
+ unsigned int i, freq_band = 0xf;
+
+ dfin_pll = (FIN_HZ / pre_divider);
+
+ /******************************************************
+ * Serial Clock(=ByteClk X 8) FreqBand[3:0] *
+ ******************************************************
+ * ~ 99.99 MHz 0000
+ * 100 ~ 119.99 MHz 0001
+ * 120 ~ 159.99 MHz 0010
+ * 160 ~ 199.99 MHz 0011
+ * 200 ~ 239.99 MHz 0100
+ * 140 ~ 319.99 MHz 0101
+ * 320 ~ 389.99 MHz 0110
+ * 390 ~ 449.99 MHz 0111
+ * 450 ~ 509.99 MHz 1000
+ * 510 ~ 559.99 MHz 1001
+ * 560 ~ 639.99 MHz 1010
+ * 640 ~ 689.99 MHz 1011
+ * 690 ~ 769.99 MHz 1100
+ * 770 ~ 869.99 MHz 1101
+ * 870 ~ 949.99 MHz 1110
+ * 950 ~ 1000 MHz 1111
+ ******************************************************/
+ if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
+ dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");
+ s5p_mipi_dsi_enable_afc(dsim, 0, 0);
+ } else {
+ if (dfin_pll < 7 * MHZ)
+ s5p_mipi_dsi_enable_afc(dsim, 1, 0x1);
+ else if (dfin_pll < 8 * MHZ)
+ s5p_mipi_dsi_enable_afc(dsim, 1, 0x0);
+ else if (dfin_pll < 9 * MHZ)
+ s5p_mipi_dsi_enable_afc(dsim, 1, 0x3);
+ else if (dfin_pll < 10 * MHZ)
+ s5p_mipi_dsi_enable_afc(dsim, 1, 0x2);
+ else if (dfin_pll < 11 * MHZ)
+ s5p_mipi_dsi_enable_afc(dsim, 1, 0x5);
+ else
+ s5p_mipi_dsi_enable_afc(dsim, 1, 0x4);
+ }
+
+ dfvco = dfin_pll * main_divider;
+ dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
+ dfvco, dfin_pll, main_divider);
+ if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
+ dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");
+
+ dpll_out = dfvco / (1 << scaler);
+ dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
+ dpll_out, dfvco, scaler);
+
+ for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
+ if (dpll_out < dpll_table[i] * MHZ) {
+ freq_band = i;
+ break;
+ }
+ }
+
+ dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
+
+ s5p_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
+
+ s5p_mipi_dsi_hs_zero_ctrl(dsim, 0);
+ s5p_mipi_dsi_prep_ctrl(dsim, 0);
+
+ /* Freq Band */
+ s5p_mipi_dsi_pll_freq_band(dsim, freq_band);
+
+ /* Stable time */
+ s5p_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);
+
+ /* Enable PLL */
+ dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
+ (dpll_out / MHZ));
+
+ return dpll_out;
+}
+
+int s5p_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
+ unsigned int byte_clk_sel, unsigned int enable)
+{
+ unsigned int esc_div;
+ unsigned long esc_clk_error_rate;
+ unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
+
+ if (enable) {
+ dsim->e_clk_src = byte_clk_sel;
+
+ /* Escape mode clock and byte clock source */
+ s5p_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
+
+ /* DPHY, DSIM Link : D-PHY clock out */
+ if (byte_clk_sel = DSIM_PLL_OUT_DIV8) {
+ hs_clk = s5p_mipi_dsi_change_pll(dsim,
+ dsim->dsim_config->p, dsim->dsim_config->m,
+ dsim->dsim_config->s);
+ if (hs_clk = 0) {
+ dev_err(dsim->dev,
+ "failed to get hs clock.\n");
+ return -EINVAL;
+ }
+
+ byte_clk = hs_clk / 8;
+ s5p_mipi_dsi_enable_pll_bypass(dsim, 0);
+ s5p_mipi_dsi_pll_on(dsim, 1);
+ /* DPHY : D-PHY clock out, DSIM link : external clock out */
+ } else if (byte_clk_sel = DSIM_EXT_CLK_DIV8) {
+ dev_warn(dsim->dev, "this project is not support\n");
+ dev_warn(dsim->dev,
+ "external clock source for MIPI DSIM.\n");
+ } else if (byte_clk_sel = DSIM_EXT_CLK_BYPASS) {
+ dev_warn(dsim->dev, "this project is not support\n");
+ dev_warn(dsim->dev,
+ "external clock source for MIPI DSIM\n");
+ }
+
+ /* escape clock divider */
+ esc_div = byte_clk / (dsim->dsim_config->esc_clk);
+ dev_dbg(dsim->dev,
+ "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
+ esc_div, byte_clk, dsim->dsim_config->esc_clk);
+ if ((byte_clk / esc_div) >= (20 * MHZ) ||
+ (byte_clk / esc_div) >
+ dsim->dsim_config->esc_clk)
+ esc_div += 1;
+
+ escape_clk = byte_clk / esc_div;
+ dev_dbg(dsim->dev,
+ "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
+ escape_clk, byte_clk, esc_div);
+
+ /* enable escape clock. */
+ s5p_mipi_dsi_enable_byte_clock(dsim, 1);
+
+ /* enable byte clk and escape clock */
+ s5p_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
+ /* escape clock on lane */
+ s5p_mipi_dsi_enable_esc_clk_on_lane(dsim,
+ (DSIM_LANE_CLOCK | dsim->data_lane), 1);
+
+ dev_dbg(dsim->dev, "byte clock is %luMHz\n",
+ (byte_clk / MHZ));
+ dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
+ (dsim->dsim_config->esc_clk / MHZ));
+ dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
+ dev_dbg(dsim->dev, "escape clock is %luMHz\n",
+ ((byte_clk / esc_div) / MHZ));
+
+ if ((byte_clk / esc_div) > escape_clk) {
+ esc_clk_error_rate = escape_clk /
+ (byte_clk / esc_div);
+ dev_warn(dsim->dev, "error rate is %lu over.\n",
+ (esc_clk_error_rate / 100));
+ } else if ((byte_clk / esc_div) < (escape_clk)) {
+ esc_clk_error_rate = (byte_clk / esc_div) /
+ escape_clk;
+ dev_warn(dsim->dev, "error rate is %lu under.\n",
+ (esc_clk_error_rate / 100));
+ }
+ } else {
+ s5p_mipi_dsi_enable_esc_clk_on_lane(dsim,
+ (DSIM_LANE_CLOCK | dsim->data_lane), 0);
+ s5p_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
+
+ /* disable escape clock. */
+ s5p_mipi_dsi_enable_byte_clock(dsim, 0);
+
+ if (byte_clk_sel = DSIM_PLL_OUT_DIV8)
+ s5p_mipi_dsi_pll_on(dsim, 0);
+ }
+
+ return 0;
+}
+
+int s5p_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
+{
+ dsim->state = DSIM_STATE_INIT;
+
+ switch (dsim->dsim_config->e_no_data_lane) {
+ case DSIM_DATA_LANE_1:
+ dsim->data_lane = DSIM_LANE_DATA0;
+ break;
+ case DSIM_DATA_LANE_2:
+ dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
+ break;
+ case DSIM_DATA_LANE_3:
+ dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
+ DSIM_LANE_DATA2;
+ break;
+ case DSIM_DATA_LANE_4:
+ dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
+ DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
+ break;
+ default:
+ dev_info(dsim->dev, "data lane is invalid.\n");
+ return -EINVAL;
+ };
+
+ s5p_mipi_dsi_sw_reset(dsim);
+ s5p_mipi_dsi_func_reset(dsim);
+
+ s5p_mipi_dsi_dp_dn_swap(dsim, 0);
+
+ return 0;
+}
+
+void s5p_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg;
+
+ s5p_mipi_dsi_clear_all_interrupt(dsim);
+
+ reg = s5p_mipi_dsi_read_interrupt_mask(dsim);
+
+ reg &= (INTMSK_BTA | INTMSK_RX_TIMEOUT |
+ INTMSK_BTA_TIMEOUT | INTMSK_RX_DONE |
+ INTMSK_RX_TE | INTMSK_RX_ACK |
+ INTMSK_RX_ECC_ERR | INTMSK_RX_CRC_ERR |
+ INTMSK_FIFO_EMPTY);
+
+ s5p_mipi_dsi_set_interrupt_mask(dsim, reg, 0);
+}
+
+int s5p_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
+ unsigned int enable)
+{
+ /* enable only frame done interrupt */
+ s5p_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
+
+ return 0;
+}
+
+void s5p_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
+ unsigned int enable)
+{
+
+ /* consider Main display and Sub display. */
+
+ s5p_mipi_dsi_set_main_stand_by(dsim, enable);
+}
+
+int s5p_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
+ struct mipi_dsim_config *dsim_config)
+{
+ struct mipi_dsim_platform_data *dsim_pd;
+ struct fb_videomode *timing;
+
+ dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;
+ timing = (struct fb_videomode *)dsim_pd->lcd_panel_info;
+
+ /* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
+ if (dsim_config->e_interface = (u32) DSIM_VIDEO) {
+ if (dsim_config->auto_vertical_cnt = 0) {
+ s5p_mipi_dsi_set_main_disp_vporch(dsim,
+ dsim_config->cmd_allow,
+ timing->upper_margin,
+ timing->lower_margin);
+ s5p_mipi_dsi_set_main_disp_hporch(dsim,
+ timing->left_margin,
+ timing->right_margin);
+ s5p_mipi_dsi_set_main_disp_sync_area(dsim,
+ timing->vsync_len,
+ timing->hsync_len);
+ }
+ }
+
+ s5p_mipi_dsi_set_main_disp_resol(dsim, timing->xres,
+ timing->yres);
+
+ s5p_mipi_dsi_display_config(dsim, dsim_config);
+
+ dev_info(dsim->dev, "lcd panel => width = %d, height = %d\n",
+ timing->xres, timing->yres);
+
+ return 0;
+}
+
+int s5p_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
+{
+ unsigned int time_out = 100;
+
+ switch (dsim->state) {
+ case DSIM_STATE_INIT:
+ s5p_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
+
+ /* dsi configuration */
+ s5p_mipi_dsi_init_config(dsim);
+ s5p_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
+ s5p_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
+
+ /* set clock configuration */
+ s5p_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);
+
+ /* check clock and data lane state are stop state */
+ while (!(s5p_mipi_dsi_is_lane_state(dsim))) {
+ time_out--;
+ if (time_out = 0) {
+ dev_err(dsim->dev,
+ "DSI Master is not stop state.\n");
+ dev_err(dsim->dev,
+ "Check initialization process\n");
+
+ return -EINVAL;
+ }
+ }
+ if (time_out != 0) {
+ dev_info(dsim->dev,
+ "DSI Master driver has been completed.\n");
+ dev_info(dsim->dev, "DSI Master state is stop state\n");
+ }
+
+ dsim->state = DSIM_STATE_STOP;
+
+ /* BTA sequence counters */
+ s5p_mipi_dsi_set_stop_state_counter(dsim,
+ dsim->dsim_config->stop_holding_cnt);
+ s5p_mipi_dsi_set_bta_timeout(dsim,
+ dsim->dsim_config->bta_timeout);
+ s5p_mipi_dsi_set_lpdr_timeout(dsim,
+ dsim->dsim_config->rx_timeout);
+
+ return 0;
+ default:
+ dev_info(dsim->dev, "DSI Master is already init.\n");
+ return 0;
+ }
+
+ return 0;
+}
+
+int s5p_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
+{
+ if (dsim->state = DSIM_STATE_STOP) {
+ if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
+ dsim->state = DSIM_STATE_HSCLKEN;
+
+ /* set LCDC and CPU transfer mode to HS. */
+ s5p_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
+ s5p_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
+
+ s5p_mipi_dsi_enable_hs_clock(dsim, 1);
+
+ return 0;
+ } else
+ dev_warn(dsim->dev,
+ "clock source is external bypass.\n");
+ } else
+ dev_warn(dsim->dev, "DSIM is not stop state.\n");
+
+ return 0;
+}
+
+int s5p_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
+ unsigned int mode)
+{
+ if (mode) {
+ if (dsim->state != DSIM_STATE_HSCLKEN) {
+ dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
+ return -EINVAL;
+ }
+
+ s5p_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
+ } else {
+ if (dsim->state = DSIM_STATE_INIT || dsim->state =
+ DSIM_STATE_ULPS) {
+ dev_err(dsim->dev,
+ "DSI Master is not STOP or HSDT state.\n");
+ return -EINVAL;
+ }
+
+ s5p_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
+ }
+
+ return 0;
+}
+
+int s5p_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
+{
+ return _s5p_mipi_dsi_get_frame_done_status(dsim);
+}
+
+int s5p_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
+{
+ _s5p_mipi_dsi_clear_frame_done(dsim);
+
+ return 0;
+}
+
+MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
+MODULE_DESCRIPTION("Samusung SoC MIPI-DSI common driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/s5p_mipi_dsi_common.h b/drivers/video/s5p_mipi_dsi_common.h
new file mode 100644
index 0000000..89f065a
--- /dev/null
+++ b/drivers/video/s5p_mipi_dsi_common.h
@@ -0,0 +1,48 @@
+/* linux/drivers/video/s5p_mipi_dsi_common.h
+ *
+ * Header file for Samsung SoC MIPI-DSI common driver.
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * InKi Dae <inki.dae@samsung.com>
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _S5P_MIPI_DSI_COMMON_H
+#define _S5P_MIPI_DSI_COMMON_H
+
+static DECLARE_COMPLETION(dsim_rd_comp);
+
+int s5p_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
+ unsigned int data0, unsigned int data1);
+int s5p_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
+ unsigned int data0, unsigned int req_size, u8 *rx_buf);
+int s5p_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable);
+unsigned long s5p_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
+ unsigned int pre_divider, unsigned int main_divider,
+ unsigned int scaler);
+irqreturn_t s5p_mipi_dsi_interrupt_handler(int irq, void *dev_id);
+void s5p_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim);
+int s5p_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
+ unsigned int byte_clk_sel, unsigned int enable);
+int s5p_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim);
+void s5p_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
+ unsigned int enable);
+int s5p_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
+ struct mipi_dsim_config *dsim_info);
+int s5p_mipi_dsi_init_link(struct mipi_dsim_device *dsim);
+int s5p_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim);
+int s5p_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
+ unsigned int mode);
+int s5p_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
+ unsigned int enable);
+int s5p_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim);
+int s5p_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
+
+extern struct fb_info *registered_fb[FB_MAX] __read_mostly;
+
+#endif /* _S5P_MIPI_DSI_COMMON_H */
diff --git a/drivers/video/s5p_mipi_dsi_lowlevel.c b/drivers/video/s5p_mipi_dsi_lowlevel.c
new file mode 100644
index 0000000..e6a9358
--- /dev/null
+++ b/drivers/video/s5p_mipi_dsi_lowlevel.c
@@ -0,0 +1,608 @@
+/* linux/drivers/video/s5p_mipi_dsi_lowlevel.c
+ *
+ * Samsung SoC MIPI-DSI lowlevel driver.
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * InKi Dae, <inki.dae@samsung.com>
+ * Donghwa Lee, <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include <linux/mipi_dsim.h>
+
+#include <mach/map.h>
+#include <plat/mipi_dsim.h>
+
+#include "s5p_mipi_dsi_regs.h"
+
+void s5p_mipi_dsi_func_reset(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg;
+
+ reg = readl(dsim->reg_base + S5P_DSIM_SWRST);
+
+ reg |= DSIM_FUNCRST;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_SWRST);
+}
+
+void s5p_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg;
+
+ reg = readl(dsim->reg_base + S5P_DSIM_SWRST);
+
+ reg |= DSIM_SWRST;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_SWRST);
+}
+
+unsigned int s5p_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg;
+
+ reg = readl(dsim->reg_base + S5P_DSIM_INTMSK);
+
+ return reg;
+}
+
+void s5p_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
+ unsigned int mode, unsigned int mask)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTMSK);
+
+ if (mask)
+ reg |= mode;
+ else
+ reg &= ~mode;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_INTMSK);
+}
+
+void s5p_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
+ unsigned int cfg)
+{
+ unsigned int reg;
+
+ reg = readl(dsim->reg_base + S5P_DSIM_FIFOCTRL);
+
+ writel(reg & ~(cfg), dsim->reg_base + S5P_DSIM_FIFOCTRL);
+ mdelay(10);
+ reg |= cfg;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_FIFOCTRL);
+}
+
+/*
+ * this function set PLL P, M and S value in D-PHY
+ */
+void s5p_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
+ unsigned int value)
+{
+ writel(DSIM_AFC_CTL(value), dsim->reg_base + S5P_DSIM_PHYACCHR);
+}
+
+void s5p_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim,
+ unsigned int enable)
+{
+ unsigned int reg;
+
+ reg = readl(dsim->reg_base + S5P_DSIM_MDRESOL);
+
+ reg &= ~DSIM_MAIN_STAND_BY;
+
+ if (enable)
+ reg |= DSIM_MAIN_STAND_BY;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_MDRESOL);
+}
+
+void s5p_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
+ unsigned int width_resol, unsigned int height_resol)
+{
+ unsigned int reg;
+
+ /* standby should be set after configuration so set to not ready*/
+ reg = (readl(dsim->reg_base + S5P_DSIM_MDRESOL)) &
+ ~(DSIM_MAIN_STAND_BY);
+ writel(reg, dsim->reg_base + S5P_DSIM_MDRESOL);
+
+ reg &= ~((0x7ff << 16) | (0x7ff << 0));
+ reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);
+
+ reg |= DSIM_MAIN_STAND_BY;
+ writel(reg, dsim->reg_base + S5P_DSIM_MDRESOL);
+}
+
+void s5p_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
+ unsigned int cmd_allow, unsigned int vfront, unsigned int vback)
+{
+ unsigned int reg;
+
+ reg = (readl(dsim->reg_base + S5P_DSIM_MVPORCH)) &
+ ~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) |
+ (DSIM_MAIN_VBP_MASK));
+
+ reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) |
+ ((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) |
+ ((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_MVPORCH);
+}
+
+void s5p_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
+ unsigned int front, unsigned int back)
+{
+ unsigned int reg;
+
+ reg = (readl(dsim->reg_base + S5P_DSIM_MHPORCH)) &
+ ~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK));
+
+ reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_MHPORCH);
+}
+
+void s5p_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
+ unsigned int vert, unsigned int hori)
+{
+ unsigned int reg;
+
+ reg = (readl(dsim->reg_base + S5P_DSIM_MSYNC)) &
+ ~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK));
+
+ reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) |
+ (hori << DSIM_MAIN_HSA_SHIFT);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_MSYNC);
+}
+
+void s5p_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
+ unsigned int vert, unsigned int hori)
+{
+ unsigned int reg;
+
+ reg = (readl(dsim->reg_base + S5P_DSIM_SDRESOL)) &
+ ~(DSIM_SUB_STANDY_MASK);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL);
+
+ reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
+ reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) |
+ ((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT);
+ writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL);
+
+ reg |= (1 << DSIM_SUB_STANDY_SHIFT);
+ writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL);
+}
+
+void s5p_mipi_dsi_init_config(struct mipi_dsim_device *dsim)
+{
+ struct mipi_dsim_config *dsim_config = dsim->dsim_config;
+
+ unsigned int cfg = (readl(dsim->reg_base + S5P_DSIM_CONFIG)) &
+ ~((1 << 28) | (0x1f << 20) | (0x3 << 5));
+
+ cfg = (dsim_config->auto_flush << 29) |
+ (dsim_config->eot_disable << 28) |
+ (dsim_config->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) |
+ (dsim_config->hse << DSIM_HSE_MODE_SHIFT) |
+ (dsim_config->hfp << DSIM_HFP_MODE_SHIFT) |
+ (dsim_config->hbp << DSIM_HBP_MODE_SHIFT) |
+ (dsim_config->hsa << DSIM_HSA_MODE_SHIFT) |
+ (dsim_config->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT);
+
+ writel(cfg, dsim->reg_base + S5P_DSIM_CONFIG);
+}
+
+void s5p_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
+ struct mipi_dsim_config *dsim_config)
+{
+ u32 reg = (readl(dsim->reg_base + S5P_DSIM_CONFIG)) &
+ ~((0x3 << 26) | (1 << 25) | (0x3 << 18) | (0x7 << 12) |
+ (0x3 << 16) | (0x7 << 8));
+
+ if (dsim_config->e_interface = DSIM_VIDEO)
+ reg |= (1 << 25);
+ else if (dsim_config->e_interface = DSIM_COMMAND)
+ reg &= ~(1 << 25);
+ else {
+ dev_err(dsim->dev, "unknown lcd type.\n");
+ return;
+ }
+
+ /* main lcd */
+ reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << 26 |
+ ((u8) (dsim_config->e_virtual_ch) & 0x3) << 18 |
+ ((u8) (dsim_config->e_pixel_format) & 0x7) << 12;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_CONFIG);
+}
+
+void s5p_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane,
+ unsigned int enable)
+{
+ unsigned int reg;
+
+ reg = readl(dsim->reg_base + S5P_DSIM_CONFIG);
+
+ if (enable)
+ reg |= DSIM_LANE_ENx(lane);
+ else
+ reg &= ~DSIM_LANE_ENx(lane);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_CONFIG);
+}
+
+
+void s5p_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
+ unsigned int count)
+{
+ unsigned int cfg;
+
+ /* get the data lane number. */
+ cfg = DSIM_NUM_OF_DATA_LANE(count);
+
+ writel(cfg, dsim->reg_base + S5P_DSIM_CONFIG);
+}
+
+void s5p_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable,
+ unsigned int afc_code)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PHYACCHR);
+
+ if (enable) {
+ reg |= (1 << 14);
+ reg &= ~(0x7 << 5);
+ reg |= (afc_code & 0x7) << 5;
+ } else
+ reg &= ~(1 << 14);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_PHYACCHR);
+}
+
+void s5p_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
+ unsigned int enable)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &
+ ~(DSIM_PLL_BYPASS_EXTERNAL);
+
+ reg |= enable << DSIM_PLL_BYPASS_SHIFT;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p,
+ unsigned int m, unsigned int s)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PLLCTRL);
+
+ reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
+ unsigned int freq_band)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &
+ ~(0x1f << DSIM_FREQ_BAND_SHIFT);
+
+ reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
+ unsigned int pre_divider, unsigned int main_divider,
+ unsigned int scaler)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &
+ ~(0x7ffff << 1);
+
+ reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 |
+ (scaler & 0x7) << 1;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
+ unsigned int lock_time)
+{
+ writel(lock_time, dsim->reg_base + S5P_DSIM_PLLTMR);
+}
+
+void s5p_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, unsigned int enable)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &
+ ~(0x1 << DSIM_PLL_EN_SHIFT);
+
+ reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
+ unsigned int src)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &
+ ~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT);
+
+ reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
+ unsigned int enable)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &
+ ~(1 << DSIM_BYTE_CLKEN_SHIFT);
+
+ reg |= enable << DSIM_BYTE_CLKEN_SHIFT;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
+ unsigned int enable, unsigned int prs_val)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &
+ ~((1 << DSIM_ESC_CLKEN_SHIFT) | (0xffff));
+
+ reg |= enable << DSIM_ESC_CLKEN_SHIFT;
+ if (enable)
+ reg |= prs_val;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
+ unsigned int lane_sel, unsigned int enable)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_CLKCTRL);
+
+ if (enable)
+ reg |= DSIM_LANE_ESC_CLKEN(lane_sel);
+ else
+
+ reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
+ unsigned int enable)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_ESCMODE)) &
+ ~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT);
+
+ reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE);
+}
+
+unsigned int s5p_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_STATUS);
+
+ /**
+ * check clock and data lane states.
+ * if MIPI-DSI controller was enabled at bootloader then
+ * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK.
+ * so it should be checked for two case.
+ */
+ if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&
+ ((reg & DSIM_STOP_STATE_CLK) ||
+ (reg & DSIM_TX_READY_HS_CLK)))
+ return 1;
+ else
+ return 0;
+
+ return 0;
+}
+
+void s5p_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
+ unsigned int cnt_val)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_ESCMODE)) &
+ ~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT);
+
+ reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE);
+}
+
+void s5p_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
+ unsigned int timeout)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_TIMEOUT)) &
+ ~(0xff << DSIM_BTA_TOUT_SHIFT);
+
+ reg |= (timeout << DSIM_BTA_TOUT_SHIFT);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_TIMEOUT);
+}
+
+void s5p_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
+ unsigned int timeout)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_TIMEOUT)) &
+ ~(0xffff << DSIM_LPDR_TOUT_SHIFT);
+
+ reg |= (timeout << DSIM_LPDR_TOUT_SHIFT);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_TIMEOUT);
+}
+
+void s5p_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
+ unsigned int lp)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_ESCMODE);
+
+ reg &= ~DSIM_CMD_LPDT_LP;
+
+ if (lp)
+ reg |= DSIM_CMD_LPDT_LP;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE);
+}
+
+void s5p_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
+ unsigned int lp)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_ESCMODE);
+
+ reg &= ~DSIM_TX_LPDT_LP;
+
+ if (lp)
+ reg |= DSIM_TX_LPDT_LP;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE);
+}
+
+void s5p_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
+ unsigned int enable)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &
+ ~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT);
+
+ reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
+ unsigned int swap_en)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PHYACCHR1);
+
+ reg &= ~(0x3 << 0);
+ reg |= (swap_en & 0x3) << 0;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_PHYACCHR1);
+}
+
+void s5p_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
+ unsigned int hs_zero)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &
+ ~(0xf << 28);
+
+ reg |= ((hs_zero & 0xf) << 28);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep)
+{
+ unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &
+ ~(0x7 << 20);
+
+ reg |= ((prep & 0x7) << 20);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+unsigned int s5p_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);
+
+ return reg;
+}
+
+void s5p_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);
+
+ reg |= INTSRC_PLL_STABLE;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_INTSRC);
+}
+
+void s5p_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);
+
+ reg |= 0xffffffff;
+
+ writel(reg, dsim->reg_base + S5P_DSIM_INTSRC);
+}
+
+unsigned int s5p_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg;
+
+ reg = readl(dsim->reg_base + S5P_DSIM_STATUS);
+
+ return reg & (1 << 31) ? 1 : 0;
+}
+
+unsigned int s5p_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim)
+{
+ unsigned int ret;
+
+ ret = readl(dsim->reg_base + S5P_DSIM_FIFOCTRL) & ~(0x1f);
+
+ return ret;
+}
+
+void s5p_mipi_dsi_wr_pkt_header(struct mipi_dsim_device *dsim,
+ unsigned int di, unsigned int data0, unsigned int data1)
+{
+ unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_PKTHDR);
+}
+
+void s5p_mipi_dsi_rd_pkt_header(struct mipi_dsim_device *dsim,
+ unsigned int di, unsigned int data0)
+{
+ unsigned int reg = (data0 << 8) | (di << 0);
+
+ writel(reg, dsim->reg_base + S5P_DSIM_PKTHDR);
+}
+
+unsigned int s5p_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg = 0;
+
+ reg = readl(dsim->reg_base + S5P_DSIM_RXFIFO);
+
+ return reg;
+}
+
+unsigned int _s5p_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);
+
+ return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
+}
+
+void _s5p_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
+{
+ unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);
+
+ writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +
+ S5P_DSIM_INTSRC);
+}
+
+void s5p_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
+ unsigned int tx_data)
+{
+ writel(tx_data, dsim->reg_base + S5P_DSIM_PAYLOAD);
+}
diff --git a/drivers/video/s5p_mipi_dsi_lowlevel.h b/drivers/video/s5p_mipi_dsi_lowlevel.h
new file mode 100644
index 0000000..d224fce
--- /dev/null
+++ b/drivers/video/s5p_mipi_dsi_lowlevel.h
@@ -0,0 +1,108 @@
+/* linux/drivers/video/s5p_mipi_dsi_lowlevel.h
+ *
+ * Header file for Samsung SoC MIPI-DSI lowlevel driver.
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * InKi Dae <inki.dae@samsung.com>
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _S5P_MIPI_DSI_LOWLEVEL_H
+#define _S5P_MIPI_DSI_LOWLEVEL_H
+
+void s5p_mipi_dsi_func_reset(struct mipi_dsim_device *dsim);
+void s5p_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim);
+void s5p_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
+ unsigned int mode, unsigned int mask);
+void s5p_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
+ unsigned int count);
+void s5p_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
+ unsigned int cfg);
+void s5p_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
+ unsigned int value);
+void s5p_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
+ unsigned int value);
+void s5p_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim,
+ unsigned int enable);
+void s5p_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
+ unsigned int width_resol, unsigned int height_resol);
+void s5p_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
+ unsigned int cmd_allow, unsigned int vfront, unsigned int vback);
+void s5p_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
+ unsigned int front, unsigned int back);
+void s5p_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
+ unsigned int vert, unsigned int hori);
+void s5p_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
+ unsigned int vert, unsigned int hori);
+void s5p_mipi_dsi_init_config(struct mipi_dsim_device *dsim);
+void s5p_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
+ struct mipi_dsim_config *dsim_config);
+void s5p_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
+ unsigned int count);
+void s5p_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane,
+ unsigned int enable);
+void s5p_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable,
+ unsigned int afc_code);
+void s5p_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
+ unsigned int enable);
+void s5p_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p,
+ unsigned int m, unsigned int s);
+void s5p_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
+ unsigned int freq_band);
+void s5p_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
+ unsigned int pre_divider, unsigned int main_divider,
+ unsigned int scaler);
+void s5p_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
+ unsigned int lock_time);
+void s5p_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim,
+ unsigned int enable);
+void s5p_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
+ unsigned int src);
+void s5p_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
+ unsigned int enable);
+void s5p_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
+ unsigned int enable, unsigned int prs_val);
+void s5p_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
+ unsigned int lane_sel, unsigned int enable);
+void s5p_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
+ unsigned int enable);
+unsigned int s5p_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim);
+void s5p_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
+ unsigned int cnt_val);
+void s5p_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
+ unsigned int timeout);
+void s5p_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
+ unsigned int timeout);
+void s5p_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
+ unsigned int lp);
+void s5p_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
+ unsigned int lp);
+void s5p_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
+ unsigned int enable);
+void s5p_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
+ unsigned int swap_en);
+void s5p_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
+ unsigned int hs_zero);
+void s5p_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep);
+unsigned int s5p_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim);
+unsigned int s5p_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim);
+void s5p_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim);
+void s5p_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim);
+unsigned int s5p_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim);
+unsigned int s5p_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim);
+unsigned int _s5p_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim);
+void _s5p_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
+void s5p_mipi_dsi_wr_pkt_header(struct mipi_dsim_device *dsim, unsigned int di,
+ unsigned int data0, unsigned int data1);
+void s5p_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
+ unsigned int tx_data);
+void s5p_mipi_dsi_rd_pkt_header(struct mipi_dsim_device *dsim,
+ unsigned int data0, unsigned int data1);
+unsigned int s5p_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim);
+
+#endif /* _S5P_MIPI_DSI_LOWLEVEL_H */
diff --git a/drivers/video/s5p_mipi_dsi_regs.h b/drivers/video/s5p_mipi_dsi_regs.h
new file mode 100644
index 0000000..e1e488f
--- /dev/null
+++ b/drivers/video/s5p_mipi_dsi_regs.h
@@ -0,0 +1,153 @@
+/* linux/driver/video/s5p_mipi_dsi_regs.h
+ *
+ * Register definition file for Samsung MIPI-DSIM driver
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * InKi Dae <inki.dae@samsung.com>
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _REGS_DSIM_H
+#define _REGS_DSIM_H
+
+#define S5P_DSIM_STATUS (0x0) /* Status register */
+#define S5P_DSIM_SWRST (0x4) /* Software reset register */
+#define S5P_DSIM_CLKCTRL (0x8) /* Clock control register */
+#define S5P_DSIM_TIMEOUT (0xc) /* Time out register */
+#define S5P_DSIM_CONFIG (0x10) /* Configuration register */
+#define S5P_DSIM_ESCMODE (0x14) /* Escape mode register */
+
+/* Main display image resolution register */
+#define S5P_DSIM_MDRESOL (0x18)
+#define S5P_DSIM_MVPORCH (0x1c) /* Main display Vporch register */
+#define S5P_DSIM_MHPORCH (0x20) /* Main display Hporch register */
+#define S5P_DSIM_MSYNC (0x24) /* Main display sync area register */
+
+/* Sub display image resolution register */
+#define S5P_DSIM_SDRESOL (0x28)
+#define S5P_DSIM_INTSRC (0x2c) /* Interrupt source register */
+#define S5P_DSIM_INTMSK (0x30) /* Interrupt mask register */
+#define S5P_DSIM_PKTHDR (0x34) /* Packet Header FIFO register */
+#define S5P_DSIM_PAYLOAD (0x38) /* Payload FIFO register */
+#define S5P_DSIM_RXFIFO (0x3c) /* Read FIFO register */
+#define S5P_DSIM_FIFOTHLD (0x40) /* FIFO threshold level register */
+#define S5P_DSIM_FIFOCTRL (0x44) /* FIFO status and control register */
+
+/* FIFO memory AC characteristic register */
+#define S5P_DSIM_PLLCTRL (0x4c) /* PLL control register */
+#define S5P_DSIM_PLLTMR (0x50) /* PLL timer register */
+#define S5P_DSIM_PHYACCHR (0x54) /* D-PHY AC characteristic register */
+#define S5P_DSIM_PHYACCHR1 (0x58) /* D-PHY AC characteristic register1 */
+
+/* DSIM_STATUS */
+#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
+#define DSIM_STOP_STATE_CLK (1 << 8)
+#define DSIM_TX_READY_HS_CLK (1 << 10)
+
+/* DSIM_SWRST */
+#define DSIM_FUNCRST (1 << 16)
+#define DSIM_SWRST (1 << 0)
+
+/* S5P_DSIM_TIMEOUT */
+#define DSIM_LPDR_TOUT_SHIFT (0)
+#define DSIM_BTA_TOUT_SHIFT (16)
+
+/* S5P_DSIM_CLKCTRL */
+#define DSIM_LANE_ESC_CLKEN_SHIFT (19)
+#define DSIM_BYTE_CLKEN_SHIFT (24)
+#define DSIM_BYTE_CLK_SRC_SHIFT (25)
+#define DSIM_PLL_BYPASS_SHIFT (27)
+#define DSIM_ESC_CLKEN_SHIFT (28)
+#define DSIM_TX_REQUEST_HSCLK_SHIFT (31)
+#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \
+ DSIM_LANE_ESC_CLKEN_SHIFT)
+#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT)
+#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT)
+#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT)
+#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT)
+#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT)
+
+/* S5P_DSIM_CONFIG */
+#define DSIM_NUM_OF_DATALANE_SHIFT (5)
+#define DSIM_HSA_MODE_SHIFT (20)
+#define DSIM_HBP_MODE_SHIFT (21)
+#define DSIM_HFP_MODE_SHIFT (22)
+#define DSIM_HSE_MODE_SHIFT (23)
+#define DSIM_AUTO_MODE_SHIFT (24)
+#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0)
+
+#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT)
+
+/* S5P_DSIM_ESCMODE */
+#define DSIM_TX_LPDT_SHIFT (6)
+#define DSIM_CMD_LPDT_SHIFT (7)
+#define DSIM_TX_LPDT_LP (1 << DSIM_TX_LPDT_SHIFT)
+#define DSIM_CMD_LPDT_LP (1 << DSIM_CMD_LPDT_SHIFT)
+#define DSIM_STOP_STATE_CNT_SHIFT (21)
+#define DSIM_FORCE_STOP_STATE_SHIFT (20)
+
+/* S5P_DSIM_MDRESOL */
+#define DSIM_MAIN_STAND_BY (1 << 31)
+#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
+#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
+
+/* S5P_DSIM_MVPORCH */
+#define DSIM_CMD_ALLOW_SHIFT (28)
+#define DSIM_STABLE_VFP_SHIFT (16)
+#define DSIM_MAIN_VBP_SHIFT (0)
+#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT)
+#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT)
+#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT)
+
+/* S5P_DSIM_MHPORCH */
+#define DSIM_MAIN_HFP_SHIFT (16)
+#define DSIM_MAIN_HBP_SHIFT (0)
+#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT)
+#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT)
+
+/* S5P_DSIM_MSYNC */
+#define DSIM_MAIN_VSA_SHIFT (22)
+#define DSIM_MAIN_HSA_SHIFT (0)
+#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT)
+#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT)
+
+/* S5P_DSIM_SDRESOL */
+#define DSIM_SUB_STANDY_SHIFT (31)
+#define DSIM_SUB_VRESOL_SHIFT (16)
+#define DSIM_SUB_HRESOL_SHIFT (0)
+#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT)
+#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT)
+#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT)
+
+/* S5P_DSIM_INTSRC */
+#define INTSRC_FRAME_DONE (1 << 24)
+#define INTSRC_PLL_STABLE (1 << 31)
+
+/* S5P_DSIM_INTMSK */
+#define INTMSK_FIFO_EMPTY (1 << 29)
+#define INTMSK_BTA (1 << 25)
+#define INTMSK_FRAME_DONE (1 << 24)
+#define INTMSK_RX_TIMEOUT (1 << 21)
+#define INTMSK_BTA_TIMEOUT (1 << 20)
+#define INTMSK_RX_DONE (1 << 18)
+#define INTMSK_RX_TE (1 << 17)
+#define INTMSK_RX_ACK (1 << 16)
+#define INTMSK_RX_ECC_ERR (1 << 15)
+#define INTMSK_RX_CRC_ERR (1 << 14)
+
+/* S5P_DSIM_FIFOCTRL */
+#define SFR_HEADER_EMPTY (1 << 22)
+
+/* S5P_DSIM_PHYACCHR */
+#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
+
+/* S5P_DSIM_PLLCTRL */
+#define DSIM_PLL_EN_SHIFT (23)
+#define DSIM_FREQ_BAND_SHIFT (24)
+
+#endif /* _REGS_DSIM_H */
diff --git a/include/linux/mipi_dsim.h b/include/linux/mipi_dsim.h
new file mode 100644
index 0000000..82807f2
--- /dev/null
+++ b/include/linux/mipi_dsim.h
@@ -0,0 +1,362 @@
+/* include/linux/mipi_dsim.h
+ *
+ * Platform data header for Samsung SoC MIPI-DSIM.
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ *
+ * InKi Dae <inki.dae@samsung.com>
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _LINUX_MIPI_DSIM_H
+#define _LINUX_MIPI_DSIM_H
+
+#include <linux/device.h>
+#include <linux/fb.h>
+
+#define PANEL_NAME_SIZE (32)
+
+/*
+ * enumurate display interface type.
+ *
+ * DSIM_COMMAND means cpu interface and rgb interface for DSIM_VIDEO.
+ *
+ * P.S. MIPI DSI Master has two display controller intefaces, RGB Interface
+ * for main display and CPU Interface(same as I80 Interface) for main
+ * and sub display.
+ */
+enum mipi_dsim_interface_type {
+ DSIM_COMMAND,
+ DSIM_VIDEO
+};
+
+enum mipi_dsim_virtual_ch_no {
+ DSIM_VIRTUAL_CH_0,
+ DSIM_VIRTUAL_CH_1,
+ DSIM_VIRTUAL_CH_2,
+ DSIM_VIRTUAL_CH_3
+};
+
+enum mipi_dsim_burst_mode_type {
+ DSIM_NON_BURST_SYNC_EVENT,
+ DSIM_BURST_SYNC_EVENT,
+ DSIM_NON_BURST_SYNC_PULSE,
+ DSIM_BURST,
+ DSIM_NON_VIDEO_MODE
+};
+
+enum mipi_dsim_no_of_data_lane {
+ DSIM_DATA_LANE_1,
+ DSIM_DATA_LANE_2,
+ DSIM_DATA_LANE_3,
+ DSIM_DATA_LANE_4
+};
+
+enum mipi_dsim_byte_clk_src {
+ DSIM_PLL_OUT_DIV8,
+ DSIM_EXT_CLK_DIV8,
+ DSIM_EXT_CLK_BYPASS
+};
+
+enum mipi_dsim_pixel_format {
+ DSIM_CMD_3BPP,
+ DSIM_CMD_8BPP,
+ DSIM_CMD_12BPP,
+ DSIM_CMD_16BPP,
+ DSIM_VID_16BPP_565,
+ DSIM_VID_18BPP_666PACKED,
+ DSIM_18BPP_666LOOSELYPACKED,
+ DSIM_24BPP_888
+};
+
+/*
+ * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
+ *
+ * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
+ * @eot_disable: enable or disable EoT packet in HS mode.
+ * @auto_vertical_cnt: specifies auto vertical count mode.
+ * in Video mode, the vertical line transition uses line counter
+ * configured by VSA, VBP, and Vertical resolution.
+ * If this bit is set to '1', the line counter does not use VSA and VBP
+ * registers.(in command mode, this variable is ignored)
+ * @hse: set horizontal sync event mode.
+ * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
+ * start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
+ * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
+ * (in mommand mode, this variable is ignored)
+ * @hfp: specifies HFP disable mode.
+ * if this variable is set, DSI master ignores HFP area in VIDEO mode.
+ * (in command mode, this variable is ignored)
+ * @hbp: specifies HBP disable mode.
+ * if this variable is set, DSI master ignores HBP area in VIDEO mode.
+ * (in command mode, this variable is ignored)
+ * @hsa: specifies HSA disable mode.
+ * if this variable is set, DSI master ignores HSA area in VIDEO mode.
+ * (in command mode, this variable is ignored)
+ * @cma_allow: specifies the number of horizontal lines, where command packet
+ * transmission is allowed after Stable VFP period.
+ * @e_interface: specifies interface to be used.(CPU or RGB interface)
+ * @e_virtual_ch: specifies virtual channel number that main or
+ * sub diaplsy uses.
+ * @e_pixel_format: specifies pixel stream format for main or sub display.
+ * @e_burst_mode: selects Burst mode in Video mode.
+ * in Non-burst mode, RGB data area is filled with RGB data and NULL
+ * packets, according to input bandwidth of RGB interface.
+ * In Burst mode, RGB data area is filled with RGB data only.
+ * @e_no_data_lane: specifies data lane count to be used by Master.
+ * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
+ * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
+ * @pll_stable_time: specifies the PLL Timer for stability of the ganerated
+ * clock(System clock cycle base)
+ * if the timer value goes to 0x00000000, the clock stable bit of status
+ * and interrupt register is set.
+ * @esc_clk: specifies escape clock frequency for getting the escape clock
+ * prescaler value.
+ * @stop_holding_cnt: specifies the interval value between transmitting
+ * read packet(or write "set_tear_on" command) and BTA request.
+ * after transmitting read packet or write "set_tear_on" command,
+ * BTA requests to D-PHY automatically. this counter value specifies
+ * the interval between them.
+ * @bta_timeout: specifies the timer for BTA.
+ * this register specifies time out from BTA request to change
+ * the direction with respect to Tx escape clock.
+ * @rx_timeout: specifies the timer for LP Rx mode timeout.
+ * this register specifies time out on how long RxValid deasserts,
+ * after RxLpdt asserts with respect to Tx escape clock.
+ * - RxValid specifies Rx data valid indicator.
+ * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
+ * - RxValid and RxLpdt specifies signal from D-PHY.
+ */
+struct mipi_dsim_config {
+ unsigned char auto_flush;
+ unsigned char eot_disable;
+
+ unsigned char auto_vertical_cnt;
+ unsigned char hse;
+ unsigned char hfp;
+ unsigned char hbp;
+ unsigned char hsa;
+ unsigned char cmd_allow;
+
+ enum mipi_dsim_interface_type e_interface;
+ enum mipi_dsim_virtual_ch_no e_virtual_ch;
+ enum mipi_dsim_pixel_format e_pixel_format;
+ enum mipi_dsim_burst_mode_type e_burst_mode;
+ enum mipi_dsim_no_of_data_lane e_no_data_lane;
+ enum mipi_dsim_byte_clk_src e_byte_clk;
+
+ /*
+ * =====================+ * | P | M | S | MHz |
+ * -------------------------------------------
+ * | 3 | 100 | 3 | 100 |
+ * | 3 | 100 | 2 | 200 |
+ * | 3 | 63 | 1 | 252 |
+ * | 4 | 100 | 1 | 300 |
+ * | 4 | 110 | 1 | 330 |
+ * | 12 | 350 | 1 | 350 |
+ * | 3 | 100 | 1 | 400 |
+ * | 4 | 150 | 1 | 450 |
+ * | 6 | 118 | 1 | 472 |
+ * | 3 | 120 | 1 | 480 |
+ * | 12 | 250 | 0 | 500 |
+ * | 4 | 100 | 0 | 600 |
+ * | 3 | 81 | 0 | 648 |
+ * | 3 | 88 | 0 | 704 |
+ * | 3 | 90 | 0 | 720 |
+ * | 3 | 100 | 0 | 800 |
+ * | 12 | 425 | 0 | 850 |
+ * | 4 | 150 | 0 | 900 |
+ * | 12 | 475 | 0 | 950 |
+ * | 6 | 250 | 0 | 1000 |
+ * -------------------------------------------
+ */
+
+ /*
+ * pms could be calculated as the following.
+ * M * 24 / P * 2 ^ S = MHz
+ */
+ unsigned char p;
+ unsigned short m;
+ unsigned char s;
+
+ unsigned int pll_stable_time;
+ unsigned long esc_clk;
+
+ unsigned short stop_holding_cnt;
+ unsigned char bta_timeout;
+ unsigned short rx_timeout;
+};
+
+/*
+ * struct mipi_dsim_device - global interface for mipi-dsi driver.
+ *
+ * @dev: driver model representation of the device.
+ * @id: unique device id.
+ * @clock: pointer to MIPI-DSI clock of clock framework.
+ * @irq: interrupt number to MIPI-DSI controller.
+ * @reg_base: base address to memory mapped SRF of MIPI-DSI controller.
+ * (virtual address)
+ * @lock: the mutex protecting this data structure.
+ * @dsim_info: infomation for configuring mipi-dsi controller.
+ * @master_ops: callbacks to mipi-dsi operations.
+ * @dsim_lcd_dev: pointer to activated ddi device.
+ * (it would be registered by mipi-dsi driver.)
+ * @dsim_lcd_drv: pointer to activated_ddi driver.
+ * (it would be registered by mipi-dsi driver.)
+ * @lcd_info: pointer to mipi_lcd_info structure.
+ * @power_t: current power status.
+ * @state: specifies status of MIPI-DSI controller.
+ * the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
+ * @data_lane: specifiec enabled data lane number.
+ * this variable would be set by driver according to e_no_data_lane
+ * automatically.
+ * @e_clk_src: select byte clock source.
+ * @pd: pointer to MIPI-DSI driver platform data.
+ */
+struct mipi_dsim_device {
+ struct device *dev;
+ int id;
+ struct resource *res;
+ struct clk *clock;
+ unsigned int irq;
+ void __iomem *reg_base;
+ struct mutex lock;
+
+ struct mipi_dsim_config *dsim_config;
+ struct mipi_dsim_master_ops *master_ops;
+ struct mipi_dsim_lcd_device *dsim_lcd_dev;
+ struct mipi_dsim_lcd_driver *dsim_lcd_drv;
+
+ atomic_t power_t;
+ unsigned int state;
+ unsigned int data_lane;
+ unsigned int e_clk_src;
+
+ struct mipi_dsim_platform_data *pd;
+};
+
+/*
+ * struct mipi_dsim_platform_data - interface to platform data
+ * for mipi-dsi driver.
+ *
+ * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
+ * lcd panel driver searched would be actived.
+ * @dsim_config: pointer of structure for configuring mipi-dsi controller.
+ * @enabled: indicate whether mipi controller got enabled or not.
+ * @lcd_panel_info: pointer for lcd panel specific structure.
+ * this structure specifies width, height, timing and polarity and so on.
+ * @mipi_power: callback pointer for enabling or disabling mipi power.
+ * @phy_enable: pointer to a callback controlling D-PHY enable/reset
+ */
+struct mipi_dsim_platform_data {
+ char lcd_panel_name[PANEL_NAME_SIZE];
+
+ struct mipi_dsim_config *dsim_config;
+ unsigned int enabled;
+ void *lcd_panel_info;
+
+ int (*mipi_power)(struct platform_device *pdev, unsigned int enable);
+ int (*phy_enable)(struct platform_device *pdev, bool on);
+};
+
+/*
+ * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations.
+ *
+ * @cmd_write: transfer command to lcd panel at LP mode.
+ * @cmd_read: read command from rx register.
+ * @get_dsim_frame_done: get the status that all screen data have been
+ * transferred to mipi-dsi.
+ * @clear_dsim_frame_done: clear frame done status.
+ * @get_fb_frame_done: get frame done status of display controller.
+ * @trigger: trigger display controller.
+ * - this one would be used only in case of CPU mode.
+ * @set_early_blank_mode: set framebuffer blank mode.
+ * - this callback should be called prior to fb_blank() by a client driver
+ * only if needing.
+ * @set_blank_mode: set framebuffer blank mode.
+ * - this callback should be called after fb_blank() by a client driver
+ * only if needing.
+ */
+
+struct mipi_dsim_master_ops {
+ int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
+ unsigned int data0, unsigned int data1);
+ int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
+ unsigned int data0, unsigned int req_size, u8 *rx_buf);
+ int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
+ int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
+
+ int (*get_fb_frame_done)(struct fb_info *info);
+ void (*trigger)(struct fb_info *info);
+ int (*set_early_blank_mode)(struct mipi_dsim_device *dsim, int power);
+ int (*set_blank_mode)(struct mipi_dsim_device *dsim, int power);
+};
+
+/*
+ * device structure for mipi-dsi based lcd panel.
+ *
+ * @name: name of the device to use with this device, or an
+ * alias for that name.
+ * @dev: driver model representation of the device.
+ * @id: id of device to be registered.
+ * @bus_id: bus id for identifing connected bus
+ * and this bus id should be same as id of mipi_dsim_device.
+ * @irq: irq number for signaling when framebuffer transfer of
+ * lcd panel module is completed.
+ * this irq would be used only for MIPI-DSI based CPU mode lcd panel.
+ * @master: pointer to mipi-dsi master device object.
+ * @platform_data: lcd panel specific platform data.
+ */
+struct mipi_dsim_lcd_device {
+ char *name;
+ struct device dev;
+ int id;
+ int bus_id;
+ int irq;
+
+ struct mipi_dsim_device *master;
+ void *platform_data;
+};
+
+/*
+ * driver structure for mipi-dsi based lcd panel.
+ *
+ * this structure should be registered by lcd panel driver.
+ * mipi-dsi driver seeks lcd panel registered through name field
+ * and calls these callback functions in appropriate time.
+ *
+ * @name: name of the driver to use with this device, or an
+ * alias for that name.
+ * @id: id of driver to be registered.
+ * this id would be used for finding device object registered.
+ */
+struct mipi_dsim_lcd_driver {
+ char *name;
+ int id;
+
+ void (*power_on)(struct mipi_dsim_lcd_device *dsim_dev);
+ void (*set_sequence)(struct mipi_dsim_lcd_device *dsim_dev);
+ int (*probe)(struct mipi_dsim_lcd_device *dsim_dev);
+ int (*remove)(struct mipi_dsim_lcd_device *dsim_dev);
+ void (*shutdown)(struct mipi_dsim_lcd_device *dsim_dev);
+ int (*suspend)(struct mipi_dsim_lcd_device *dsim_dev);
+ int (*resume)(struct mipi_dsim_lcd_device *dsim_dev);
+};
+
+/*
+ * register mipi_dsim_lcd_device to mipi-dsi master.
+ */
+int s5p_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
+ *lcd_dev);
+/**
+ * register mipi_dsim_lcd_driver object defined by lcd panel driver
+ * to mipi-dsi driver.
+ */
+int s5p_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
+ *lcd_drv);
+#endif /* _LINUX_MIPI_DSIM_H */
--
1.7.4.1
^ permalink raw reply related
* [PATCH] video:da8xx-fb: Disable and reset sequence on version2 of LCDC
From: Manjunathappa, Prakash @ 2011-11-15 12:14 UTC (permalink / raw)
To: linux-fbdev
Patch follows the disable and software reset sequence specified
in version2 to LCDC functional specification.
Without this flicker is observed on re-enabling the LCDC.
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
---
drivers/video/da8xx-fb.c | 15 ++++++++++++++-
1 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index e111971..6b27751 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -118,6 +118,7 @@
/* Clock registers available only on Version 2 */
#define LCD_CLK_ENABLE_REG 0x6c
#define LCD_CLK_RESET_REG 0x70
+#define LCD_CLK_MAIN_RESET BIT(3)
#define LCD_NUM_BUFFERS 2
@@ -246,6 +247,10 @@ static inline void lcd_enable_raster(void)
{
u32 reg;
+ /* Bring LCDC out of reset */
+ if (lcd_revision = LCD_VERSION_2)
+ lcdc_write(0, LCD_CLK_RESET_REG);
+
reg = lcdc_read(LCD_RASTER_CTRL_REG);
if (!(reg & LCD_RASTER_ENABLE))
lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
@@ -259,6 +264,10 @@ static inline void lcd_disable_raster(void)
reg = lcdc_read(LCD_RASTER_CTRL_REG);
if (reg & LCD_RASTER_ENABLE)
lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
+
+ if (lcd_revision = LCD_VERSION_2)
+ /* Write 1 to reset LCDC */
+ lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
}
static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
@@ -618,8 +627,12 @@ static void lcd_reset(struct da8xx_fb_par *par)
lcdc_write(0, LCD_DMA_CTRL_REG);
lcdc_write(0, LCD_RASTER_CTRL_REG);
- if (lcd_revision = LCD_VERSION_2)
+ if (lcd_revision = LCD_VERSION_2) {
lcdc_write(0, LCD_INT_ENABLE_SET_REG);
+ /* Write 1 to reset */
+ lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
+ lcdc_write(0, LCD_CLK_RESET_REG);
+ }
}
static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
--
1.7.1
^ permalink raw reply related
* [PATCH] video:da8xx-fb: Add 24bpp LCD configuration support
From: Manjunathappa, Prakash @ 2011-11-15 12:13 UTC (permalink / raw)
To: linux-fbdev
LCD controller on am335x supports 24bpp raster configuration
in addition to ones on da850. LCDC also supports 24bpp in unpacked
format having ARGB:8888 32bpp format data in DDR, but it doesn't
interpret Alpha component of the data.
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
---
drivers/video/da8xx-fb.c | 57 +++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 56 insertions(+), 1 deletions(-)
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 55f91d9..e111971 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -82,6 +82,8 @@
#define LCD_V2_LIDD_CLK_EN BIT(1)
#define LCD_V2_CORE_CLK_EN BIT(0)
#define LCD_V2_LPP_B10 26
+#define LCD_V2_TFT_24BPP_MODE BIT(25)
+#define LCD_V2_TFT_24BPP_UNPACK BIT(26)
/* LCD Raster Timing 2 Register */
#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
@@ -151,7 +153,7 @@ struct da8xx_fb_par {
unsigned int dma_end;
struct clk *lcdc_clk;
int irq;
- unsigned short pseudo_palette[16];
+ unsigned short pseudo_palette[32];
unsigned int palette_sz;
unsigned int pxl_clk;
int blank;
@@ -458,6 +460,9 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
{
u32 reg;
+ if ((bpp > 16) && (lcd_revision = LCD_VERSION_1))
+ return -EINVAL;
+
/* Set the Panel Width */
/* Pixels per line = (PPL + 1)*16 */
if (lcd_revision = LCD_VERSION_1) {
@@ -501,6 +506,13 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
if (raster_order)
reg |= LCD_RASTER_ORDER;
+
+ if (bpp = 24)
+ reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
+ else if (bpp = 32)
+ reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
+ | LCD_V2_TFT_24BPP_UNPACK);
+
lcdc_write(reg, LCD_RASTER_CTRL_REG);
switch (bpp) {
@@ -508,6 +520,8 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
case 2:
case 4:
case 16:
+ case 24:
+ case 32:
par->palette_sz = 16 * 2;
break;
@@ -537,6 +551,9 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
if (info->fix.visual = FB_VISUAL_DIRECTCOLOR)
return 1;
+ if ((info->var.bits_per_pixel > 16) && (lcd_revision = LCD_VERSION_1))
+ return 1;
+
if (info->var.bits_per_pixel = 8) {
red >>= 4;
green >>= 8;
@@ -566,6 +583,23 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
update_hw = 1;
palette[0] = 0x4000;
}
+ } else if (((info->var.bits_per_pixel = 32) && regno < 32) ||
+ ((info->var.bits_per_pixel = 24) && regno < 24)) {
+ red >>= (24 - info->var.red.length);
+ red <<= info->var.red.offset;
+
+ green >>= (24 - info->var.green.length);
+ green <<= info->var.green.offset;
+
+ blue >>= (24 - info->var.blue.length);
+ blue <<= info->var.blue.offset;
+
+ par->pseudo_palette[regno] = red | green | blue;
+
+ if (palette[0] != 0x4000) {
+ update_hw = 1;
+ palette[0] = 0x4000;
+ }
}
/* Update the palette in the h/w as needed. */
@@ -777,6 +811,9 @@ static int fb_check_var(struct fb_var_screeninfo *var,
{
int err = 0;
+ if ((var->bits_per_pixel > 16) && (lcd_revision = LCD_VERSION_1))
+ return -EINVAL;
+
switch (var->bits_per_pixel) {
case 1:
case 8:
@@ -809,6 +846,24 @@ static int fb_check_var(struct fb_var_screeninfo *var,
var->transp.offset = 0;
var->transp.length = 0;
break;
+ case 24:
+ var->red.offset = 16;
+ var->red.length = 8;
+ var->green.offset = 8;
+ var->green.length = 8;
+ var->blue.offset = 0;
+ var->blue.length = 8;
+ break;
+ case 32:
+ var->transp.offset = 24;
+ var->transp.length = 8;
+ var->red.offset = 16;
+ var->red.length = 8;
+ var->green.offset = 8;
+ var->green.length = 8;
+ var->blue.offset = 0;
+ var->blue.length = 8;
+ break;
default:
err = -EINVAL;
}
--
1.7.1
^ permalink raw reply related
* Re: Getting FB to work in Console
From: D.J.J. Ring, Jr. @ 2011-11-14 23:38 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <CADO5RbhunU1X7mWwGDbVRc1FSPKBaLudAVav0TMkBoQ_1zp0Mw@mail.gmail.com>
Hello everyone,
I know this is a bit off topic, but I just ran the command groups in
my username mode.
It just shows my username as the only group.
But I tried to adduser username to the group video and it tells me
that my username is already a member of video. Likewise if I adduser
username to the group tty it says that I am already a member of the
group tty. Same thing with superuser account root. The command
groups when running as superuser shows only that I belong to the group
root.
Is there a package that allows me to see the supplementary groups and
manage them?
I'm running Debian Stable.
David
^ permalink raw reply
* [PATCH] fb: split out framebuffer initialization from allocation
From: Timur Tabi @ 2011-11-14 22:01 UTC (permalink / raw)
To: linux-fbdev
Introduce functions framebuffer_init() and framebuffer_cleanup() to allow
the initialization of a user-allocated fb_info object.
framebuffer_alloc() allows for appending a private data structure when it
allocates the fb_info object. However, a driver that registers multiple
framebuffers for one device may also need another private data structure
for the device itself. framebuffer_init() allows such drivers to store
the fb_info objects in the device-specific private data structure,
thereby simplifying memory allocation.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
drivers/video/fbsysfs.c | 45 +++++++++++++++++++++++++++++++++++++++------
include/linux/fb.h | 2 ++
2 files changed, 41 insertions(+), 6 deletions(-)
diff --git a/drivers/video/fbsysfs.c b/drivers/video/fbsysfs.c
index 67afa9c..77d1c83 100644
--- a/drivers/video/fbsysfs.c
+++ b/drivers/video/fbsysfs.c
@@ -24,6 +24,29 @@
#define FB_SYSFS_FLAG_ATTR 1
/**
+ * framebuffer_init - initialize a frame buffer info object
+ *
+ * @info: pointer to the fb_info object
+ * @dev: pointer to the device for this fb, this can be NULL
+ *
+ * Initializes a frame buffer info object. The object should be zeroed-out
+ * before calling this function, because only some fields are initialized.
+ *
+ * Use this function for fb_info objects that are not allocated via
+ * framebuffer_alloc(). The object must be cleaned up with
+ * framebuffer_cleanup() before its memory is deallocated.
+ */
+void framebuffer_init(struct fb_info *info, struct device *dev)
+{
+ info->device = dev;
+
+#ifdef CONFIG_FB_BACKLIGHT
+ mutex_init(&info->bl_curve_mutex);
+#endif
+}
+EXPORT_SYMBOL(framebuffer_init);
+
+/**
* framebuffer_alloc - creates a new frame buffer info structure
*
* @size: size of driver private data, can be zero
@@ -35,6 +58,7 @@
*
* Returns the new structure, or NULL if an error occurred.
*
+ * The object must be deallocated with framebuffer_release().
*/
struct fb_info *framebuffer_alloc(size_t size, struct device *dev)
{
@@ -57,11 +81,7 @@ struct fb_info *framebuffer_alloc(size_t size, struct device *dev)
if (size)
info->par = p + fb_info_size;
- info->device = dev;
-
-#ifdef CONFIG_FB_BACKLIGHT
- mutex_init(&info->bl_curve_mutex);
-#endif
+ framebuffer_init(info, dev);
return info;
#undef PADDING
@@ -70,6 +90,19 @@ struct fb_info *framebuffer_alloc(size_t size, struct device *dev)
EXPORT_SYMBOL(framebuffer_alloc);
/**
+ * framebuffer_cleanup - cleans up a frame buffer info object
+ *
+ * @info: frame buffer info object
+ *
+ * Cleans up an fb_info object that was initialized with framebuffer_init().
+ */
+void framebuffer_cleanup(struct fb_info *info)
+{
+ kfree(info->apertures);
+}
+EXPORT_SYMBOL(framebuffer_cleanup);
+
+/**
* framebuffer_release - marks the structure available for freeing
*
* @info: frame buffer info structure
@@ -80,7 +113,7 @@ EXPORT_SYMBOL(framebuffer_alloc);
*/
void framebuffer_release(struct fb_info *info)
{
- kfree(info->apertures);
+ framebuffer_cleanup(info);
kfree(info);
}
EXPORT_SYMBOL(framebuffer_release);
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 1d6836c..c2347fb 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -1068,6 +1068,8 @@ static inline bool fb_be_math(struct fb_info *info)
/* drivers/video/fbsysfs.c */
extern struct fb_info *framebuffer_alloc(size_t size, struct device *dev);
extern void framebuffer_release(struct fb_info *info);
+extern void framebuffer_init(struct fb_info *info, struct device *dev);
+extern void framebuffer_cleanup(struct fb_info *info);
extern int fb_init_device(struct fb_info *fb_info);
extern void fb_cleanup_device(struct fb_info *head);
extern void fb_bl_default_curve(struct fb_info *fb_info, u8 off, u8 min, u8 max);
--
1.7.3.4
^ permalink raw reply related
* Re: Getting FB to work in Console
From: David J Ring Jr @ 2011-11-14 21:50 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <CADO5RbhunU1X7mWwGDbVRc1FSPKBaLudAVav0TMkBoQ_1zp0Mw@mail.gmail.com>
[-- Attachment #1: Type: TEXT/PLAIN, Size: 71306 bytes --]
Hello Bruno and Anatolij -- and everyone who is helping or reading!
Anatolij, I forgot to say I did run sudo update-grub, but still no
framebuffer.
Bruno, there is nothing in GRUB when I edit the commandline that has
anythhing to do with video or nomodeset.
Here is my kernel log for the last boot.
I am using a USB stick only - it is /dev/sda and it has / on /dev/sda1 and
/home on /dev/sda2
Nov 14 21:30:57 vinux kernel: imklog 4.6.4, log source = /proc/kmsg started.
Nov 14 21:30:57 vinux kernel: [ 0.000000] Initializing cgroup subsys cpuset
Nov 14 21:30:57 vinux kernel: [ 0.000000] Initializing cgroup subsys cpu
Nov 14 21:30:57 vinux kernel: [ 0.000000] Linux version 2.6.32-5-686 (Debian 2.6.32-38) (ben@decadent.org.uk) (gcc version 4.3.5 (Debian 4.3.5-4) ) #1 SMP Mon Oct 3 04:15:24 UTC 2011
Nov 14 21:30:57 vinux kernel: [ 0.000000] KERNEL supported cpus:
Nov 14 21:30:57 vinux kernel: [ 0.000000] Intel GenuineIntel
Nov 14 21:30:57 vinux kernel: [ 0.000000] AMD AuthenticAMD
Nov 14 21:30:57 vinux kernel: [ 0.000000] NSC Geode by NSC
Nov 14 21:30:57 vinux kernel: [ 0.000000] Cyrix CyrixInstead
Nov 14 21:30:57 vinux kernel: [ 0.000000] Centaur CentaurHauls
Nov 14 21:30:57 vinux kernel: [ 0.000000] Transmeta GenuineTMx86
Nov 14 21:30:57 vinux kernel: [ 0.000000] Transmeta TransmetaCPU
Nov 14 21:30:57 vinux kernel: [ 0.000000] UMC UMC UMC UMC
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-provided physical RAM map:
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009f400 (usable)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 000000000009f400 - 00000000000a0000 (reserved)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000000d2000 - 00000000000d4000 (reserved)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000000dc000 - 0000000000100000 (reserved)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 0000000000100000 - 00000000bd6b3000 (usable)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000bd6b3000 - 00000000bd6b9000 (reserved)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000bd6b9000 - 00000000bd7b2000 (usable)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000bd7b2000 - 00000000bd80f000 (reserved)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000bd80f000 - 00000000bd907000 (usable)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000bd907000 - 00000000bdb0f000 (reserved)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000bdb0f000 - 00000000bdb18000 (usable)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000bdb18000 - 00000000bdb1f000 (reserved)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000bdb1f000 - 00000000bdb63000 (usable)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000bdb63000 - 00000000bdb9f000 (ACPI NVS)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 00000000bdb9f000 - 00000000bdc00000 (ACPI data)
Nov 14 21:30:57 vinux kernel: [ 0.000000] BIOS-e820: 0000000100000000 - 0000000140000000 (usable)
Nov 14 21:30:57 vinux kernel: [ 0.000000] DMI present.
Nov 14 21:30:57 vinux kernel: [ 0.000000] last_pfn = 0xbdb63 max_arch_pfn = 0x100000
Nov 14 21:30:57 vinux kernel: [ 0.000000] MTRR default type: uncachable
Nov 14 21:30:57 vinux kernel: [ 0.000000] MTRR fixed ranges enabled:
Nov 14 21:30:57 vinux kernel: [ 0.000000] 00000-9FFFF write-back
Nov 14 21:30:57 vinux kernel: [ 0.000000] A0000-BFFFF uncachable
Nov 14 21:30:57 vinux kernel: [ 0.000000] C0000-FFFFF write-protect
Nov 14 21:30:57 vinux kernel: [ 0.000000] MTRR variable ranges enabled:
Nov 14 21:30:57 vinux kernel: [ 0.000000] 0 base 0C0000000 mask FC0000000 uncachable
Nov 14 21:30:57 vinux kernel: [ 0.000000] 1 base 000000000 mask F00000000 write-back
Nov 14 21:30:57 vinux kernel: [ 0.000000] 2 base 100000000 mask FC0000000 write-back
Nov 14 21:30:57 vinux kernel: [ 0.000000] 3 base 0BDC00000 mask FFFC00000 uncachable
Nov 14 21:30:57 vinux kernel: [ 0.000000] 4 disabled
Nov 14 21:30:57 vinux kernel: [ 0.000000] 5 disabled
Nov 14 21:30:57 vinux kernel: [ 0.000000] 6 disabled
Nov 14 21:30:57 vinux kernel: [ 0.000000] 7 disabled
Nov 14 21:30:57 vinux kernel: [ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
Nov 14 21:30:57 vinux kernel: [ 0.000000] e820 update range: 00000000bdc00000 - 00000000be000000 (usable) ==> (reserved)
Nov 14 21:30:57 vinux kernel: [ 0.000000] e820 update range: 00000000c0000000 - 0000000100000000 (usable) ==> (reserved)
Nov 14 21:30:57 vinux kernel: [ 0.000000] initial memory mapped : 0 - 01800000
Nov 14 21:30:57 vinux kernel: [ 0.000000] init_memory_mapping: 0000000000000000-00000000373fe000
Nov 14 21:30:57 vinux kernel: [ 0.000000] 0000000000 - 0000400000 page 4k
Nov 14 21:30:57 vinux kernel: [ 0.000000] 0000400000 - 0037000000 page 2M
Nov 14 21:30:57 vinux kernel: [ 0.000000] 0037000000 - 00373fe000 page 4k
Nov 14 21:30:57 vinux kernel: [ 0.000000] kernel direct mapping tables up to 373fe000 @ 7000-d000
Nov 14 21:30:57 vinux kernel: [ 0.000000] RAMDISK: 3759a000 - 37fef5a8
Nov 14 21:30:57 vinux kernel: [ 0.000000] Allocated new RAMDISK: 00100000 - 00b555a8
Nov 14 21:30:57 vinux kernel: [ 0.000000] Move RAMDISK from 000000003759a000 - 0000000037fef5a7 to 00100000 - 00b555a7
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: RSDP 000f7190 00024 (v02 LENOVO)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: XSDT bdbf6067 0006C (v01 LENOVO TP-6G 00000000 LTP 00000000)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: FACP bdbe8000 000F4 (v03 LENOVO TP-6G 00000001 ALAN 00000001)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: DSDT bdbe9000 06B23 (v02 LENOVO TP-6G 00000001 INTL 20050624)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: FACS bdb9efc0 00040
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: HPET bdbfcd86 00038 (v01 LENOVO TP-6G 00000001 LOHR 0000005A)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: MCFG bdbfcdbe 0003C (v01 LENOVO TP-6G 00000001 LOHR 0000005A)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: SLIC bdbfcdfa 00176 (v01 LENOVO TP-6G 00000001 TBD 00000001)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: APIC bdbfcf70 00068 (v01 PTLTD ? APIC 00000000 LTP 00000000)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: BOOT bdbfcfd8 00028 (v01 PTLTD $SBFTBL$ 00000000 LTP 00000001)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: SSDT bdbe7000 00655 (v01 PmRef CpuPm 00003000 INTL 20050624)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: SSDT bdbe6000 00259 (v01 PmRef Cpu0Tst 00003000 INTL 20050624)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: SSDT bdbe5000 0020F (v01 PmRef ApTst 00003000 INTL 20050624)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000
Nov 14 21:30:57 vinux kernel: [ 0.000000] 2151MB HIGHMEM available.
Nov 14 21:30:57 vinux kernel: [ 0.000000] 883MB LOWMEM available.
Nov 14 21:30:57 vinux kernel: [ 0.000000] mapped low ram: 0 - 373fe000
Nov 14 21:30:57 vinux kernel: [ 0.000000] low ram: 0 - 373fe000
Nov 14 21:30:57 vinux kernel: [ 0.000000] node 0 low ram: 00000000 - 373fe000
Nov 14 21:30:57 vinux kernel: [ 0.000000] node 0 bootmap 00009000 - 0000fe80
Nov 14 21:30:57 vinux kernel: [ 0.000000] (9 early reservations) ==> bootmem [0000000000 - 00373fe000]
Nov 14 21:30:57 vinux kernel: [ 0.000000] #0 [0000000000 - 0000001000] BIOS data page ==> [0000000000 - 0000001000]
Nov 14 21:30:57 vinux kernel: [ 0.000000] #1 [0000001000 - 0000002000] EX TRAMPOLINE ==> [0000001000 - 0000002000]
Nov 14 21:30:57 vinux kernel: [ 0.000000] #2 [0000006000 - 0000007000] TRAMPOLINE ==> [0000006000 - 0000007000]
Nov 14 21:30:57 vinux kernel: [ 0.000000] #3 [0001000000 - 00014cccf4] TEXT DATA BSS ==> [0001000000 - 00014cccf4]
Nov 14 21:30:57 vinux kernel: [ 0.000000] #4 [000009f400 - 0000100000] BIOS reserved ==> [000009f400 - 0000100000]
Nov 14 21:30:57 vinux kernel: [ 0.000000] #5 [00014cd000 - 00014d3184] BRK ==> [00014cd000 - 00014d3184]
Nov 14 21:30:57 vinux kernel: [ 0.000000] #6 [0000007000 - 0000009000] PGTABLE ==> [0000007000 - 0000009000]
Nov 14 21:30:57 vinux kernel: [ 0.000000] #7 [0000100000 - 0000b555a8] NEW RAMDISK ==> [0000100000 - 0000b555a8]
Nov 14 21:30:57 vinux kernel: [ 0.000000] #8 [0000009000 - 0000010000] BOOTMAP ==> [0000009000 - 0000010000]
Nov 14 21:30:57 vinux kernel: [ 0.000000] found SMP MP-table at [c00f7230] f7230
Nov 14 21:30:57 vinux kernel: [ 0.000000] Zone PFN ranges:
Nov 14 21:30:57 vinux kernel: [ 0.000000] DMA 0x00000000 -> 0x00001000
Nov 14 21:30:57 vinux kernel: [ 0.000000] Normal 0x00001000 -> 0x000373fe
Nov 14 21:30:57 vinux kernel: [ 0.000000] HighMem 0x000373fe -> 0x000bdb63
Nov 14 21:30:57 vinux kernel: [ 0.000000] Movable zone start PFN for each node
Nov 14 21:30:57 vinux kernel: [ 0.000000] early_node_map[6] active PFN ranges
Nov 14 21:30:57 vinux kernel: [ 0.000000] 0: 0x00000000 -> 0x0000009f
Nov 14 21:30:57 vinux kernel: [ 0.000000] 0: 0x00000100 -> 0x000bd6b3
Nov 14 21:30:57 vinux kernel: [ 0.000000] 0: 0x000bd6b9 -> 0x000bd7b2
Nov 14 21:30:57 vinux kernel: [ 0.000000] 0: 0x000bd80f -> 0x000bd907
Nov 14 21:30:57 vinux kernel: [ 0.000000] 0: 0x000bdb0f -> 0x000bdb18
Nov 14 21:30:57 vinux kernel: [ 0.000000] 0: 0x000bdb1f -> 0x000bdb63
Nov 14 21:30:57 vinux kernel: [ 0.000000] On node 0 totalpages: 776336
Nov 14 21:30:57 vinux kernel: [ 0.000000] free_area_init_node: node 0, pgdat c13b4860, node_mem_map c14d5000
Nov 14 21:30:57 vinux kernel: [ 0.000000] DMA zone: 32 pages used for memmap
Nov 14 21:30:57 vinux kernel: [ 0.000000] DMA zone: 0 pages reserved
Nov 14 21:30:57 vinux kernel: [ 0.000000] DMA zone: 3967 pages, LIFO batch:0
Nov 14 21:30:57 vinux kernel: [ 0.000000] Normal zone: 1736 pages used for memmap
Nov 14 21:30:57 vinux kernel: [ 0.000000] Normal zone: 220470 pages, LIFO batch:31
Nov 14 21:30:57 vinux kernel: [ 0.000000] HighMem zone: 4303 pages used for memmap
Nov 14 21:30:57 vinux kernel: [ 0.000000] HighMem zone: 545828 pages, LIFO batch:31
Nov 14 21:30:57 vinux kernel: [ 0.000000] Using APIC driver default
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: PM-Timer IO Port: 0x408
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
Nov 14 21:30:57 vinux kernel: [ 0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 high edge)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: IRQ0 used by override.
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: IRQ2 used by override.
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: IRQ9 used by override.
Nov 14 21:30:57 vinux kernel: [ 0.000000] Using ACPI (MADT) for SMP configuration information
Nov 14 21:30:57 vinux kernel: [ 0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000
Nov 14 21:30:57 vinux kernel: [ 0.000000] SMP: Allowing 2 CPUs, 0 hotplug CPUs
Nov 14 21:30:57 vinux kernel: [ 0.000000] nr_irqs_gsi: 24
Nov 14 21:30:57 vinux kernel: [ 0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
Nov 14 21:30:57 vinux kernel: [ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000d2000
Nov 14 21:30:57 vinux kernel: [ 0.000000] PM: Registered nosave memory: 00000000000d2000 - 00000000000d4000
Nov 14 21:30:57 vinux kernel: [ 0.000000] PM: Registered nosave memory: 00000000000d4000 - 00000000000dc000
Nov 14 21:30:57 vinux kernel: [ 0.000000] PM: Registered nosave memory: 00000000000dc000 - 0000000000100000
Nov 14 21:30:57 vinux kernel: [ 0.000000] Allocating PCI resources starting at bdc00000 (gap: bdc00000:42400000)
Nov 14 21:30:57 vinux kernel: [ 0.000000] Booting paravirtualized kernel on bare hardware
Nov 14 21:30:57 vinux kernel: [ 0.000000] NR_CPUS:32 nr_cpumask_bits:32 nr_cpu_ids:2 nr_node_ids:1
Nov 14 21:30:57 vinux kernel: [ 0.000000] PERCPU: Embedded 14 pages/cpu @c3000000 s34328 r0 d23016 u2097152
Nov 14 21:30:57 vinux kernel: [ 0.000000] pcpu-alloc: s34328 r0 d23016 u2097152 alloc=1*4194304
Nov 14 21:30:57 vinux kernel: [ 0.000000] pcpu-alloc: [0] 0 1
Nov 14 21:30:57 vinux kernel: [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 770265
Nov 14 21:30:57 vinux kernel: [ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-2.6.32-5-686 root=UUID=cb1268f1-4e20-4409-87b1-3d882c14102c ro
Nov 14 21:30:57 vinux kernel: [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
Nov 14 21:30:57 vinux kernel: [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Nov 14 21:30:57 vinux kernel: [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Nov 14 21:30:57 vinux kernel: [ 0.000000] Enabling fast FPU save and restore... done.
Nov 14 21:30:57 vinux kernel: [ 0.000000] Enabling unmasked SIMD FPU exception support... done.
Nov 14 21:30:57 vinux kernel: [ 0.000000] Initializing CPU#0
Nov 14 21:30:57 vinux kernel: [ 0.000000] Initializing HighMem for node 0 (000373fe:000bdb63)
Nov 14 21:30:57 vinux kernel: [ 0.000000] Memory: 3063500k/3108236k available (2504k kernel code, 40824k reserved, 1328k data, 380k init, 2200524k highmem)
Nov 14 21:30:57 vinux kernel: [ 0.000000] virtual kernel memory layout:
Nov 14 21:30:57 vinux kernel: [ 0.000000] fixmap : 0xffd56000 - 0xfffff000 (2724 kB)
Nov 14 21:30:57 vinux kernel: [ 0.000000] pkmap : 0xff400000 - 0xff800000 (4096 kB)
Nov 14 21:30:57 vinux kernel: [ 0.000000] vmalloc : 0xf7bfe000 - 0xff3fe000 ( 120 MB)
Nov 14 21:30:57 vinux kernel: [ 0.000000] lowmem : 0xc0000000 - 0xf73fe000 ( 883 MB)
Nov 14 21:30:57 vinux kernel: [ 0.000000] .init : 0xc13bf000 - 0xc141e000 ( 380 kB)
Nov 14 21:30:57 vinux kernel: [ 0.000000] .data : 0xc12721f1 - 0xc13be480 (1328 kB)
Nov 14 21:30:57 vinux kernel: [ 0.000000] .text : 0xc1000000 - 0xc12721f1 (2504 kB)
Nov 14 21:30:57 vinux kernel: [ 0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok.
Nov 14 21:30:57 vinux kernel: [ 0.000000] SLUB: Genslabs=13, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Nov 14 21:30:57 vinux kernel: [ 0.000000] Hierarchical RCU implementation.
Nov 14 21:30:57 vinux kernel: [ 0.000000] NR_IRQS:1280
Nov 14 21:30:57 vinux kernel: [ 0.000000] Extended CMOS year: 2000
Nov 14 21:30:57 vinux kernel: [ 0.000000] Console: colour VGA+ 80x25
Nov 14 21:30:57 vinux kernel: [ 0.000000] console [tty0] enabled
Nov 14 21:30:57 vinux kernel: [ 0.000000] hpet clockevent registered
Nov 14 21:30:57 vinux kernel: [ 0.000000] Fast TSC calibration using PIT
Nov 14 21:30:57 vinux kernel: [ 0.000000] Detected 2161.220 MHz processor.
Nov 14 21:30:57 vinux kernel: [ 0.004004] Calibrating delay loop (skipped), value calculated using timer frequency.. 4322.44 BogoMIPS (lpj=8644880)
Nov 14 21:30:57 vinux kernel: [ 0.004139] Security Framework initialized
Nov 14 21:30:57 vinux kernel: [ 0.004202] SELinux: Disabled at boot.
Nov 14 21:30:57 vinux kernel: [ 0.004266] Mount-cache hash table entries: 512
Nov 14 21:30:57 vinux kernel: [ 0.004439] Initializing cgroup subsys ns
Nov 14 21:30:57 vinux kernel: [ 0.004501] Initializing cgroup subsys cpuacct
Nov 14 21:30:57 vinux kernel: [ 0.004563] Initializing cgroup subsys devices
Nov 14 21:30:57 vinux kernel: [ 0.004623] Initializing cgroup subsys freezer
Nov 14 21:30:57 vinux kernel: [ 0.004684] Initializing cgroup subsys net_cls
Nov 14 21:30:57 vinux kernel: [ 0.004765] CPU: L1 I cache: 32K, L1 D cache: 32K
Nov 14 21:30:57 vinux kernel: [ 0.004867] CPU: L2 cache: 1024K
Nov 14 21:30:57 vinux kernel: [ 0.004927] CPU: Physical Processor ID: 0
Nov 14 21:30:57 vinux kernel: [ 0.004986] CPU: Processor Core ID: 0
Nov 14 21:30:57 vinux kernel: [ 0.005048] mce: CPU supports 6 MCE banks
Nov 14 21:30:57 vinux kernel: [ 0.005114] CPU0: Thermal monitoring enabled (TM2)
Nov 14 21:30:57 vinux kernel: [ 0.005176] using mwait in idle threads.
Nov 14 21:30:57 vinux kernel: [ 0.005240] Performance Events: Core2 events, Intel PMU driver.
Nov 14 21:30:57 vinux kernel: [ 0.005389] ... version: 2
Nov 14 21:30:57 vinux kernel: [ 0.005448] ... bit width: 40
Nov 14 21:30:57 vinux kernel: [ 0.008005] ... generic registers: 2
Nov 14 21:30:57 vinux kernel: [ 0.008064] ... value mask: 000000ffffffffff
Nov 14 21:30:57 vinux kernel: [ 0.008126] ... max period: 000000007fffffff
Nov 14 21:30:57 vinux kernel: [ 0.008187] ... fixed-purpose events: 3
Nov 14 21:30:57 vinux kernel: [ 0.008247] ... event mask: 0000000700000003
Nov 14 21:30:57 vinux kernel: [ 0.008311] Checking 'hlt' instruction... OK.
Nov 14 21:30:57 vinux kernel: [ 0.025104] ACPI: Core revision 20090903
Nov 14 21:30:57 vinux kernel: [ 0.036059] Enabling APIC mode: Flat. Using 1 I/O APICs
Nov 14 21:30:57 vinux kernel: [ 0.036511] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
Nov 14 21:30:57 vinux kernel: [ 0.079757] CPU0: Intel(R) Pentium(R) Dual CPU T3400 @ 2.16GHz stepping 0d
Nov 14 21:30:57 vinux kernel: [ 0.080001] Booting processor 1 APIC 0x1 ip 0x6000
Nov 14 21:30:57 vinux kernel: [ 0.008000] Initializing CPU#1
Nov 14 21:30:57 vinux kernel: [ 0.008000] CPU: L1 I cache: 32K, L1 D cache: 32K
Nov 14 21:30:57 vinux kernel: [ 0.008000] CPU: L2 cache: 1024K
Nov 14 21:30:57 vinux kernel: [ 0.008000] CPU: Physical Processor ID: 0
Nov 14 21:30:57 vinux kernel: [ 0.008000] CPU: Processor Core ID: 1
Nov 14 21:30:57 vinux kernel: [ 0.008000] CPU1: Thermal monitoring enabled (TM2)
Nov 14 21:30:57 vinux kernel: [ 0.164086] CPU1: Intel(R) Pentium(R) Dual CPU T3400 @ 2.16GHz stepping 0d
Nov 14 21:30:57 vinux kernel: [ 0.164589] checking TSC synchronization [CPU#0 -> CPU#1]: passed.
Nov 14 21:30:57 vinux kernel: [ 0.168046] Brought up 2 CPUs
Nov 14 21:30:57 vinux kernel: [ 0.168106] Total of 2 processors activated (8644.94 BogoMIPS).
Nov 14 21:30:57 vinux kernel: [ 0.168738] CPU0 attaching sched-domain:
Nov 14 21:30:57 vinux kernel: [ 0.168742] domain 0: span 0-1 level MC
Nov 14 21:30:57 vinux kernel: [ 0.168744] groups: group c3003778 cpus 0 group c3203778 cpus 1
Nov 14 21:30:57 vinux kernel: [ 0.168750] CPU1 attaching sched-domain:
Nov 14 21:30:57 vinux kernel: [ 0.168752] domain 0: span 0-1 level MC
Nov 14 21:30:57 vinux kernel: [ 0.168754] groups: group c3203778 cpus 1 group c3003778 cpus 0
Nov 14 21:30:57 vinux kernel: [ 0.168804] devtmpfs: initialized
Nov 14 21:30:57 vinux kernel: [ 0.168804] regulator: core version 0.5
Nov 14 21:30:57 vinux kernel: [ 0.168804] NET: Registered protocol family 16
Nov 14 21:30:57 vinux kernel: [ 0.169011] ACPI: bus type pci registered
Nov 14 21:30:57 vinux kernel: [ 0.169133] PCI: MCFG configuration 0: base e0000000 segment 0 buses 0 - 255
Nov 14 21:30:57 vinux kernel: [ 0.169199] PCI: Not using MMCONFIG.
Nov 14 21:30:57 vinux kernel: [ 0.169699] PCI: PCI BIOS revision 3.00 entry at 0xfde11, last bus=8
Nov 14 21:30:57 vinux kernel: [ 0.169763] PCI: Using configuration type 1 for base access
Nov 14 21:30:57 vinux kernel: [ 0.172112] bio: create slab <bio-0> at 0
Nov 14 21:30:57 vinux kernel: [ 0.172806] ACPI: EC: Look up EC in DSDT
Nov 14 21:30:57 vinux kernel: [ 0.176261] ACPI: BIOS _OSI(Linux) query ignored
Nov 14 21:30:57 vinux kernel: [ 0.177657] ACPI: Interpreter enabled
Nov 14 21:30:57 vinux kernel: [ 0.177719] ACPI: (supports S0 S3 S4 S5)
Nov 14 21:30:57 vinux kernel: [ 0.177962] ACPI: Using IOAPIC for interrupt routing
Nov 14 21:30:57 vinux kernel: [ 0.178070] PCI: MCFG configuration 0: base e0000000 segment 0 buses 0 - 255
Nov 14 21:30:57 vinux kernel: [ 0.216431] PCI: MCFG area at e0000000 reserved in ACPI motherboard resources
Nov 14 21:30:57 vinux kernel: [ 0.216497] PCI: Using MMCONFIG for extended config space
Nov 14 21:30:57 vinux kernel: [ 0.258858] ACPI: EC: GPE = 0x1c, I/O: command/status = 0x66, data = 0x62
Nov 14 21:30:57 vinux kernel: [ 0.259221] ACPI: No dock devices found.
Nov 14 21:30:57 vinux kernel: [ 0.259753] ACPI: PCI Root Bridge [PCI0] (0000:00)
Nov 14 21:30:57 vinux kernel: [ 0.259867] DMAR: Forcing write-buffer flush capability
Nov 14 21:30:57 vinux kernel: [ 0.259929] DMAR: Disabling IOMMU for graphics on this chipset
Nov 14 21:30:57 vinux kernel: [ 0.260039] pci 0000:00:02.0: reg 10 64bit mmio: [0xf4000000-0xf43fffff]
Nov 14 21:30:57 vinux kernel: [ 0.260046] pci 0000:00:02.0: reg 18 64bit mmio pref: [0xd0000000-0xdfffffff]
Nov 14 21:30:57 vinux kernel: [ 0.260052] pci 0000:00:02.0: reg 20 io port: [0x1800-0x1807]
Nov 14 21:30:57 vinux kernel: [ 0.260093] pci 0000:00:02.1: reg 10 64bit mmio: [0xf4400000-0xf44fffff]
Nov 14 21:30:57 vinux kernel: [ 0.260222] pci 0000:00:1a.0: reg 20 io port: [0x1820-0x183f]
Nov 14 21:30:57 vinux kernel: [ 0.260320] pci 0000:00:1a.1: reg 20 io port: [0x1840-0x185f]
Nov 14 21:30:57 vinux kernel: [ 0.260417] pci 0000:00:1a.2: reg 20 io port: [0x1860-0x187f]
Nov 14 21:30:57 vinux kernel: [ 0.260515] pci 0000:00:1a.7: reg 10 32bit mmio: [0xf4a04800-0xf4a04bff]
Nov 14 21:30:57 vinux kernel: [ 0.260586] pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold
Nov 14 21:30:57 vinux kernel: [ 0.260653] pci 0000:00:1a.7: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.260770] pci 0000:00:1b.0: reg 10 64bit mmio: [0xf4a00000-0xf4a03fff]
Nov 14 21:30:57 vinux kernel: [ 0.260833] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
Nov 14 21:30:57 vinux kernel: [ 0.260899] pci 0000:00:1b.0: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.261055] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
Nov 14 21:30:57 vinux kernel: [ 0.261121] pci 0000:00:1c.0: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.261279] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold
Nov 14 21:30:57 vinux kernel: [ 0.261345] pci 0000:00:1c.1: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.261503] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold
Nov 14 21:30:57 vinux kernel: [ 0.261569] pci 0000:00:1c.2: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.261726] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
Nov 14 21:30:57 vinux kernel: [ 0.261792] pci 0000:00:1c.3: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.261951] pci 0000:00:1c.5: PME# supported from D0 D3hot D3cold
Nov 14 21:30:57 vinux kernel: [ 0.262018] pci 0000:00:1c.5: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.262157] pci 0000:00:1d.0: reg 20 io port: [0x1880-0x189f]
Nov 14 21:30:57 vinux kernel: [ 0.262254] pci 0000:00:1d.1: reg 20 io port: [0x18a0-0x18bf]
Nov 14 21:30:57 vinux kernel: [ 0.262352] pci 0000:00:1d.2: reg 20 io port: [0x18c0-0x18df]
Nov 14 21:30:57 vinux kernel: [ 0.262450] pci 0000:00:1d.7: reg 10 32bit mmio: [0xf4a04c00-0xf4a04fff]
Nov 14 21:30:57 vinux kernel: [ 0.262521] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
Nov 14 21:30:57 vinux kernel: [ 0.262588] pci 0000:00:1d.7: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.262916] pci 0000:00:1f.2: reg 10 io port: [0x1818-0x181f]
Nov 14 21:30:57 vinux kernel: [ 0.262924] pci 0000:00:1f.2: reg 14 io port: [0x180c-0x180f]
Nov 14 21:30:57 vinux kernel: [ 0.262932] pci 0000:00:1f.2: reg 18 io port: [0x1810-0x1817]
Nov 14 21:30:57 vinux kernel: [ 0.262940] pci 0000:00:1f.2: reg 1c io port: [0x1808-0x180b]
Nov 14 21:30:57 vinux kernel: [ 0.262948] pci 0000:00:1f.2: reg 20 io port: [0x18e0-0x18ff]
Nov 14 21:30:57 vinux kernel: [ 0.262956] pci 0000:00:1f.2: reg 24 32bit mmio: [0xf4a04000-0xf4a047ff]
Nov 14 21:30:57 vinux kernel: [ 0.263005] pci 0000:00:1f.2: PME# supported from D3hot
Nov 14 21:30:57 vinux kernel: [ 0.263070] pci 0000:00:1f.2: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.263172] pci 0000:00:1f.3: reg 10 64bit mmio: [0x000000-0x0000ff]
Nov 14 21:30:57 vinux kernel: [ 0.263192] pci 0000:00:1f.3: reg 20 io port: [0x1c00-0x1c1f]
Nov 14 21:30:57 vinux kernel: [ 0.263298] pci 0000:02:00.0: reg 10 32bit mmio: [0xf4500000-0xf45000ff]
Nov 14 21:30:57 vinux kernel: [ 0.263378] pci 0000:02:00.0: reg 30 32bit mmio pref: [0x000000-0x00ffff]
Nov 14 21:30:57 vinux kernel: [ 0.263543] pci 0000:02:00.2: reg 10 32bit mmio: [0xf4500400-0xf45004ff]
Nov 14 21:30:57 vinux kernel: [ 0.263780] pci 0000:02:00.3: reg 10 32bit mmio: [0xf4500800-0xf45008ff]
Nov 14 21:30:57 vinux kernel: [ 0.272236] pci 0000:00:1c.0: bridge 32bit mmio: [0xf4500000-0xf45fffff]
Nov 14 21:30:57 vinux kernel: [ 0.272516] pci 0000:04:00.0: reg 10 64bit mmio: [0xf4700000-0xf4703fff]
Nov 14 21:30:57 vinux kernel: [ 0.272737] pci 0000:04:00.0: supports D1 D2
Nov 14 21:30:57 vinux kernel: [ 0.272739] pci 0000:04:00.0: PME# supported from D0 D3hot D3cold
Nov 14 21:30:57 vinux kernel: [ 0.272847] pci 0000:04:00.0: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.273433] pci 0000:00:1c.2: bridge 32bit mmio: [0xf4700000-0xf47fffff]
Nov 14 21:30:57 vinux kernel: [ 0.273500] pci 0000:00:1c.3: bridge io port: [0x2000-0x2fff]
Nov 14 21:30:57 vinux kernel: [ 0.273505] pci 0000:00:1c.3: bridge 32bit mmio: [0xf0000000-0xf3ffffff]
Nov 14 21:30:57 vinux kernel: [ 0.273514] pci 0000:00:1c.3: bridge 64bit mmio pref: [0xf6000000-0xf7ffffff]
Nov 14 21:30:57 vinux kernel: [ 0.273738] pci 0000:07:00.0: reg 10 64bit mmio: [0xf4600000-0xf460ffff]
Nov 14 21:30:57 vinux kernel: [ 0.273978] pci 0000:07:00.0: PME# supported from D3hot D3cold
Nov 14 21:30:57 vinux kernel: [ 0.274084] pci 0000:07:00.0: PME# disabled
Nov 14 21:30:57 vinux kernel: [ 0.274686] pci 0000:00:1c.5: bridge 32bit mmio: [0xf4600000-0xf46fffff]
Nov 14 21:30:57 vinux kernel: [ 0.274760] pci 0000:00:1e.0: transparent bridge
Nov 14 21:30:57 vinux kernel: [ 0.274870] pci_bus 0000:00: on NUMA node 0
Nov 14 21:30:57 vinux kernel: [ 0.274875] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
Nov 14 21:30:57 vinux kernel: [ 0.275009] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0P1._PRT]
Nov 14 21:30:57 vinux kernel: [ 0.275097] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP01._PRT]
Nov 14 21:30:57 vinux kernel: [ 0.275199] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP02._PRT]
Nov 14 21:30:57 vinux kernel: [ 0.275262] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP03._PRT]
Nov 14 21:30:57 vinux kernel: [ 0.275332] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP04._PRT]
Nov 14 21:30:57 vinux kernel: [ 0.275398] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP06._PRT]
Nov 14 21:30:57 vinux kernel: [ 0.287616] ACPI: PCI Interrupt Link [LNKA] (IRQs 1 3 4 *5 6 7 10 12 14 15)
Nov 14 21:30:57 vinux kernel: [ 0.288280] ACPI: PCI Interrupt Link [LNKB] (IRQs 1 3 4 5 6 7 *11 12 14 15)
Nov 14 21:30:57 vinux kernel: [ 0.288940] ACPI: PCI Interrupt Link [LNKC] (IRQs 1 *3 4 5 6 7 10 12 14 15)
Nov 14 21:30:57 vinux kernel: [ 0.289598] ACPI: PCI Interrupt Link [LNKD] (IRQs 1 3 4 5 6 7 11 12 14 15) *10
Nov 14 21:30:57 vinux kernel: [ 0.290310] ACPI: PCI Interrupt Link [LNKE] (IRQs 1 3 4 5 6 *7 10 12 14 15)
Nov 14 21:30:57 vinux kernel: [ 0.290968] ACPI: PCI Interrupt Link [LNKF] (IRQs 1 3 4 5 6 7 *11 12 14 15)
Nov 14 21:30:57 vinux kernel: [ 0.291628] ACPI: PCI Interrupt Link [LNKG] (IRQs 1 3 4 5 6 7 *10 12 14 15)
Nov 14 21:30:57 vinux kernel: [ 0.292276] ACPI: PCI Interrupt Link [LNKH] (IRQs 1 3 *4 5 6 7 11 12 14 15)
Nov 14 21:30:57 vinux kernel: [ 0.292926] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
Nov 14 21:30:57 vinux kernel: [ 0.293016] vgaarb: loaded
Nov 14 21:30:57 vinux kernel: [ 0.293086] PCI: Using ACPI for IRQ routing
Nov 14 21:30:57 vinux kernel: [ 0.293086] HPET: 4 timers in total, 0 timers will be used for per-cpu timer
Nov 14 21:30:57 vinux kernel: [ 0.293086] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0
Nov 14 21:30:57 vinux kernel: [ 0.293086] hpet0: 4 comparators, 64-bit 14.318180 MHz counter
Nov 14 21:30:57 vinux kernel: [ 0.300019] Switching to clocksource tsc
Nov 14 21:30:57 vinux kernel: [ 0.301240] pnp: PnP ACPI init
Nov 14 21:30:57 vinux kernel: [ 0.301309] ACPI: bus type pnp registered
Nov 14 21:30:57 vinux kernel: [ 0.319871] pnp: PnP ACPI: found 10 devices
Nov 14 21:30:57 vinux kernel: [ 0.319932] ACPI: ACPI bus type pnp unregistered
Nov 14 21:30:57 vinux kernel: [ 0.319994] PnPBIOS: Disabled by ACPI PNP
Nov 14 21:30:57 vinux kernel: [ 0.320063] system 00:03: iomem range 0xfed00000-0xfed003ff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320134] system 00:05: ioport range 0x680-0x69f has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320199] system 00:05: ioport range 0xffff-0xffff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320264] system 00:05: ioport range 0xffff-0xffff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320329] system 00:05: ioport range 0xffff-0xffff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320394] system 00:05: ioport range 0x400-0x47f has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320459] system 00:05: ioport range 0x480-0x48f has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320524] system 00:05: ioport range 0x1180-0x11ff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320588] system 00:05: ioport range 0x164e-0x164f has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320654] system 00:05: ioport range 0xfe00-0xfe00 has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320719] system 00:05: ioport range 0xff00-0xff7f has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320787] system 00:09: iomem range 0xfed1c000-0xfed1ffff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320853] system 00:09: iomem range 0xfed10000-0xfed13fff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320919] system 00:09: iomem range 0xfed18000-0xfed18fff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.320985] system 00:09: iomem range 0xfed19000-0xfed19fff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.321051] system 00:09: iomem range 0xe0000000-0xefffffff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.321117] system 00:09: iomem range 0xfed20000-0xfed3ffff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.321182] system 00:09: iomem range 0xfed40000-0xfed44fff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.321248] system 00:09: iomem range 0xfed45000-0xfed8ffff has been reserved
Nov 14 21:30:57 vinux kernel: [ 0.356108] pci 0000:00:1c.0: PCI bridge, secondary bus 0000:02
Nov 14 21:30:57 vinux kernel: [ 0.356173] pci 0000:00:1c.0: IO window: 0x3000-0x3fff
Nov 14 21:30:57 vinux kernel: [ 0.356241] pci 0000:00:1c.0: MEM window: 0xf4500000-0xf45fffff
Nov 14 21:30:57 vinux kernel: [ 0.356308] pci 0000:00:1c.0: PREFETCH window: 0xc0000000-0xc01fffff
Nov 14 21:30:57 vinux kernel: [ 0.356378] pci 0000:00:1c.1: PCI bridge, secondary bus 0000:03
Nov 14 21:30:57 vinux kernel: [ 0.356443] pci 0000:00:1c.1: IO window: 0x4000-0x4fff
Nov 14 21:30:57 vinux kernel: [ 0.356510] pci 0000:00:1c.1: MEM window: 0xc0200000-0xc03fffff
Nov 14 21:30:57 vinux kernel: [ 0.356576] pci 0000:00:1c.1: PREFETCH window: 0x000000c0400000-0x000000c05fffff
Nov 14 21:30:57 vinux kernel: [ 0.356659] pci 0000:00:1c.2: PCI bridge, secondary bus 0000:04
Nov 14 21:30:57 vinux kernel: [ 0.356724] pci 0000:00:1c.2: IO window: 0x5000-0x5fff
Nov 14 21:30:57 vinux kernel: [ 0.356791] pci 0000:00:1c.2: MEM window: 0xf4700000-0xf47fffff
Nov 14 21:30:57 vinux kernel: [ 0.356858] pci 0000:00:1c.2: PREFETCH window: 0x000000c0600000-0x000000c07fffff
Nov 14 21:30:57 vinux kernel: [ 0.356941] pci 0000:00:1c.3: PCI bridge, secondary bus 0000:05
Nov 14 21:30:57 vinux kernel: [ 0.357006] pci 0000:00:1c.3: IO window: 0x2000-0x2fff
Nov 14 21:30:57 vinux kernel: [ 0.357073] pci 0000:00:1c.3: MEM window: 0xf0000000-0xf3ffffff
Nov 14 21:30:57 vinux kernel: [ 0.357139] pci 0000:00:1c.3: PREFETCH window: 0x000000f6000000-0x000000f7ffffff
Nov 14 21:30:57 vinux kernel: [ 0.357222] pci 0000:00:1c.5: PCI bridge, secondary bus 0000:07
Nov 14 21:30:57 vinux kernel: [ 0.357287] pci 0000:00:1c.5: IO window: 0x6000-0x6fff
Nov 14 21:30:57 vinux kernel: [ 0.357354] pci 0000:00:1c.5: MEM window: 0xf4600000-0xf46fffff
Nov 14 21:30:57 vinux kernel: [ 0.357420] pci 0000:00:1c.5: PREFETCH window: 0x000000c0800000-0x000000c09fffff
Nov 14 21:30:57 vinux kernel: [ 0.357503] pci 0000:00:1e.0: PCI bridge, secondary bus 0000:08
Nov 14 21:30:57 vinux kernel: [ 0.357566] pci 0000:00:1e.0: IO window: disabled
Nov 14 21:30:57 vinux kernel: [ 0.357631] pci 0000:00:1e.0: MEM window: disabled
Nov 14 21:30:57 vinux kernel: [ 0.357696] pci 0000:00:1e.0: PREFETCH window: disabled
Nov 14 21:30:57 vinux kernel: [ 0.357777] pci 0000:00:1c.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17
Nov 14 21:30:57 vinux kernel: [ 0.357846] pci 0000:00:1c.0: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.357858] pci 0000:00:1c.1: PCI INT B -> GSI 16 (level, low) -> IRQ 16
Nov 14 21:30:57 vinux kernel: [ 0.357925] pci 0000:00:1c.1: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.357936] pci 0000:00:1c.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
Nov 14 21:30:57 vinux kernel: [ 0.358003] pci 0000:00:1c.2: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.358015] pci 0000:00:1c.3: PCI INT D -> GSI 19 (level, low) -> IRQ 19
Nov 14 21:30:57 vinux kernel: [ 0.358082] pci 0000:00:1c.3: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.358092] pci 0000:00:1c.5: PCI INT B -> GSI 16 (level, low) -> IRQ 16
Nov 14 21:30:57 vinux kernel: [ 0.358159] pci 0000:00:1c.5: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.358168] pci 0000:00:1e.0: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.358172] pci_bus 0000:00: resource 0 io: [0x00-0xffff]
Nov 14 21:30:57 vinux kernel: [ 0.358175] pci_bus 0000:00: resource 1 mem: [0x000000-0xffffffff]
Nov 14 21:30:57 vinux kernel: [ 0.358178] pci_bus 0000:02: resource 0 io: [0x3000-0x3fff]
Nov 14 21:30:57 vinux kernel: [ 0.358180] pci_bus 0000:02: resource 1 mem: [0xf4500000-0xf45fffff]
Nov 14 21:30:57 vinux kernel: [ 0.358182] pci_bus 0000:02: resource 2 pref mem [0xc0000000-0xc01fffff]
Nov 14 21:30:57 vinux kernel: [ 0.358185] pci_bus 0000:03: resource 0 io: [0x4000-0x4fff]
Nov 14 21:30:57 vinux kernel: [ 0.358187] pci_bus 0000:03: resource 1 mem: [0xc0200000-0xc03fffff]
Nov 14 21:30:57 vinux kernel: [ 0.358190] pci_bus 0000:03: resource 2 pref mem [0xc0400000-0xc05fffff]
Nov 14 21:30:57 vinux kernel: [ 0.358192] pci_bus 0000:04: resource 0 io: [0x5000-0x5fff]
Nov 14 21:30:57 vinux kernel: [ 0.358195] pci_bus 0000:04: resource 1 mem: [0xf4700000-0xf47fffff]
Nov 14 21:30:57 vinux kernel: [ 0.358197] pci_bus 0000:04: resource 2 pref mem [0xc0600000-0xc07fffff]
Nov 14 21:30:57 vinux kernel: [ 0.358200] pci_bus 0000:05: resource 0 io: [0x2000-0x2fff]
Nov 14 21:30:57 vinux kernel: [ 0.358202] pci_bus 0000:05: resource 1 mem: [0xf0000000-0xf3ffffff]
Nov 14 21:30:57 vinux kernel: [ 0.358204] pci_bus 0000:05: resource 2 pref mem [0xf6000000-0xf7ffffff]
Nov 14 21:30:57 vinux kernel: [ 0.358207] pci_bus 0000:07: resource 0 io: [0x6000-0x6fff]
Nov 14 21:30:57 vinux kernel: [ 0.358209] pci_bus 0000:07: resource 1 mem: [0xf4600000-0xf46fffff]
Nov 14 21:30:57 vinux kernel: [ 0.358212] pci_bus 0000:07: resource 2 pref mem [0xc0800000-0xc09fffff]
Nov 14 21:30:57 vinux kernel: [ 0.358214] pci_bus 0000:08: resource 3 io: [0x00-0xffff]
Nov 14 21:30:57 vinux kernel: [ 0.358217] pci_bus 0000:08: resource 4 mem: [0x000000-0xffffffff]
Nov 14 21:30:57 vinux kernel: [ 0.358245] NET: Registered protocol family 2
Nov 14 21:30:57 vinux kernel: [ 0.358378] IP route cache hash table entries: 32768 (order: 5, 131072 bytes)
Nov 14 21:30:57 vinux kernel: [ 0.358712] TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
Nov 14 21:30:57 vinux kernel: [ 0.359232] TCP bind hash table entries: 65536 (order: 7, 524288 bytes)
Nov 14 21:30:57 vinux kernel: [ 0.359589] TCP: Hash tables configured (established 131072 bind 65536)
Nov 14 21:30:57 vinux kernel: [ 0.359655] TCP reno registered
Nov 14 21:30:57 vinux kernel: [ 0.359818] NET: Registered protocol family 1
Nov 14 21:30:57 vinux kernel: [ 0.359899] pci 0000:00:02.0: Boot video device
Nov 14 21:30:57 vinux kernel: [ 0.360107] Unpacking initramfs...
Nov 14 21:30:57 vinux kernel: [ 0.637581] Freeing initrd memory: 10581k freed
Nov 14 21:30:57 vinux kernel: [ 0.644068] Simple Boot Flag at 0x36 set to 0x1
Nov 14 21:30:57 vinux kernel: [ 0.644417] audit: initializing netlink socket (disabled)
Nov 14 21:30:57 vinux kernel: [ 0.644491] type=2000 audit(1321306245.643:1): initialized
Nov 14 21:30:57 vinux kernel: [ 0.647782] highmem bounce pool size: 64 pages
Nov 14 21:30:57 vinux kernel: [ 0.647846] HugeTLB registered 4 MB page size, pre-allocated 0 pages
Nov 14 21:30:57 vinux kernel: [ 0.649170] VFS: Disk quotas dquot_6.5.2
Nov 14 21:30:57 vinux kernel: [ 0.649281] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
Nov 14 21:30:57 vinux kernel: [ 0.649412] msgmni has been set to 1708
Nov 14 21:30:57 vinux kernel: [ 0.649638] alg: No test for stdrng (krng)
Nov 14 21:30:57 vinux kernel: [ 0.649744] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
Nov 14 21:30:57 vinux kernel: [ 0.649822] io scheduler noop registered
Nov 14 21:30:57 vinux kernel: [ 0.649882] io scheduler anticipatory registered
Nov 14 21:30:57 vinux kernel: [ 0.649943] io scheduler deadline registered
Nov 14 21:30:57 vinux kernel: [ 0.650033] io scheduler cfq registered (default)
Nov 14 21:30:57 vinux kernel: [ 0.650245] pcieport 0000:00:1c.0: irq 24 for MSI/MSI-X
Nov 14 21:30:57 vinux kernel: [ 0.650257] pcieport 0000:00:1c.0: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.650416] pcieport 0000:00:1c.1: irq 25 for MSI/MSI-X
Nov 14 21:30:57 vinux kernel: [ 0.650426] pcieport 0000:00:1c.1: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.650584] pcieport 0000:00:1c.2: irq 26 for MSI/MSI-X
Nov 14 21:30:57 vinux kernel: [ 0.650595] pcieport 0000:00:1c.2: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.650750] pcieport 0000:00:1c.3: irq 27 for MSI/MSI-X
Nov 14 21:30:57 vinux kernel: [ 0.650761] pcieport 0000:00:1c.3: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.650916] pcieport 0000:00:1c.5: irq 28 for MSI/MSI-X
Nov 14 21:30:57 vinux kernel: [ 0.650926] pcieport 0000:00:1c.5: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 0.651089] isapnp: Scanning for PnP cards...
Nov 14 21:30:57 vinux kernel: [ 1.005143] isapnp: No Plug & Play device found
Nov 14 21:30:57 vinux kernel: [ 1.006452] Linux agpgart interface v0.103
Nov 14 21:30:57 vinux kernel: [ 1.006583] agpgart-intel 0000:00:00.0: Intel Mobile Intel® GM45 Express Chipset
Nov 14 21:30:57 vinux kernel: [ 1.007017] agpgart-intel 0000:00:00.0: detected 32764K stolen memory
Nov 14 21:30:57 vinux kernel: [ 1.038455] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000
Nov 14 21:30:57 vinux kernel: [ 1.038593] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
Nov 14 21:30:57 vinux kernel: [ 1.039021] PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:MSE0] at 0x60,0x64 irq 1,12
Nov 14 21:30:57 vinux kernel: [ 1.069998] serio: i8042 KBD port at 0x60,0x64 irq 1
Nov 14 21:30:57 vinux kernel: [ 1.070065] serio: i8042 AUX port at 0x60,0x64 irq 12
Nov 14 21:30:57 vinux kernel: [ 1.070174] mice: PS/2 mouse device common for all mice
Nov 14 21:30:57 vinux kernel: [ 1.070275] rtc_cmos 00:06: RTC can wake from S4
Nov 14 21:30:57 vinux kernel: [ 1.070370] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0
Nov 14 21:30:57 vinux kernel: [ 1.070466] rtc0: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
Nov 14 21:30:57 vinux kernel: [ 1.070542] cpuidle: using governor ladder
Nov 14 21:30:57 vinux kernel: [ 1.070605] cpuidle: using governor menu
Nov 14 21:30:57 vinux kernel: [ 1.070668] No iBFT detected.
Nov 14 21:30:57 vinux kernel: [ 1.071036] TCP cubic registered
Nov 14 21:30:57 vinux kernel: [ 1.071222] NET: Registered protocol family 10
Nov 14 21:30:57 vinux kernel: [ 1.071931] Mobile IPv6
Nov 14 21:30:57 vinux kernel: [ 1.071992] NET: Registered protocol family 17
Nov 14 21:30:57 vinux kernel: [ 1.072079] Using IPI No-Shortcut mode
Nov 14 21:30:57 vinux kernel: [ 1.072198] PM: Resume from disk failed.
Nov 14 21:30:57 vinux kernel: [ 1.072213] registered taskstats version 1
Nov 14 21:30:57 vinux kernel: [ 1.073330] rtc_cmos 00:06: setting system clock to 2011-11-14 21:30:47 UTC (1321306247)
Nov 14 21:30:57 vinux kernel: [ 1.073464] Initalizing network drop monitor service
Nov 14 21:30:57 vinux kernel: [ 1.073543] Freeing unused kernel memory: 380k freed
Nov 14 21:30:57 vinux kernel: [ 1.073773] Write protecting the kernel text: 2508k
Nov 14 21:30:57 vinux kernel: [ 1.073854] Write protecting the kernel read-only data: 920k
Nov 14 21:30:57 vinux kernel: [ 1.089978] udev[56]: starting version 164
Nov 14 21:30:57 vinux kernel: [ 1.100796] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input0
Nov 14 21:30:57 vinux kernel: [ 1.206841] usbcore: registered new interface driver usbfs
Nov 14 21:30:57 vinux kernel: [ 1.207059] usbcore: registered new interface driver hub
Nov 14 21:30:57 vinux kernel: [ 1.207279] usbcore: registered new device driver usb
Nov 14 21:30:57 vinux kernel: [ 1.215511] ACPI: Invalid active0 threshold
Nov 14 21:30:57 vinux kernel: [ 1.220431] thermal LNXTHERM:01: registered as thermal_zone0
Nov 14 21:30:57 vinux kernel: [ 1.221449] ACPI: Thermal Zone [TZ00] (64 C)
Nov 14 21:30:57 vinux kernel: [ 1.222779] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
Nov 14 21:30:57 vinux kernel: [ 1.222884] ehci_hcd 0000:00:1a.7: PCI INT C -> GSI 20 (level, low) -> IRQ 20
Nov 14 21:30:57 vinux kernel: [ 1.222972] ehci_hcd 0000:00:1a.7: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.222976] ehci_hcd 0000:00:1a.7: EHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.223062] ehci_hcd 0000:00:1a.7: new USB bus registered, assigned bus number 1
Nov 14 21:30:57 vinux kernel: [ 1.223187] ehci_hcd 0000:00:1a.7: debug port 1
Nov 14 21:30:57 vinux kernel: [ 1.227149] ehci_hcd 0000:00:1a.7: cache line size of 32 is not supported
Nov 14 21:30:57 vinux kernel: [ 1.227395] SCSI subsystem initialized
Nov 14 21:30:57 vinux kernel: [ 1.231991] ehci_hcd 0000:00:1a.7: irq 20, io mem 0xf4a04800
Nov 14 21:30:57 vinux kernel: [ 1.238254] sdhci: Secure Digital Host Controller Interface driver
Nov 14 21:30:57 vinux kernel: [ 1.238324] sdhci: Copyright(c) Pierre Ossman
Nov 14 21:30:57 vinux kernel: [ 1.239687] uhci_hcd: USB Universal Host Controller Interface driver
Nov 14 21:30:57 vinux kernel: [ 1.245045] sdhci-pci 0000:02:00.0: SDHCI controller found [197b:2382] (rev 0)
Nov 14 21:30:57 vinux kernel: [ 1.245151] sdhci-pci 0000:02:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
Nov 14 21:30:57 vinux kernel: [ 1.245275] sdhci-pci 0000:02:00.0: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.245383] Registered led device: mmc0::
Nov 14 21:30:57 vinux kernel: [ 1.245506] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA
Nov 14 21:30:57 vinux kernel: [ 1.245587] sdhci-pci 0000:02:00.2: SDHCI controller found [197b:2381] (rev 0)
Nov 14 21:30:57 vinux kernel: [ 1.245684] sdhci-pci 0000:02:00.2: PCI INT A -> GSI 16 (level, low) -> IRQ 16
Nov 14 21:30:57 vinux kernel: [ 1.245765] sdhci-pci 0000:02:00.2: Refusing to bind to secondary interface.
Nov 14 21:30:57 vinux kernel: [ 1.245836] sdhci-pci 0000:02:00.2: PCI INT A disabled
Nov 14 21:30:57 vinux kernel: [ 1.256489] ehci_hcd 0000:00:1a.7: USB 2.0 started, EHCI 1.00
Nov 14 21:30:57 vinux kernel: [ 1.256589] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
Nov 14 21:30:57 vinux kernel: [ 1.256654] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
Nov 14 21:30:57 vinux kernel: [ 1.256731] usb usb1: Product: EHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.256793] usb usb1: Manufacturer: Linux 2.6.32-5-686 ehci_hcd
Nov 14 21:30:57 vinux kernel: [ 1.256856] usb usb1: SerialNumber: 0000:00:1a.7
Nov 14 21:30:57 vinux kernel: [ 1.256996] usb usb1: configuration #1 chosen from 1 choice
Nov 14 21:30:57 vinux kernel: [ 1.257092] hub 1-0:1.0: USB hub found
Nov 14 21:30:57 vinux kernel: [ 1.257161] hub 1-0:1.0: 6 ports detected
Nov 14 21:30:57 vinux kernel: [ 1.257299] uhci_hcd 0000:00:1a.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
Nov 14 21:30:57 vinux kernel: [ 1.257379] uhci_hcd 0000:00:1a.0: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.257383] uhci_hcd 0000:00:1a.0: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.257458] uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 2
Nov 14 21:30:57 vinux kernel: [ 1.257570] uhci_hcd 0000:00:1a.0: irq 16, io base 0x00001820
Nov 14 21:30:57 vinux kernel: [ 1.257674] usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
Nov 14 21:30:57 vinux kernel: [ 1.257739] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
Nov 14 21:30:57 vinux kernel: [ 1.257816] usb usb2: Product: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.257878] usb usb2: Manufacturer: Linux 2.6.32-5-686 uhci_hcd
Nov 14 21:30:57 vinux kernel: [ 1.257941] usb usb2: SerialNumber: 0000:00:1a.0
Nov 14 21:30:57 vinux kernel: [ 1.258080] usb usb2: configuration #1 chosen from 1 choice
Nov 14 21:30:57 vinux kernel: [ 1.258171] hub 2-0:1.0: USB hub found
Nov 14 21:30:57 vinux kernel: [ 1.258237] hub 2-0:1.0: 2 ports detected
Nov 14 21:30:57 vinux kernel: [ 1.258364] ehci_hcd 0000:00:1d.7: PCI INT A -> GSI 23 (level, low) -> IRQ 23
Nov 14 21:30:57 vinux kernel: [ 1.258448] ehci_hcd 0000:00:1d.7: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.258451] ehci_hcd 0000:00:1d.7: EHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.258519] ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 3
Nov 14 21:30:57 vinux kernel: [ 1.258632] ehci_hcd 0000:00:1d.7: debug port 1
Nov 14 21:30:57 vinux kernel: [ 1.260842] tg3.c:v3.116 (December 3, 2010)
Nov 14 21:30:57 vinux kernel: [ 1.260990] tg3 0000:07:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17
Nov 14 21:30:57 vinux kernel: [ 1.262452] tg3 0000:07:00.0: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.262598] ehci_hcd 0000:00:1d.7: cache line size of 32 is not supported
Nov 14 21:30:57 vinux kernel: [ 1.262717] ehci_hcd 0000:00:1d.7: irq 23, io mem 0xf4a04c00
Nov 14 21:30:57 vinux kernel: [ 1.263025] libata version 3.00 loaded.
Nov 14 21:30:57 vinux kernel: [ 1.276007] ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00
Nov 14 21:30:57 vinux kernel: [ 1.276091] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002
Nov 14 21:30:57 vinux kernel: [ 1.276156] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
Nov 14 21:30:57 vinux kernel: [ 1.276233] usb usb3: Product: EHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.276295] usb usb3: Manufacturer: Linux 2.6.32-5-686 ehci_hcd
Nov 14 21:30:57 vinux kernel: [ 1.276359] usb usb3: SerialNumber: 0000:00:1d.7
Nov 14 21:30:57 vinux kernel: [ 1.276497] usb usb3: configuration #1 chosen from 1 choice
Nov 14 21:30:57 vinux kernel: [ 1.276591] hub 3-0:1.0: USB hub found
Nov 14 21:30:57 vinux kernel: [ 1.276657] hub 3-0:1.0: 6 ports detected
Nov 14 21:30:57 vinux kernel: [ 1.276787] uhci_hcd 0000:00:1a.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
Nov 14 21:30:57 vinux kernel: [ 1.276862] uhci_hcd 0000:00:1a.1: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.276866] uhci_hcd 0000:00:1a.1: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.276937] uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4
Nov 14 21:30:57 vinux kernel: [ 1.277064] uhci_hcd 0000:00:1a.1: irq 21, io base 0x00001840
Nov 14 21:30:57 vinux kernel: [ 1.277160] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
Nov 14 21:30:57 vinux kernel: [ 1.277225] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
Nov 14 21:30:57 vinux kernel: [ 1.277301] usb usb4: Product: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.277363] usb usb4: Manufacturer: Linux 2.6.32-5-686 uhci_hcd
Nov 14 21:30:57 vinux kernel: [ 1.277426] usb usb4: SerialNumber: 0000:00:1a.1
Nov 14 21:30:57 vinux kernel: [ 1.277550] usb usb4: configuration #1 chosen from 1 choice
Nov 14 21:30:57 vinux kernel: [ 1.277637] hub 4-0:1.0: USB hub found
Nov 14 21:30:57 vinux kernel: [ 1.277701] hub 4-0:1.0: 2 ports detected
Nov 14 21:30:57 vinux kernel: [ 1.278007] ahci 0000:00:1f.2: version 3.0
Nov 14 21:30:57 vinux kernel: [ 1.278022] ahci 0000:00:1f.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19
Nov 14 21:30:57 vinux kernel: [ 1.278184] ahci 0000:00:1f.2: irq 29 for MSI/MSI-X
Nov 14 21:30:57 vinux kernel: [ 1.278265] ahci: SSS flag set, parallel bus scan disabled
Nov 14 21:30:57 vinux kernel: [ 1.278391] ahci 0000:00:1f.2: AHCI 0001.0200 32 slots 4 ports 3 Gbps 0x3 impl SATA mode
Nov 14 21:30:57 vinux kernel: [ 1.278500] ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pio slum part ccc ems sxs
Nov 14 21:30:57 vinux kernel: [ 1.278622] ahci 0000:00:1f.2: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.285066] scsi0 : ahci
Nov 14 21:30:57 vinux kernel: [ 1.285314] scsi1 : ahci
Nov 14 21:30:57 vinux kernel: [ 1.285492] scsi2 : ahci
Nov 14 21:30:57 vinux kernel: [ 1.285672] scsi3 : ahci
Nov 14 21:30:57 vinux kernel: [ 1.285794] ata1: SATA max UDMA/133 abar m2048@0xf4a04000 port 0xf4a04100 irq 29
Nov 14 21:30:57 vinux kernel: [ 1.285915] ata2: SATA max UDMA/133 abar m2048@0xf4a04000 port 0xf4a04180 irq 29
Nov 14 21:30:57 vinux kernel: [ 1.286018] ata3: DUMMY
Nov 14 21:30:57 vinux kernel: [ 1.286098] ata4: DUMMY
Nov 14 21:30:57 vinux kernel: [ 1.286318] uhci_hcd 0000:00:1a.2: PCI INT C -> GSI 20 (level, low) -> IRQ 20
Nov 14 21:30:57 vinux kernel: [ 1.286417] uhci_hcd 0000:00:1a.2: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.286420] uhci_hcd 0000:00:1a.2: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.286513] uhci_hcd 0000:00:1a.2: new USB bus registered, assigned bus number 5
Nov 14 21:30:57 vinux kernel: [ 1.286661] uhci_hcd 0000:00:1a.2: irq 20, io base 0x00001860
Nov 14 21:30:57 vinux kernel: [ 1.286786] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
Nov 14 21:30:57 vinux kernel: [ 1.286874] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
Nov 14 21:30:57 vinux kernel: [ 1.286979] usb usb5: Product: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.287074] usb usb5: Manufacturer: Linux 2.6.32-5-686 uhci_hcd
Nov 14 21:30:57 vinux kernel: [ 1.287162] usb usb5: SerialNumber: 0000:00:1a.2
Nov 14 21:30:57 vinux kernel: [ 1.287448] usb usb5: configuration #1 chosen from 1 choice
Nov 14 21:30:57 vinux kernel: [ 1.287595] hub 5-0:1.0: USB hub found
Nov 14 21:30:57 vinux kernel: [ 1.287680] hub 5-0:1.0: 2 ports detected
Nov 14 21:30:57 vinux kernel: [ 1.287823] uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 23 (level, low) -> IRQ 23
Nov 14 21:30:57 vinux kernel: [ 1.287924] uhci_hcd 0000:00:1d.0: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.287931] uhci_hcd 0000:00:1d.0: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.288020] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 6
Nov 14 21:30:57 vinux kernel: [ 1.288162] uhci_hcd 0000:00:1d.0: irq 23, io base 0x00001880
Nov 14 21:30:57 vinux kernel: [ 1.288287] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
Nov 14 21:30:57 vinux kernel: [ 1.288371] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
Nov 14 21:30:57 vinux kernel: [ 1.288476] usb usb6: Product: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.288558] usb usb6: Manufacturer: Linux 2.6.32-5-686 uhci_hcd
Nov 14 21:30:57 vinux kernel: [ 1.288655] usb usb6: SerialNumber: 0000:00:1d.0
Nov 14 21:30:57 vinux kernel: [ 1.288844] usb usb6: configuration #1 chosen from 1 choice
Nov 14 21:30:57 vinux kernel: [ 1.288985] hub 6-0:1.0: USB hub found
Nov 14 21:30:57 vinux kernel: [ 1.289096] hub 6-0:1.0: 2 ports detected
Nov 14 21:30:57 vinux kernel: [ 1.289232] uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 19 (level, low) -> IRQ 19
Nov 14 21:30:57 vinux kernel: [ 1.289328] uhci_hcd 0000:00:1d.1: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.289336] uhci_hcd 0000:00:1d.1: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.289424] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 7
Nov 14 21:30:57 vinux kernel: [ 1.289580] uhci_hcd 0000:00:1d.1: irq 19, io base 0x000018a0
Nov 14 21:30:57 vinux kernel: [ 1.289698] usb usb7: New USB device found, idVendor=1d6b, idProduct=0001
Nov 14 21:30:57 vinux kernel: [ 1.289782] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
Nov 14 21:30:57 vinux kernel: [ 1.289898] usb usb7: Product: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.289984] usb usb7: Manufacturer: Linux 2.6.32-5-686 uhci_hcd
Nov 14 21:30:57 vinux kernel: [ 1.290068] usb usb7: SerialNumber: 0000:00:1d.1
Nov 14 21:30:57 vinux kernel: [ 1.290252] usb usb7: configuration #1 chosen from 1 choice
Nov 14 21:30:57 vinux kernel: [ 1.290392] hub 7-0:1.0: USB hub found
Nov 14 21:30:57 vinux kernel: [ 1.290477] hub 7-0:1.0: 2 ports detected
Nov 14 21:30:57 vinux kernel: [ 1.290608] uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
Nov 14 21:30:57 vinux kernel: [ 1.290713] uhci_hcd 0000:00:1d.2: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 1.290720] uhci_hcd 0000:00:1d.2: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.290807] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 8
Nov 14 21:30:57 vinux kernel: [ 1.290959] uhci_hcd 0000:00:1d.2: irq 18, io base 0x000018c0
Nov 14 21:30:57 vinux kernel: [ 1.291079] usb usb8: New USB device found, idVendor=1d6b, idProduct=0001
Nov 14 21:30:57 vinux kernel: [ 1.291165] usb usb8: New USB device strings: Mfr=3, Product=2, SerialNumber=1
Nov 14 21:30:57 vinux kernel: [ 1.291272] usb usb8: Product: UHCI Host Controller
Nov 14 21:30:57 vinux kernel: [ 1.291355] usb usb8: Manufacturer: Linux 2.6.32-5-686 uhci_hcd
Nov 14 21:30:57 vinux kernel: [ 1.291443] usb usb8: SerialNumber: 0000:00:1d.2
Nov 14 21:30:57 vinux kernel: [ 1.291795] usb usb8: configuration #1 chosen from 1 choice
Nov 14 21:30:57 vinux kernel: [ 1.291950] hub 8-0:1.0: USB hub found
Nov 14 21:30:57 vinux kernel: [ 1.292050] hub 8-0:1.0: 2 ports detected
Nov 14 21:30:57 vinux kernel: [ 1.310906] tg3 0000:07:00.0: eth0: Tigon3 [partno(BCM95906) rev c002] (PCI Express) MAC address 00:23:5a:17:01:6e
Nov 14 21:30:57 vinux kernel: [ 1.310993] tg3 0000:07:00.0: eth0: attached PHY is 5906 (10/100Base-TX Ethernet) (WireSpeed[0])
Nov 14 21:30:57 vinux kernel: [ 1.311072] tg3 0000:07:00.0: eth0: RXcsums[1] LinkChgREG[0] MIirq[0] ASF[0] TSOcap[1]
Nov 14 21:30:57 vinux kernel: [ 1.311151] tg3 0000:07:00.0: eth0: dma_rwctrl[76180000] dma_mask[64-bit]
Nov 14 21:30:57 vinux kernel: [ 1.569009] usb 1-6: new high speed USB device using ehci_hcd and address 2
Nov 14 21:30:57 vinux kernel: [ 1.613018] ata1: SATA link down (SStatus 0 SControl 300)
Nov 14 21:30:57 vinux kernel: [ 1.701857] usb 1-6: New USB device found, idVendor=0781, idProduct=5567
Nov 14 21:30:57 vinux kernel: [ 1.701922] usb 1-6: New USB device strings: Mfr=1, Product=2, SerialNumber=3
Nov 14 21:30:57 vinux kernel: [ 1.701987] usb 1-6: Product: Cruzer Blade
Nov 14 21:30:57 vinux kernel: [ 1.702047] usb 1-6: Manufacturer: SanDisk
Nov 14 21:30:57 vinux kernel: [ 1.702108] usb 1-6: SerialNumber: 20043513421424F00A4F
Nov 14 21:30:57 vinux kernel: [ 1.702252] usb 1-6: configuration #1 chosen from 1 choice
Nov 14 21:30:57 vinux kernel: [ 1.708889] Initializing USB Mass Storage driver...
Nov 14 21:30:57 vinux kernel: [ 1.709085] scsi4 : SCSI emulation for USB Mass Storage devices
Nov 14 21:30:57 vinux kernel: [ 1.709224] usbcore: registered new interface driver usb-storage
Nov 14 21:30:57 vinux kernel: [ 1.709291] USB Mass Storage support registered.
Nov 14 21:30:57 vinux kernel: [ 1.709357] usb-storage: device found at 2
Nov 14 21:30:57 vinux kernel: [ 1.709358] usb-storage: waiting for device to settle before scanning
Nov 14 21:30:57 vinux kernel: [ 1.813010] usb 3-3: new high speed USB device using ehci_hcd and address 2
Nov 14 21:30:57 vinux kernel: [ 1.949023] ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
Nov 14 21:30:57 vinux kernel: [ 1.952813] ata2.00: ATAPI: HL-DT-ST DVDRAM GSA-T50N, RV06, max UDMA/133
Nov 14 21:30:57 vinux kernel: [ 1.957769] ata2.00: configured for UDMA/133
Nov 14 21:30:57 vinux kernel: [ 2.086991] scsi 1:0:0:0: CD-ROM HL-DT-ST DVDRAM GSA-T50N RV06 PQ: 0 ANSI: 5
Nov 14 21:30:57 vinux kernel: [ 2.099970] usb 3-3: New USB device found, idVendor=04f2, idProduct=b090
Nov 14 21:30:57 vinux kernel: [ 2.100067] usb 3-3: New USB device strings: Mfr=1, Product=2, SerialNumber=0
Nov 14 21:30:57 vinux kernel: [ 2.100136] usb 3-3: Product: Lenovo EasyCamera
Nov 14 21:30:57 vinux kernel: [ 2.100949] usb 3-3: Manufacturer: Vimicro Corp.
Nov 14 21:30:57 vinux kernel: [ 2.101106] usb 3-3: configuration #1 chosen from 1 choice
Nov 14 21:30:57 vinux kernel: [ 2.422941] sr0: scsi3-mmc drive: 24x/24x writer dvd-ram cd/rw xa/form2 cdda tray
Nov 14 21:30:57 vinux kernel: [ 2.423022] Uniform CD-ROM driver Revision: 3.20
Nov 14 21:30:57 vinux kernel: [ 2.423180] sr 1:0:0:0: Attached scsi CD-ROM sr0
Nov 14 21:30:57 vinux kernel: [ 2.427234] sr 1:0:0:0: Attached scsi generic sg0 type 5
Nov 14 21:30:57 vinux kernel: [ 6.709201] usb-storage: device scan complete
Nov 14 21:30:57 vinux kernel: [ 6.709822] scsi 4:0:0:0: Direct-Access SanDisk Cruzer Blade 1.14 PQ: 0 ANSI: 2
Nov 14 21:30:57 vinux kernel: [ 6.710236] scsi 4:0:0:0: Attached scsi generic sg1 type 0
Nov 14 21:30:57 vinux kernel: [ 6.716312] sd 4:0:0:0: [sda] 7821312 512-byte logical blocks: (4.00 GB/3.72 GiB)
Nov 14 21:30:57 vinux kernel: [ 6.717805] sd 4:0:0:0: [sda] Write Protect is off
Nov 14 21:30:57 vinux kernel: [ 6.717867] sd 4:0:0:0: [sda] Mode Sense: 03 00 00 00
Nov 14 21:30:57 vinux kernel: [ 6.717870] sd 4:0:0:0: [sda] Assuming drive cache: write through
Nov 14 21:30:57 vinux kernel: [ 6.720430] sd 4:0:0:0: [sda] Assuming drive cache: write through
Nov 14 21:30:57 vinux kernel: [ 6.720494] sda: sda1 sda2 sda3
Nov 14 21:30:57 vinux kernel: [ 6.724555] sd 4:0:0:0: [sda] Assuming drive cache: write through
Nov 14 21:30:57 vinux kernel: [ 6.724621] sd 4:0:0:0: [sda] Attached SCSI removable disk
Nov 14 21:30:57 vinux kernel: [ 7.028659] EXT4-fs (sda1): mounted filesystem with ordered data mode
Nov 14 21:30:57 vinux kernel: [ 7.675596] udev[423]: starting version 164
Nov 14 21:30:57 vinux kernel: [ 7.807298] ACPI: SSDT bdb1ac20 00265 (v01 PmRef Cpu0Ist 00003000 INTL 20050624)
Nov 14 21:30:57 vinux kernel: [ 7.827883] ACPI: SSDT bdb18620 00549 (v01 PmRef Cpu0Cst 00003001 INTL 20050624)
Nov 14 21:30:57 vinux kernel: [ 7.858295] Monitor-Mwait will be used to enter C-1 state
Nov 14 21:30:57 vinux kernel: [ 7.888137] Monitor-Mwait will be used to enter C-2 state
Nov 14 21:30:57 vinux kernel: [ 7.888144] Marking TSC unstable due to TSC halts in idle
Nov 14 21:30:57 vinux kernel: [ 7.888303] processor LNXCPU:00: registered as cooling_device0
Nov 14 21:30:57 vinux kernel: [ 7.888891] ACPI: SSDT bdb19ca0 001CF (v01 PmRef ApIst 00003000 INTL 20050624)
Nov 14 21:30:57 vinux kernel: [ 7.889483] ACPI: SSDT bdb19f20 0008D (v01 PmRef ApCst 00003000 INTL 20050624)
Nov 14 21:30:57 vinux kernel: [ 7.892044] Switching to clocksource hpet
Nov 14 21:30:57 vinux kernel: [ 7.892310] processor LNXCPU:01: registered as cooling_device1
Nov 14 21:30:57 vinux kernel: [ 7.906109] lib80211: common routines for IEEE802.11 drivers
Nov 14 21:30:57 vinux kernel: [ 7.906181] lib80211_crypt: registered algorithm 'NULL'
Nov 14 21:30:57 vinux kernel: [ 8.558438] wl: module license 'MIXED/Proprietary' taints kernel.
Nov 14 21:30:57 vinux kernel: [ 8.558508] Disabling lock debugging due to kernel taint
Nov 14 21:30:57 vinux kernel: [ 8.564650] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input1
Nov 14 21:30:57 vinux kernel: [ 8.564816] ACPI: Lid Switch [LID0]
Nov 14 21:30:57 vinux kernel: [ 8.564940] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input2
Nov 14 21:30:57 vinux kernel: [ 8.565027] ACPI: Power Button [PWRB]
Nov 14 21:30:57 vinux kernel: [ 8.565162] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3
Nov 14 21:30:57 vinux kernel: [ 8.565245] ACPI: Power Button [PWRF]
Nov 14 21:30:57 vinux kernel: [ 8.568882] wl 0000:04:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
Nov 14 21:30:57 vinux kernel: [ 8.568997] wl 0000:04:00.0: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 8.569334] input: PC Speaker as /devices/platform/pcspkr/input/input4
Nov 14 21:30:57 vinux kernel: [ 8.583369] i801_smbus 0000:00:1f.3: PCI INT C -> GSI 19 (level, low) -> IRQ 19
Nov 14 21:30:57 vinux kernel: [ 8.583452] ACPI: I/O resource 0000:00:1f.3 [0x1c00-0x1c1f] conflicts with ACPI region SMBI [0x1c00-0x1c0f]
Nov 14 21:30:57 vinux kernel: [ 8.583582] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
Nov 14 21:30:57 vinux kernel: [ 8.588300] jmb38x_ms 0000:02:00.3: PCI INT A -> GSI 16 (level, low) -> IRQ 16
Nov 14 21:30:57 vinux kernel: [ 8.588387] jmb38x_ms 0000:02:00.3: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 8.594085] ACPI: AC Adapter [ACAD] (on-line)
Nov 14 21:30:57 vinux kernel: [ 8.615386] lib80211_crypt: registered algorithm 'TKIP'
Nov 14 21:30:57 vinux kernel: [ 8.757606] ACPI: Battery Slot [BAT1] (battery present)
Nov 14 21:30:57 vinux kernel: [ 8.758213] eth1: Broadcom BCM4315 802.11 Hybrid Wireless Controller 5.60.48.36
Nov 14 21:30:57 vinux kernel: [ 8.769316] Linux video capture interface: v2.00
Nov 14 21:30:57 vinux kernel: [ 8.784857] uvcvideo: Found UVC 1.00 device Lenovo EasyCamera (04f2:b090)
Nov 14 21:30:57 vinux kernel: [ 8.788177] input: Lenovo EasyCamera as /devices/pci0000:00/0000:00:1d.7/usb3/3-3/3-3:1.0/input/input5
Nov 14 21:30:57 vinux kernel: [ 8.788320] usbcore: registered new interface driver uvcvideo
Nov 14 21:30:57 vinux kernel: [ 8.788386] USB Video Class driver (v0.1.0)
Nov 14 21:30:57 vinux kernel: [ 8.808253] [drm] Initialized drm 1.1.0 20060810
Nov 14 21:30:57 vinux kernel: [ 8.854048] pci 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
Nov 14 21:30:57 vinux kernel: [ 8.854122] pci 0000:00:02.0: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 8.860192] mtrr: type mismatch for d0000000,10000000 old: write-back new: write-combining
Nov 14 21:30:57 vinux kernel: [ 8.860274] [drm] MTRR allocation failed. Graphics performance may suffer.
Nov 14 21:30:57 vinux kernel: [ 8.860429] pci 0000:00:02.0: irq 30 for MSI/MSI-X
Nov 14 21:30:57 vinux kernel: [ 8.887967] acpi device:05: registered as cooling_device2
Nov 14 21:30:57 vinux kernel: [ 8.916479] acpi device:06: registered as cooling_device3
Nov 14 21:30:57 vinux kernel: [ 8.937741] acpi device:07: registered as cooling_device4
Nov 14 21:30:57 vinux kernel: [ 8.948176] HDA Intel 0000:00:1b.0: power state changed by ACPI to D0
Nov 14 21:30:57 vinux kernel: [ 8.948288] HDA Intel 0000:00:1b.0: power state changed by ACPI to D0
Nov 14 21:30:57 vinux kernel: [ 8.948363] HDA Intel 0000:00:1b.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22
Nov 14 21:30:57 vinux kernel: [ 8.948508] HDA Intel 0000:00:1b.0: irq 31 for MSI/MSI-X
Nov 14 21:30:57 vinux kernel: [ 8.948537] HDA Intel 0000:00:1b.0: setting latency timer to 64
Nov 14 21:30:57 vinux kernel: [ 8.964050] acpi device:08: registered as cooling_device5
Nov 14 21:30:57 vinux kernel: [ 8.992601] acpi device:09: registered as cooling_device6
Nov 14 21:30:57 vinux kernel: [ 8.992803] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:01/input/input6
Nov 14 21:30:57 vinux kernel: [ 8.992932] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no)
Nov 14 21:30:57 vinux kernel: [ 8.993026] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
Nov 14 21:30:57 vinux kernel: [ 9.010779] input: HDA Intel Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input7
Nov 14 21:30:57 vinux kernel: [ 9.010942] input: HDA Intel Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8
Nov 14 21:30:57 vinux kernel: [ 9.011081] input: HDA Intel Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9
Nov 14 21:30:57 vinux kernel: [ 9.309423] input: PS/2 Mouse as /devices/platform/i8042/serio1/input/input10
Nov 14 21:30:57 vinux kernel: [ 9.347979] input: AlpsPS/2 ALPS GlidePoint as /devices/platform/i8042/serio1/input/input11
Nov 14 21:30:57 vinux kernel: [ 9.564661] Adding 208836k swap on /dev/sda3. Priority:-1 extents:1 across:208836k
Nov 14 21:30:57 vinux kernel: [ 9.709959] loop: module loaded
Nov 14 21:30:57 vinux kernel: [ 9.730217] input: Speakup as /devices/virtual/input/input12
Nov 14 21:30:57 vinux kernel: [ 9.730424] speakup 3.1.5: initialized
Nov 14 21:30:57 vinux kernel: [ 9.730495] synth name on entry is: <NULL>
Nov 14 21:30:57 vinux kernel: [ 9.730930] initialized device: /dev/synth, node (MAJOR 10, MINOR 25)
Nov 14 21:30:57 vinux kernel: [ 9.733621] synth probe
Nov 14 21:30:57 vinux kernel: [ 9.734065] initialized device: /dev/softsynth, node (MAJOR 10, MINOR 26)
Nov 14 21:30:57 vinux kernel: [ 9.877615] EXT4-fs (sda2): mounted filesystem with ordered data mode
Nov 14 21:30:57 vinux kernel: [ 10.381844] fuse init (API version 7.13)
Nov 14 21:30:57 vinux kernel: [ 10.819860] apm: BIOS not found.
Nov 14 21:30:59 vinux kernel: [ 12.665417] input: ACPI Virtual Keyboard Device as /devices/virtual/input/input13
Nov 14 21:30:59 vinux kernel: [ 12.890636] Bluetooth: Core ver 2.15
Nov 14 21:30:59 vinux kernel: [ 12.890811] NET: Registered protocol family 31
Nov 14 21:30:59 vinux kernel: [ 12.890897] Bluetooth: HCI device and connection manager initialized
Nov 14 21:30:59 vinux kernel: [ 12.890992] Bluetooth: HCI socket layer initialized
Nov 14 21:30:59 vinux kernel: [ 12.903506] Bluetooth: L2CAP ver 2.14
Nov 14 21:30:59 vinux kernel: [ 12.903597] Bluetooth: L2CAP socket layer initialized
Nov 14 21:30:59 vinux kernel: [ 12.922900] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
Nov 14 21:30:59 vinux kernel: [ 12.923012] Bluetooth: BNEP filters: protocol multicast
Nov 14 21:30:59 vinux kernel: [ 12.945253] Bridge firewalling registered
Nov 14 21:30:59 vinux kernel: [ 12.960072] Bluetooth: SCO (Voice Link) ver 0.6
Nov 14 21:30:59 vinux kernel: [ 12.960162] Bluetooth: SCO socket layer initialized
Nov 14 21:30:59 vinux kernel: [ 12.979459] lp: driver loaded but no devices found
Nov 14 21:30:59 vinux kernel: [ 12.986681] ppdev: user-space parallel port driver
Nov 14 21:31:00 vinux kernel: [ 13.661172] tg3 0000:07:00.0: irq 32 for MSI/MSI-X
Nov 14 21:31:00 vinux kernel: [ 13.693978] ADDRCONF(NETDEV_UP): eth0: link is not ready
Nov 14 21:31:08 vinux kernel: [ 22.036017] eth1: no IPv6 routers present
I don't see a helpful error!
David
On Mon, 14 Nov 2011, Bruno Prémont wrote:
> On Mon, 14 November 2011 "D.J.J. Ring, Jr." <n1ea@arrl.net> wrote:
>> I am sorry Anatolij,
>>
>> I should have said that I DID run sudo update-grub and then I rebooted.
>>
>> When it rebooted, I still have the "no /dev/fb0" error.
>>
>> I apologize for not being thourough in my words.
>
> Please make sure "nomodeset" is no more present on kernel cmdline and
> if it's gone post your corresponding kernel log (at least the relevant
> parts of it like the few first line including cmdline and anything
> that is related to drm, i915, *fb*, vesa or vga)!
>
> Note, with grub you should also be able to edit the kernel cmdline from
> grubs interface before you tell it to boot the kernel.
> You could even attempt to reboot with kexec (where you can choose kernel
> and cmdline as well) if you can't convince grub.
>
> Bruno
>
^ permalink raw reply
* Re: Getting FB to work in Console
From: Bruno Prémont @ 2011-11-14 20:25 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <CADO5RbhunU1X7mWwGDbVRc1FSPKBaLudAVav0TMkBoQ_1zp0Mw@mail.gmail.com>
On Mon, 14 November 2011 "D.J.J. Ring, Jr." <n1ea@arrl.net> wrote:
> I am sorry Anatolij,
>
> I should have said that I DID run sudo update-grub and then I rebooted.
>
> When it rebooted, I still have the "no /dev/fb0" error.
>
> I apologize for not being thourough in my words.
Please make sure "nomodeset" is no more present on kernel cmdline and
if it's gone post your corresponding kernel log (at least the relevant
parts of it like the few first line including cmdline and anything
that is related to drm, i915, *fb*, vesa or vga)!
Note, with grub you should also be able to edit the kernel cmdline from
grubs interface before you tell it to boot the kernel.
You could even attempt to reboot with kexec (where you can choose kernel
and cmdline as well) if you can't convince grub.
Bruno
^ permalink raw reply
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